0% found this document useful (0 votes)
13 views50 pages

Ecen1011 2023 06

This document discusses flip-flop based synchronous networks including registers, shift registers, and counters. Registers can store data in parallel or serial modes using flip-flops. Shift registers can shift data serially for parallel-serial or serial-parallel conversion. Counters generate numerical sequences using flip-flops and are commonly binary up/down counters that can be extended and enabled/disabled. Asynchronous counters provide alternatives to synchronous ripple counters. VHDL is used to model shift registers and counters.

Uploaded by

SANG SANG
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
13 views50 pages

Ecen1011 2023 06

This document discusses flip-flop based synchronous networks including registers, shift registers, and counters. Registers can store data in parallel or serial modes using flip-flops. Shift registers can shift data serially for parallel-serial or serial-parallel conversion. Counters generate numerical sequences using flip-flops and are commonly binary up/down counters that can be extended and enabled/disabled. Asynchronous counters provide alternatives to synchronous ripple counters. VHDL is used to model shift registers and counters.

Uploaded by

SANG SANG
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 50

Chapter 6

Flip-Flop-Based
synChronous networks
31-Oct-23 ECEN1011 232
A flip-flop-based
synchronous network is a
network in which the flip-
flops share the same clock,
and the flip-flop
asynchronous inputs (i.e.,
Clear and Preset) are used
only for their initialization. If
these two conditions are not
met, the network falls into
the category of
asynchronous networks.
31-Oct-23 ECEN1011 233
General
Structure of a
Synchronous
Network

31-Oct-23 ECEN1011 234


Synchronizer
In any case, errors due to metastability are
very rare in well-designed flip-flops in non-
critical conditions. The
average time between two
consecutive errors could be
on the order of hundreds of
years. Since the robability of
an error in the digital circuit due to other
causes (a circuit failure, electromagnetic
disturbance, for example) is much higher, we
can say that signal synchronization through this
technique is generally reliable for many applications.
31-Oct-23 ECEN1011 235
Multistage Synchronization

31-Oct-23 ECEN1011 236


1
Pe   3.17098 E  16
100 year  365day  24hour  3600 second 1MHz

for 100 FFs :


Pe100  1  1  Pe 
100
  3.33067 14
1
 0.952054716 year (347 days) only
Pe100  365day  24hour  3600second 1MHz

for 100, 000 FFs :


Pe100 k  1  1  Pe 
100 k
  3.33067 11
1
 0.000952055 year (8.34 hours) only
Pe100 k  365day  24hour  3600second  1MHz

1, 000, 000, 000 FF  3 seconds only!


31-Oct-23 ECEN1011 237
Flip-Flop-Based
synChronous networks
Registers

31-Oct-23 ECEN1011 238


Registers are important logical structures used to memorize
data. It is possible to “write” binary data on a register, keep it
for a period of time, and “read it” as many times as necessary.
From this perspective, the D flip-flop is also a register, since it
can carry out the operations described on one single bit.

A register is usually made up of a number of flip-flops equal


to the number of bits of the data that needs to be memorized.
Registers allow for two ways to store and retrieve data: the
parallel mode and the serial mode, as we will see in the next
few sections.
31-Oct-23 ECEN1011 239
Parallel Registers
“PIPO”
(Parallel Input –
Parallel Output)

31-Oct-23 ECEN1011 240


8-bit synchronous parallel registers

31-Oct-23 ECEN1011 241


8-bit synchronous parallel registers timing

31-Oct-23 ECEN1011 242


Shift Registers (SHR, serial–parallel
conversion)

“serial” input

31-Oct-23 ECEN1011 243


SHR
timing

SIPO
Serial Input –
Parallel Output

31-Oct-23 ECEN1011 244


8-bit shift registers

“SISO” (Serial Input - Serial Output)


obtain a delayed signal of as many clock cycles

31-Oct-23 ECEN1011 245


both parrallel and serial ciucuit by the help
of multiplexer.

Shift Registers with Parallel Load piso

(parallel–serial conversion)

31-Oct-23 ECEN1011 246


Load

31-Oct-23 ECEN1011 247


Shift

31-Oct-23 ECEN1011 248


8-bit shift registers (PISO)

31-Oct-23 ECEN1011 249


Universal Shift Register

31-Oct-23 ECEN1011 250


Universal Shift Register

31-Oct-23 ECEN1011 251


Maintaining information

31-Oct-23 ECEN1011 252


Right shifting

31-Oct-23 ECEN1011 253


Left shifting

31-Oct-23 ECEN1011 254


Parallel load

31-Oct-23 ECEN1011 255


Shift Register in VHDL (Entity)
entity shift_register is
port ( i_clk : in std_logic;
i_rstb : in std_logic;
i_data : in std_logic_vector(1 downto 0);
o_data : out std_logic_vector(1 downto 0));
end shift_register;

31-Oct-23 ECEN1011 256


Shift Register in VHDL (plain description)
architecture rtl of shift_register is
signal r0_data : std_logic_vector(1 downto 0);
signal r1_data : std_logic_vector(1 downto 0);
signal r2_data : std_logic_vector(1 downto 0);
signal r3_data : std_logic_vector(1 downto 0);
begin
o_data <= r3_data;
p_sreg : process(i_clk,i_rstb)
begin
if(i_rstb='0') then
r0_data <= (others=>'0'); r1_data <= (others=>'0');
r2_data <= (others=>'0'); r3_data <= (others=>'0');
elsif(rising_edge(i_clk)) then
r0_data <= i_data; r1_data <= r0_data ;
r2_data <= r1_data ; r3_data <= r2_data ;
end if;
end process p_sreg;
end rtl;
31-Oct-23 ECEN1011 257
Shift Register in VHDL (description 1)
architecture rtl of shift_register is
begin
p_sreg : process(i_clk, i_rstb)
variable v0_data : std_logic_vector(1 downto 0);
variable v1_data : std_logic_vector(1 downto 0);
variable v2_data : std_logic_vector(1 downto 0);
begin
if(i_rstb='0') then
v0_data := (others=>'0'); v1_data := (others=>'0');
v2_data := (others=>'0'); o_data <= (others=>'0');
elsif(rising_edge(i_clk)) then
o_data <= v2_data ; v2_data := v1_data ;
v1_data := v0_data ; v0_data := i_data;
end if;
end process p_sreg;
end rtl;
31-Oct-23 ECEN1011 258
Shift Register in VHDL (description 2)
architecture rtl of shift_register is
type t_sreg is array(0 to 3) of std_logic_vector(1 downto 0);
signal r_data : t_sreg;
begin
o_data <= r_data(r_data'length-1) ;
p_sreg : process(i_clk,i_rstb)
begin
if(i_rstb='0') then
r_data <= (others=>(others=>'0'));
elsif(rising_edge(i_clk)) then
r_data(0) <= i_data;
for idx in 1 to r_data'length-1 loop
r_data(idx) <= r_data(idx-1) ;
end loop;
end if;
end process p_sreg;
end rtl;
31-Oct-23 ECEN1011 259
Shift Register in VHDL (description 3)
architecture rtl of shift_register is
type t_sreg is array(0 to 3) of std_logic_vector(1 downto 0);
signal r_data : t_sreg;
begin
o_data <= r_data(r_data'length-1) ;
p_sreg : process(i_clk, i_rstb)
begin
if(i_rstb='0') then
r_data <= (others=>(others=>'0'));
elsif(rising_edge(i_clk)) then
r_data <= i_data&r_data(0 to r_data'length-2);
end if;
end process p_sreg;
end rtl;
31-Oct-23 ECEN1011 260
Flip-Flop-Based
synChronous networks
Counters

31-Oct-23 ECEN1011 261


Another commonly used type of sequential network is the
counter. This term indicates a network that generates a
numerical sequence in a particular code (think, for example, of
an increasing sequence made up of binary numbers
represented by a certain number of bits).

The network’s active edge of the clock input causes the


passage from one element of the sequence to the next. The
counter is synchronous when the flip-flop network that
creates it is synchronous.
31-Oct-23 ECEN1011 262
Binary Counters

• binary 4-bit counter


• 16 combinations
• module 16 counting
• up counter

31-Oct-23 ECEN1011 263


31-Oct-23 ECEN1011 264
31-Oct-23 ECEN1011 265
31-Oct-23 ECEN1011 266
cascade driving

maximum operating frequency declines


31-Oct-23 ECEN1011 267
Frequency Divider

31-Oct-23 ECEN1011 268


synchronous, binary, 4-bit up counter with an
added TC (“Terminal Count”) output

31-Oct-23 ECEN1011 269


Counters with
Enabling

multiplexer
31-Oct-23 ECEN1011 270
if i can build a counter
that starts from3 end at15
(never go to 0)

Up/Down
Counters

31-Oct-23 ECEN1011 271


31-Oct-23 ECEN1011 272
31-Oct-23 ECEN1011 273
“Universal”
Counters

31-Oct-23 ECEN1011 274


Counter Extension

31-Oct-23 ECEN1011 275


Bus Versiion

31-Oct-23 ECEN1011 276


Asynchronous Counters

ripple counter

31-Oct-23 ECEN1011 277


Down Counter

31-Oct-23 ECEN1011 278


4-bit up-down binary counter in VHDL (1)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity counter is
Port ( rst,clk,up_dwn : in std_logic;
o: out std_logic_vector(0 to 3));
end counter;

31-Oct-23 ECEN1011 279


4-bit up-down binary counter in VHDL (2)
architecture count_arch of counter is if (up_dwn = ‘1’) then
signal count : std_logic_vector(0 to 3); count <= count – 1;
begin else
process(rst, clk) count <= count + 1;
begin end if;
if (rst = ‘1’) then end if;
count <= “0000”; end process;
elsif (clk’event and clk = ‘0’) then o <= count;
end count_arch;

31-Oct-23 ECEN1011 280


Assignment 5
• P. 228
• 1, 4, 8

31-Oct-23 ECEN1011 281

You might also like