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Lab 4

The document describes several sequential logic circuits including D flip-flops, T flip-flops, counters, shift registers, and latches. RTL code and testbenches are provided for each circuit. The document also covers synthesis models for the described circuits.

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Prithvi Rastogi
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40 views

Lab 4

The document describes several sequential logic circuits including D flip-flops, T flip-flops, counters, shift registers, and latches. RTL code and testbenches are provided for each circuit. The document also covers synthesis models for the described circuits.

Uploaded by

Prithvi Rastogi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Lab4: Sequential Logic (Flip-Flop, Counters, Shift registers)

1. Write an RTL description and test bench for a D flip flop.

RTL CODE :-

module d_flip_flop (Q,D,clk,reset);


input D;
input clk;
input reset;
output reg Q;
always @(posedge clk or posedge reset)
begin
if (reset == 1'b1 )
Q <= 1'b0;
else
Q <= D;
end
endmodule

TESTBENCH :-

module tb;
reg D;
reg clk;
reg reset;
wire Q;
d_flip_flop d1(Q,D,clk,reset);
initial
begin
clk = 1'b0;
forever #20 clk = ~clk ;
end
initial
begin
reset = 1'b1;
#40;
reset = 1'b0;
#40;
D = 1'b0;
#40;
D = 1'b1;
#40;
$display("D=%b, clk=%b, reset=%b, Q=%b",D,clk,reset,Q);
$finish ;
end
endmodule
Simulation result :-

D=1, clk=1, reset=0, Q=1

Synthesis model :-
2. Write structural model for T flip flop using D flip flop.

STRUCTURAL MODEL RTL CODE :-

module dff(D, CLK, RESET, Q, QOUT);


input D, CLK, RESET;
output Q, QOUT;
reg Q, QOUT;
always @ (posedge CLK or posedge RESET)
begin
if(RESET)
begin
Q <= 1'b0;
QOUT <= 1'b1;
end
else
begin
Q <= D;
QOUT <= ~D;
end
end
endmodule

module tff(T, CLK, RESET, Q, QOUT);


input T, CLK, RESET;
output Q, QOUT;
wire out1;
wire out2;
assign out1 = T ^ out2;
dff uut(out1, CLK, RESET, out2, QOUT);
assign Q = out2;
endmodule
Synthesis model :-
3. Write an RTL description for a 4 bit synchronous loadable up
counter and verify using a test bench.

RTL CODE :-

module up_counter(input clk, reset, output[3:0] counter);


reg [3:0] counter_up;
always @(posedge clk or posedge reset)
begin
if(reset)
counter_up <= 4'd0;
else
counter_up <= counter_up + 4'd1;
end
assign counter = counter_up;
endmodule

TESTBENCH :-

module upcounter_testbench();
reg clk, reset;
wire [3:0] counter;
up_counter dut(clk, reset, counter);
initial begin
clk=0;
forever #5 clk=~clk;
end
initial begin
reset=1;
#20;
reset=0;
end
endmodule
Simulation result :-

Synthesis model :-
4. Write an RTL description for JK flip flop using parameter declaration for
the respective scenarios HOLD, SET, RESET, TOGGLE.

RTL CODE :-

module jk_ff(clk,reset,j,k,q,qb);
parameter HOLD=2'b00,
SET=2'b10,
RESET=2'b01,
TOGGLE=2'b11;
input clk,reset,j,k;
output reg q;
output qb;
always@(posedge clk or posedge reset )
begin
if(reset)q<=1'b0;
else
begin
case
({j,k})HOLD:q<=q;
RESET:q<=0;
SET:q<=1;
TOGGLE:q<=~q;
default:q<=q;
endcase
end
end
assign qb=~q;
endmodule

Synthesis model :-
TESTBENCH :-

module jk_ff_tb();
reg clk, reset,j,k;
wire q,qb;
parameter cycle=10;
jk_ff JK1 (clk,reset,j,k,q,qb);
initial
begin
clk = 1'b0;
forever
#(cycle/2) clk=~clk;
end
task rst_dut();
begin
reset=1'b1;
#10;
reset=1'b0;
end
endtask
task din(input x,y);
begin@(negedge clk);
j=x;k=y;
end
endtask
initial
begin
rst_dut;
din(0,0);
din(0,1);
din(1,0);
din(1,1);
din(1,0);
din(0,0);
din(0,1);
din(1,1);
din(0,1);
#10;
$finish;
end
initial
$monitor("clk=%b, Input ->JK=%b%b, Reset = %b, Output ->Q =%b,
Qbar=%b",clk,j,k,reset,q,qb);
Endmodule
Simulation result :-

clk=0, Input ->JK=xx, Reset = 1, Output ->Q =0, Qbar=1


clk=1, Input ->JK=xx, Reset = 1, Output ->Q =0, Qbar=1
clk=0, Input ->JK=00, Reset = 0, Output ->Q =0, Qbar=1
clk=1, Input ->JK=00, Reset = 0, Output ->Q =0, Qbar=1
clk=0, Input ->JK=01, Reset = 0, Output ->Q =0, Qbar=1
clk=1, Input ->JK=01, Reset = 0, Output ->Q =0, Qbar=1
clk=0, Input ->JK=10, Reset = 0, Output ->Q =0, Qbar=1
clk=1, Input ->JK=10, Reset = 0, Output ->Q =1, Qbar=0
clk=0, Input ->JK=11, Reset = 0, Output ->Q =1, Qbar=0
clk=1, Input ->JK=11, Reset = 0, Output ->Q =0, Qbar=1
clk=0, Input ->JK=10, Reset = 0, Output ->Q =0, Qbar=1
clk=1, Input ->JK=10, Reset = 0, Output ->Q =1, Qbar=0
clk=0, Input ->JK=00, Reset = 0, Output ->Q =1, Qbar=0
clk=1, Input ->JK=00, Reset = 0, Output ->Q =1, Qbar=0
clk=0, Input ->JK=01, Reset = 0, Output ->Q =1, Qbar=0
clk=1, Input ->JK=01, Reset = 0, Output ->Q =0, Qbar=1
clk=0, Input ->JK=11, Reset = 0, Output ->Q =0, Qbar=1
clk=1, Input ->JK=11, Reset = 0, Output ->Q =1, Qbar=0
clk=0, Input ->JK=01, Reset = 0, Output ->Q =1, Qbar=0
clk=1, Input ->JK=01, Reset = 0, Output ->Q =0, Qbar=1
5. Write an RTL description and test bench for a SR LATCH.

RTL CODE :-

module SR_latch(R,S,Q,Qnot);
input R, S;
output Q, Qnot;
nand(Qnot, R, Q);
nand(Q, S, Qnot);
endmodule

TESTBENCH :-

module SR_latch_tb;
reg R, S;
wire Q, Qnot;
SR_latch dut(R,S,Q,Qnot);
initial
begin
$dumpfile("latch.vcd");
$dumpvars(1);
$display("S R !Q Q");
$monitor("%b %b %b %b",S,R,Qnot,Q);

#5 R=1'b1; S=1'b0;
#5 R=1'b0; S=1'b1;
#5 R=1'b1; S=1'b1;
#5 R=1'b0; S=1'b0;

#5 $finish;
end
endmodule

Simulation result :-
Synthesis model :-
6. Write a RTL to design 4 bit MOD12 loadable binary up counter and
verify using test bench.

RTL CODE :-

module mod12_up_counter(input clk,input rst,input load,input [3:0] data_in,output [3:0]q);


reg [3:0] count;
always @(posedge clk or posedge rst) begin
if (rst)
count <= 4'b0000;
else if (load)
count <= data_in;
else if (count == 4'b1011)
count <= 4'b0000;
else
count <= count + 1;
end
assign q = count;
endmodule

TESTBENCH :-

module mod12_up_counter_tb;
reg clk, rst, load;
reg [3:0] data_in;
wire [3:0] q;
mod12_up_counter uut(
.clk(clk),
.rst(rst),
.load(load),
.data_in(data_in),
.q(q));
initial begin
$dumpfile("mod12_up_counter_tb.vcd");
$dumpvars(0, mod12_up_counter_tb);
clk = 0;
rst = 1;
load = 0;
data_in = 4'b0000;
#10 rst = 0;
#10 load = 1;
data_in = 4'b1010;
#10 load = 0;
#50 $finish;
end
always #5 clk = ~clk;
endmodule
Simulation result :-

Synthesis model :-
7. Write a RTL to design a 4 bit binary up down counter counter.

RTL CODE :-

module up_down_counter(input clk, reset,up_down, output[3:0] counter);


reg [3:0] counter_up_down;
always @(posedge clk or posedge reset)
begin
if(reset)
counter_up_down <= 4'h0;
else if(~up_down)
counter_up_down <= counter_up_down + 4'd1;
else
counter_up_down <= counter_up_down - 4'd1;
end
assign counter = counter_up_down;
endmodule

TESTBENCH :-

module updowncounter_testbench();
reg clk, reset,up_down;
wire [3:0] counter;
up_down_counter dut(clk, reset,up_down, counter);
initial begin
clk=0;
forever #5 clk=~clk;
end
initial begin
reset=1;
up_down=0;
#20;
reset=0;
#200;
up_down=1;
end
endmodule
Simulation result :-

Synthesis model :-
8. Write an RTL and testbench for 4 bit SISO.

RTL CODE :-

module siso(clk, si, so);


input clk;
input si;
output so;
reg [3:0]q=0;
always@(posedge clk)
begin
q[3]<=si;
q[2]<=q[3];
q[1]<=q[2];
q[0]<=q[1];
end
assign so=q[0];
endmodule

TESTBENCH :-

module sisootb;
reg clk;
reg si;
wire so;
siso uut (.clk(clk), .si(si), .so(so));
initial begin
clk=0;
si=1;
#10;
si=0;
#10;
si=0;
#10;
si=1;
end
always #5 clk=~clk;
endmodule
Simulation result :-

Synthesis model :-

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