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Ece4804 HW2

This assignment involves designing and simulating a sample-and-hold amplifier (SHA) circuit. Students will: 1) Calculate OTA parameters to ensure stability and determine component values for a behavioral SHA model. 2) Simulate the behavioral SHA model and add modifications like a nulling resistor to improve stability. 3) Design a full SHA circuit with switches and simulate its transient response, investigating signal-to-noise ratio. 4) Add a bootstrapped switch and repeat simulations. 5) As a warm-up for an analog VLSI design project, students will lay out a 5T OTA using a provided PDK and simulate its performance as a unity-gain buffer.

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0% found this document useful (0 votes)
115 views3 pages

Ece4804 HW2

This assignment involves designing and simulating a sample-and-hold amplifier (SHA) circuit. Students will: 1) Calculate OTA parameters to ensure stability and determine component values for a behavioral SHA model. 2) Simulate the behavioral SHA model and add modifications like a nulling resistor to improve stability. 3) Design a full SHA circuit with switches and simulate its transient response, investigating signal-to-noise ratio. 4) Add a bootstrapped switch and repeat simulations. 5) As a warm-up for an analog VLSI design project, students will lay out a 5T OTA using a provided PDK and simulate its performance as a unity-gain buffer.

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ECE 4804/8804 AVS: Analog VLSI I: from Theory to Tape-out

Assignment #2
Due: 02-09-2024 11:59pm

This assignment’s objectives are to familiarize with the TI Artisan design flow and to learn to build
SHA behavioral modeling testbench. You will work with an ideal component model library
ECE6414_lib_OA and the TI LBC7 PDK. Watch a supplementary tutorial to learn how to correctly
use the 6414 lib. Please ensure that your submission includes well-defined simulation plots with
marked critical points on the curve. It is essential for your report to be both concise and organized.

1. SHA stability analysis


The first phase in designing an SHA is to develop the OTA and put it in the right feedback
condition (i.e., the charge transfer phase) and ensure it is stable. We can first verify that with a
behavioral-level OTA model, as shown in Figure 1. The ideal Gm-cell model is called OTA_diff.
For simplicity, the caps can be the ideal ones from analogLib.

CF

CC CL
CS
VINP VOP
CMDM

CS Gm Gm
VINM VOM
CL
CC

CF

Figure 1
a. Calculation of OTA parameters: assuming the sampling speed of this SHA is 1 MHz with a 50%-
50% split of the track phase and charge transfer phase. The required dynamic settling error is
0.05% and the static error is 0.05%, respectively. To make it simple let’s preset CF = 1pF, CS =
1pF, CL = 2pF (in real design you need to calculate them from SNR spec). Please calculate the
parameters loop gain (LG), loop gain bandwidth (LGBW), and then determine the value of Gm1,
Gm2 and open-loop gain (Av) of the overall OTA. Notice that to suffice the stability the non-
dominant pole needs to be >3X LGBW. For CC, set it to be 0.35*CL,tot. (Note that CL,tot is not
just CL, but also the loading effect of CS and CF). Show your step-by-step calculation and
summarize the stage parameters neatly.
b. Verification with stb analysis: config the schematic as Figure 1 shows, then use CMDM probe
(in analogLib) to break the loop at the input of the first-stage Gm. Perform an STB simulation
using the value that you obtain from 1-a. Then, inspect the LG, LGBW, and LG phase margin.
Does it match the calculation result? For both Gm cell, press Q to set the FT = 3G and gmID =10
and allocate the first-stage gain 10X larger than second-stage gain. Connect the ‘vcmo’ pin to 0V.
c. Add a nulling resistor in series with CC with a value of 1/Gm2. Inspect the LG phase margin
and see if there’s any improvement.

2. SHA Transient Analysis


a. Modify the schematic from problem1 to a full SHA with ideal switches (use the 100-Ohm one
provided in the ECE6414_lib_OA) as Figure 2 shows. Use the parameters that you calculated
in 1-a for this question and set the CL = 0.35*CL. Setup a differential input sinusoidal wave
with Vpp = +/-2V and VCM = 2V, with frequency at 11/128*1MHz (you can use the ‘S2D’
block to create this signal). You can set up the switch control signals using the ‘CLK_Gen’
block easily. In this problem we will set the ‘vcmo’ pins for Gm1 and Gm2 to both 2V. Then
perform the transient simulation with sufficient time to obtain slightly more than 128 samples.
Investigate the SNR and spectrum (128pt) for both transient-noise on and off.

CF
VCM VCM VCM

PH2 PH1E CC PH1


CL
CS
VINP VOP
PH1 Gm1 Gm2 PH1 PH2
CS
VINM VOM
CL PH1
PH2 PH1E CC

VCM VCM VCM


CF

Figure 2

b. Replace the very left signal tracking switches with a semi-ideal bootstrapped MOS switch as
shown in Figure 3 (which you need to build by yourself). Use the NCH_5V in the lbc7 library
for the MOS switch and repeat the previous transient simulation. Set the Cboot = 250fF and
VDD = 5V. For NCH_5V device, the body should be connected to ground (0V).
VDD

PH1B PH1B
PH1

Cboot
To CS
PH1B
VIN

Figure 3

3. LBC7 Process Design Warm Up


Design a 5T D2S OTA using LBC7 5V transistors (NCH_5V_ISO, PCH_5V) as Figure 5 shows.
The ISO NMOS allows you to connect the body to source to minimize the body effect. Configure
this amplifier into a unity-gain buffer with close-loop BW = 50 MHz. Use 5V as VDD and 2pF as
the output loading. Make the small-signal closed-loop gain better than 0.95 (verify with AC
simulation). Summarize the current and sizing in a table.
Nore: make sure your input has a reasonable DC bias when you run the simulation.

VDD

VIN
VOUT
VOUT OTA

VIN+ VIN- CL = 2pF

Figure 4

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