Ece4804 HW2
Ece4804 HW2
Assignment #2
Due: 02-09-2024 11:59pm
This assignment’s objectives are to familiarize with the TI Artisan design flow and to learn to build
SHA behavioral modeling testbench. You will work with an ideal component model library
ECE6414_lib_OA and the TI LBC7 PDK. Watch a supplementary tutorial to learn how to correctly
use the 6414 lib. Please ensure that your submission includes well-defined simulation plots with
marked critical points on the curve. It is essential for your report to be both concise and organized.
CF
CC CL
CS
VINP VOP
CMDM
CS Gm Gm
VINM VOM
CL
CC
CF
Figure 1
a. Calculation of OTA parameters: assuming the sampling speed of this SHA is 1 MHz with a 50%-
50% split of the track phase and charge transfer phase. The required dynamic settling error is
0.05% and the static error is 0.05%, respectively. To make it simple let’s preset CF = 1pF, CS =
1pF, CL = 2pF (in real design you need to calculate them from SNR spec). Please calculate the
parameters loop gain (LG), loop gain bandwidth (LGBW), and then determine the value of Gm1,
Gm2 and open-loop gain (Av) of the overall OTA. Notice that to suffice the stability the non-
dominant pole needs to be >3X LGBW. For CC, set it to be 0.35*CL,tot. (Note that CL,tot is not
just CL, but also the loading effect of CS and CF). Show your step-by-step calculation and
summarize the stage parameters neatly.
b. Verification with stb analysis: config the schematic as Figure 1 shows, then use CMDM probe
(in analogLib) to break the loop at the input of the first-stage Gm. Perform an STB simulation
using the value that you obtain from 1-a. Then, inspect the LG, LGBW, and LG phase margin.
Does it match the calculation result? For both Gm cell, press Q to set the FT = 3G and gmID =10
and allocate the first-stage gain 10X larger than second-stage gain. Connect the ‘vcmo’ pin to 0V.
c. Add a nulling resistor in series with CC with a value of 1/Gm2. Inspect the LG phase margin
and see if there’s any improvement.
CF
VCM VCM VCM
Figure 2
b. Replace the very left signal tracking switches with a semi-ideal bootstrapped MOS switch as
shown in Figure 3 (which you need to build by yourself). Use the NCH_5V in the lbc7 library
for the MOS switch and repeat the previous transient simulation. Set the Cboot = 250fF and
VDD = 5V. For NCH_5V device, the body should be connected to ground (0V).
VDD
PH1B PH1B
PH1
Cboot
To CS
PH1B
VIN
Figure 3
VDD
VIN
VOUT
VOUT OTA
Figure 4