MC33290 XX
MC33290 XX
MC33290 XX
Rev 3, 08/2002
SEMICONDUCTOR TECHNICAL DATA
33290
ISO K Line Serial Link Interface
The 33290 is a serial link bus interface device designed to provide bi-
directional half-duplex communication interfacing in automotive diagnostic
applications. It is designed to interface between the vehicle’s on-board
microcontroller and systems off-board the vehicle via the special ISO K line. ISO K LINE SERIAL LINK
The 33290 is designed to meet the Diagnostic Systems ISO9141 specification. INTERFACE
The device’s K line bus driver’s output is fully protected against bus shorts and
overtemperature conditions.
The 33290 derives its robustness to temperature and voltage extremes by
being built on a SMARTMOS process, incorporating CMOS logic, bipolar/
MOS analog circuitry, and DMOS power FETs. Although the 33290 was
principally designed for automotive applications, it is suited for other serial
communication applications. It is parametrically specified over an ambient
temperature range of -40°C ≤ TA ≤ 125°C and 8.0 V ≤ VBB ≤ 18 V supply. The
economical SO-8 surface-mount plastic package makes the 33290 very cost
effective. D SUFFIX
PLASTIC PACKAGE
Features CASE 751
• Designed to Operate Over Wide Supply Voltage of 8.0 to 18 V (SO-8)
• Ambient Operating Temperature of -40 to 125°C
• Interfaces Directly to Standard CMOS Microprocessors
• ISO K Line Pin Protected Against Shorts to Ground ORDERING INFORMATION
• Thermal Shutdown with Hysteresis
Temperature
• Maximum Transmission Speeds in Excess of 50 k Baud Device
Range (TA)
Package
• ISO K Line Pin Capable of High Currents
• ISO K Line Can Be Driven with up to 10 nF of Parasitic Capacitance MC33290D -40 to 125°C SO-8
• 8.0 kV ESD Protection Attainable with Few Additional Components
• Standby Mode: No VBat Current Drain with VDD at 5.0 V
• Low Current Drain During Operation with VDD at 5.0 V
Components necessary for Reverse Battery (1), Overvoltage Transient (2), and 8.0 kV
ESD Protection (3) in a metal module case. This device contains 85 active transistors.
1 50 V 20 V
200 Ω Rx
6
10 V 10 V
ISO
RHys
Master
Bias
CEN
8 40 V
VDD 125 kΩ
Thermal
Shutdown GND
7
125 kΩ 3
Tx 2.0 kΩ
5 10 V 10 V
ISO 44 55 CEN
8 CEN Chip enable. Logic “1” for active state. Logic “0” for sleep state.
Notes:
1. NC pins should not have any connections made to them. NC pins are not guaranteed to be open circuits.
Power Dissipation PD W
TA = 25°C 0.8
Notes:
2. Device will survive double battery jump start conditions in typical applications for 10 minutes duration, but is not guaranteed to remain within
specified parametric limits during this duration.
3. ESD data available upon request.
4. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).
5. ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
6. Nonrepetitive clamping capability at 25°C.
7. Lead soldering temperature limit is for 10 seconds maximum duration. Contact Motorola Sales Office for device immersion soldering time/
temperature limits.
Chip Enable V
Input High-Voltage Threshold (Note 8) VIH(CEN) 0.7 VDD – –
Input Low-Voltage Threshold (Note 9) VIL(CEN) – – 0.3 VDD
Notes:
8. When IBB transitions to >100 µA.
9. When IBB transitions to <100 µA.
10. Enable pin has an internal current pull-down equivalent to greater than 50 kΩ.
11. Measured by ramping TX down from 0.7 VDD and noting TX value at which ISO falls below 0.2 VBB.
12. Measured by ramping TX up from 0.3 VDD and noting the value at which ISO rises above 0.9 VBB.
13. Tx pin has internal current pull-up equivalent to greater than 50 kΩ. Pull-Up current measured with TX pin at 0.7 VDD.
14. Thermal Shutdown performance (TLIM) is guaranteed by design but not production tested.
Notes:
15. ISO ramped from 0.8 VBB to 0.4 VBB, Monitor RX, Value of ISO voltage at which RX transitions to 0.3 VDD.
16. ISO ramped from 0.4 VBB to 0.8 VBB, Monitor RX, Value of ISO voltage at which RX transitions to 0.7 VDD.
17. Input Hysteresis, VHys(ISO) = VIH(ISO) - VIL(ISO).
18. ISO has internal current limiting.
Notes:
19. Time required ISO voltage to transition from 0.8 VBB to 0.2 VBB.
20. Changes in the value of CISO affect the rise and fall time but have minimal effect on Propagation Delay.
21. Step TX voltage from 0.2 VDD to 0.8 VDD. Time measured from VIH(ISO) until VISO reaches 0.3 VBB.
22. Step TX voltage from 0.8 VDD to 0.2 VDD. Time measured from VIL(ISO) until VISO reaches 0.7 VBB.
0.6 1.2
Figure 2. ISO Input Threshold/VBB vs. Temperature Figure 4. ISO Fall Time vs. Temperature
0.95 0.7
tPD(ISO), PROPAGATION DELAY (µs)
0.9 0.6
VDD = 5.25 V, VBB = 18 V
VDD = 4.75 V, VBB = 8.0 V
0.85
0.5
0.8
0.4
0.75
VDD = 4.75 V, VBB = 8.0 V
0.3
0.7 VDD = 5.25 V, VBB = 18 V PdL-H
VDD = 4.75 V, VBB = 8.0 V
0.65 0.2
-50 0 50 100 150 -50 0 50 100 150
TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)
Figure 3. ISO Output/VBB vs. Temperature Figure 5. ISO Propagation Delay vs. Temperature
FUNCTIONAL DESCRIPTION
The 33290 transforms 5.0 V microcontroller logic signals to In the receive mode, all ISO K Line bus input signals greater
battery level logic signals and visa versa. This serial link than the 0.7 x VBB thresholds are valid for a high-level signal
interface device, operating in a typical automotive diagnostic and less than the 0.4 x VBB thresholds for a low-level signal. In
application, operates at bit rates up to 10.4 kbps with less than the transmit mode, valid ISO K line bus output signal levels are
2.0 µs propagation delay and less than 2.0 µs fall time. Rise greater than 0.95 x VBB and less than 0.1 x VBB. A pull-up
time is a function of the resistor used in the application to pull resistor of ≥ 100 kΩ to battery is internally provided as well as
up the bus to battery voltage, working in conjunction with the an active data pull-down. The internal active pull-down is
total capacitance present on the bus. The serial link interface current-limit-protected against shorts to battery and further
will remain fully functional over a battery voltage range of 6.0 to protected by thermal shutdown. Typical applications have
18 V. The device is parametrically specified over a dynamic VBB reverse battery protection by the incorporation of an external
voltage range of 8.0 to 18 V. 510 Ω pull-up resistor and diode to battery.
Required input levels from the microcontroller are ratio- Reverse battery protection of the device is provided by using
metric with the VDD voltage normally used to power the a reverse battery blocking diode [(D) in the Simplified
microcontroller. This enhances the 33290’s ability to remain in Application Diagram on page 1]. Battery line transient
harmony with the RX and TX control input signals of the protection of the device is provided for by using a 45 V zener
microcontroller. The RX and TX control inputs are compatible and a 500 Ω resistor connected to the VBB source as shown in
with standard 5.0 V CMOS circuitry. For fault-tolerant purposes the same diagram. Device ESD protection from the
the TX input from the microcontroller has an internal passive communication lines exiting the module is through the use of
pull-up to VDD of approximately 125 kΩ, while the CEN input the 10 nF connected to the VBB device pin and the 5.0 nF used
has an internal passive pull-down to ground of approximately in conjunction with the 27 V zener connected to the ISO pin.
125 kΩ.
D SUFFIX
(8-LEAD SOIC)
PLASTIC PACKAGE
CASE 751-06
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
A D
C Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETER.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
8 5 PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
E H 0.25 M B M 5. DIMENSION B DOES NOT INCLUDE DAMBAR
1 PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
4 SHALL BE 0.127 TOTAL IN EXCESS OF THE B
DIMENSION AT MAXIMUM MATERIAL CONDITION.
h X 45 °
MILLIMETERS
B θ
e DIM MIN MAX
A 1.35 1.75
A1 0.10 0.25
A
C B 0.35 0.49
SEATING C 0.19 0.25
PLANE D 4.80 5.00
L E 3.80 4.00
0.10 e 1.27 BSC
H 5.80 6.20
A1 B h 0.25 0.50
L 0.40 1.25
0.25 M C B S A S θ 0° 7°
MC33290/D
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