System Programming Course Code: CS609

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Lecture #7

The microprocessor package has many signals for data, control and addresses. Some of
these signals may be input signals and some might be output. Hardware interrupts make
use of two of such input signals namely NMI (Non maskable Interrupt) &
INTR(Interrupt Request).

Reset

Hold
NMI Microprocessor

INTR
NMI is a higher priority signal than INTR, HOLD has even higher priority and RESET
has the highest priority. If any of the NMI or INTR pins are activated the microprocessor
is interrupted on the basis of priority, if no higher priority signals are present. This is how
microprocessor can be interrupted without the use of any software instruction hence the
name hardware interrupts.

Hardware Interrupt and Arbitration

Most of the devices use the INTR line. NMI signal is used by devices which perform
operations of the utmost need like the division by zero interrupt which is generated by
ALU circuitry which performs division. Definitely this operation is not possible and the
circuitry generates an interrupt if it receives a 0 as divisor from the control unit.
INTR is used by other devices like COM ports LPT ports, keyboard, timer etc. Since only
one signal is available for microprocessor interruption, this signal is arbitrated among
various devices. This arbitration can be performed by a special hardware called the
Programmable Interrupt Controller (PIC).

Interrupt Controller
A single interrupt controller can arbitrate among 8 different devices.

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D0 IRQ0

PIC
D7

INT IRQ7

As it can be seen from the diagram above the PIC device has 8 inputs IRQ0-IRQ7. IRQ0
has the highest priority and IRQ7 has the lowest. Each IRQ input is attached to an I/O
device whenever the device requires an I/O operation it sends a signal to the PIC. The
PIC on the basis of its priority and presence of other requests decides which request to
serve. Whenever a request is to be served by PIC it interrupt the processor with the INT
output connected to the INTR input of the processor and send the interrupt # to be
generated the data lines connected to the lower 8 datelines of the data bus to inform the
processor about the interrupt number. In case no higher priority signal is available to the
processor and the processor is successfully interrupted the microprocessor sends back an
INTA (interrupt Acknowledge) signal to inform the PIC that the processor has been
interrupted.
The following diagram also shows the typical connectivity of the IRQ lines with various
devices

Interval Timer
0 IRQ1
KBD Controller
1
DO
2
MICRO
COM2 3 D7 PROCESSOR
PIC
COM1 4
INT INTR
5
Other
6 INTA
Controllers
Printer Controller 7 IRQ7

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In standard PCs there maybe more than 8 devices so generally two PIC are used for INTR
line arbitration. These 2 PICs are cascaded such that they collectively are able to arbitrate
among 16 devices in all as shown in the following diagram.
MASTER IRQO
DO

PIC IRQ7
D7 cas1
cas2
INTA cas3

DO IRQ8

D7 PIC IRQ15
cas1
INTA cas2
cas3
SLAVE

The PICs are cascaded such that a total of 16 IRQ levels can be provided number IRQ0-
IRQ15. The IRQ level 2 is used to cascade both of the PIC devices. The Data lines are
multiplexed such that the interrupt number is issued by the concerned PIC. The IRQ 2
input of the Master PIC is connected to the INT output of the Slave PIC. If the slave PIC
is interrupted by a device its request ins propagated to the master PIC and the master PIC
ultimately interrupts the processor on INTR line according to the priorities.
In a standard PC the PICs are programmed such that the master PIC generated the
interrupt number 8-15 for IRQ0 –IRQ7 respectively and the slave PIC generates interrupt
number 70-77H for IRQ8-IRQ15

Hardware Interrupts are Non-Preemptive

As described earlier IRQ 0 has the highest priority and IRQ 15 has the lowest priority. If
a number of requests are available instantaneously the request with higher priority will be
sent for service first by the PIC. Now what will happen if a lower priority interrupt is
being service and a higher priority interrupt request occurs, will the lower priority
interrupt be preempted? The answer is that the interrupt being serviced will not be
preempted no matter what. The reason for this non-preemptive can be understood by the
example illustrated as below. Lets first consider that the hardware interrupts are
preemptive for argument sake. If a character ‘A’ is input a H/W interrupt will occur to
process it, while this interrupt is being processed another character is input say ‘B’ in case
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the interrupts have been preemptive the previous instance will be preempted and another
instance for the H/W interrupt call will be generated, and similarly consider another
character is input ‘C’ and the same happened for this input as well. In this case the
character first to be fully processed and received will be ‘C’ and then ‘B’ will be
processed and then ‘A’. So the sequence of input will change to CBA while the correct
sequence would be ABC.

C PRESSED

A PRESSED

B PRESSED

Input received C B A Logically Incorrect

Logically Correct ABC

The input will be received in correct sequence only if the H/W interrupts are non-
preemptive as illustrated in the diagram below.

A PRESSED

B PRESSED

C PRESSED

Input received A B C Logically Correct

Hardware interrupts requires something more to be programmed into them as compared

with software interrupts. The major difference is because of the reason given above that
the H/W interrupts are non-preemptive. To make them non-preemptive the PIC should
know when the previously issued interrupt returns. The PIC cannot issue the next pending
interrupt unless it is notified that the previous interrupt has returned.

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Who Notifies EOI (End of interrupt)

The PIC has to be notified about the return of the previous interrupt by the ISR routine.
From programmer point of view this is the major difference between H/W and software
interrupt. A software interrupt will not require any such notification. As the diagram
below illustrates that every interrupt returns with an IRET instruction. This instruction is
executed by the microprocessor and has no linkage with the PIC. So there has to be a
different method to notify the PIC about the End of interrupt.

Pending Hardware interrupts.

While a hardware interrupt is being processed a number of various other interrupt maybe
pending. For the subtle working of the system it is necessary for the In-service hardware
interrupt to return early and notify the PIC on return. If this operation takes long and the
pending interrupt requests occur repeated there is a chance of loosing data.

Programming the PIC

To understand how the PIC is notified about the end of interrupt lets take a look into the
internal registers of PIC and their significance. A PIC has a number of initialization
control words (ICW) and operation control words (OCW), following is characteristic of
ICW and OCWs
• ICW programmed at time of boot up
• ICW are used to program the operation mode like cascade mode or not also it is
used to program the function of PIC i.e if it is to invoke interrupts 08~ 0FH or
70-77H on IRQ request.
• OCW are used at run-time.
• OCW is used signal PIC EOI
• OCW are also used to read/write the value of ISR(In-service register),
IMR(interrupt mask register), IRR(interrupt request register).

To understand the ISR, IMR and IRR lets take a look at the following diagram illustrating
an example.
7 6 5 4 3 2 1 0
ISR 0 0 0 1 0 0 0 0

7 6 5 4 3 2 1 0
IMR 0 0 0 0 0 0 1 0

7 6 5 4 3 2 1 0
IRR 1 1 0 0 0 1 0 1

The values shown in the various registers illustrate that the currently in-service interrupt
is that generated through IRQ4 of the PIC (int 0CH in case of mater PIC), also the
interrupt through IRQ1 has been masked (int 9h (keyboard interrupt) in case of master
PIC) which means that even though a request for this interrupt is received by the PIC but
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this request is ignored by the PIC until this bit is cleared. And the requests through IRQ7,
IRQ6, IRQ2 and IRQ0 are pending and waiting for the previously issued interrupt to
return.

Port Addresses
Few of the operation control words can be altered after boot time. The addresses for these
OCW are listed as below

• Master PIC has two ports

20H=OCW for EOI
21H=OCW for IMR
• Slave PIC has two ports as well
A0H=OCW for EOI code
A1H=OCW for IMR

Let’s now discuss an example that accesses these ports to control the PIC

#include <stdio.h>
#include <bios.h>
void main()
{

outport(0x21,0x02);

This example simply accesses the bit # 1 of IMR in the master PIC. It sets the bit #1 in
IMR which masks the keyboard interrupt. As a result no input could be received from the
keyboard after running this program.

Lets now look at another example

#include <dos.h>
#include <stdio.h>
#include <bios.h>
void interrupt(*oldints)();
void interrupt newint8();
int t=0; //corrected
void main()
{
oldints=getvect(0x08);

setvect(0x08,newint8);
keep(0,1000);
}
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void interrupt newint8()

{
t++:
if (t==182)
{
outport(0x21,2);
}
else{
if (t==364)
{
outport(0x21,0);
t=0;
}
}
(*oldints)();
}

The example above is also an interesting example. This program intercepts the timer
interrupt. The timer interrupt makes use of a variable to keep track of how much time has
passed; t is incremented each time int 8 occurs. It the reaches the 182 after 10 second, at
this point the keyboard interrupt is masked and remains masked for subsequent 10 second
at which point the value of t will be 364, also t is cleared to 0 for another such round.

#include <dos.h>
void interrupt(*old)();
void interrupt newint9();
char far *scr=(char far *) 0x00400017;

void main()
{
old=getvect(0x09);
setvect(0x09,newint9);
keep(0,1000);
}
void interrupt newint9()
{
if (inportb(0x60)==83
&&(((*scr)&12)==12)) //corrected
{
outportb(0X20,0x20);
return;
}
(*old)();
}

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The above program disables the CTRL+ALT+DEL combination in the DOS environment
(if windows OS is also running this combination will not be disabled for its
environment). The keyboard interrupt has been intercepted, whnever the keyboard
interrupt occurs the newint9 function receives the scan key code from the keyboard port
0x60, 83 is the scan key code of DEL key. Also the program checks if the ALT and CTRL
button has been pressed as well from the status of the 40:17H keyboard status byte. If it
confirms that the combination pressed is CTRL+ALT+DEL then it does not invoke the
real int 9 ( *oldint() which will make the computer reboot in DOS environment had the
computer been booted through DOS) and simply returns. But notice that before returning
it notifies the PIC that the interrupt has ended. The EOI code sent to the OCW at the
address 0x20 is also 0x20. This is being done because int 9 is a hardware interrupt, had
this been a software interrupt this would have not been required.

#include <dos.h>

void interrupt(*old)();

void interrupt newint9();

void main()
{

old=getvect(0x09);
setvect(0x09,newint9);
keep(0,1000);

}
void interrupt newint9()
{

if (inportb(0x60)==0x1F) //corrected

outportb(0X20,0x20);
return;
}
(*old)();

The above C language program suppresses the ‘s’ input from the keyboard. The keyboard
interrupt has been intercepted. When a key is pressed newint9 is invoked. This service
checks the value through the import statement of the keyboard port numbered 0x60. If he
scan code ( and not the ASCII code) is 0x1F then it indicates that the ‘s’ key was pressed.

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This program in this case simply returns the newint9 hence suppressing this input by not
calling the real int 9. Before return it also notifies the PIC about the end of interrupt.

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