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    Lecture 5 MoSFET-Circuits

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    fahad00navas
    The document discusses MOSFET circuits. It mentions that while the leakage current of a single transistor is low, the leakage current becomes significant when there are millions of transistors in an integrated circuit due to the cumulative effect. It also discusses the linear and saturation regions for n-MOS and p-MOS transistors based on drain-source voltage and gate-source voltage. An inverter circuit is described as having low power consumption when the output transition from 0V to VDD is abrupt, with power only consumed during the transition. Noise margin values are important specifications for inverters, with larger values being preferred.

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    Lecture 5 MoSFET-Circuits

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    fahad00navas
    55 views22 pages
    The document discusses MOSFET circuits. It mentions that while the leakage current of a single transistor is low, the leakage current becomes significant when there are millions of transistors in an integrated circuit due to the cumulative effect. It also discusses the linear and saturation regions for n-MOS and p-MOS transistors based on drain-source voltage and gate-source voltage. An inverter circuit is described as having low power consumption when the output transition from 0V to VDD is abrupt, with power only consumed during the transition. Noise margin values are important specifications for inverters, with larger values being preferred.

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    The document discusses MOSFET circuits. It mentions that while the leakage current of a single transistor is low, the leakage current becomes significant when there are millions of transistors in an integrated circuit due to the cumulative effect. It also discusses the linear and saturation regions for n-MOS and p-MOS transistors based on drain-source voltage and gate-source voltage. An inverter circuit is described as having low power consumption when the output transition from 0V to VDD is abrupt, with power only consumed during the transition. Noise margin values are important specifications for inverters, with larger values being preferred.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    55 views22 pages

    Lecture 5 MoSFET-Circuits

    Uploaded by

    fahad00navas
    The document discusses MOSFET circuits. It mentions that while the leakage current of a single transistor is low, the leakage current becomes significant when there are millions of transistors in an integrated circuit due to the cumulative effect. It also discusses the linear and saturation regions for n-MOS and p-MOS transistors based on drain-source voltage and gate-source voltage. An inverter circuit is described as having low power consumption when the output transition from 0V to VDD is abrupt, with power only consumed during the transition. Noise margin values are important specifications for inverters, with larger values being preferred.

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    © All Rights Reserved
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    Download as pdf or txt
    of 22

    EC4066D Nanoelectronics

    Lecture 5: MoSFET - Circuits

    Dr. Venu Anand


    Room No.202, ECED block I
    [email protected]
    Current IDS is expressed in
    µA/µm
    Two different Vth
    related to linear and
    saturation regions
    Even though the off current of a single transistor
    is low, with millions of transistors, this leakage
    current becomes significant
    DIBL = ΔVT / ΔVDS
    Vin = pulse (0,VDD )

    Although the leakage current of a


    single transistor is low, a million of
    them inside and IC will cause a
    significant leakage current

    For n-MOS
    VDS < VGS-|VT| (linear)
    VDS>VGS-|VT| (saturation)
    For p-MOS
    VSD < VSG-|VT| (linear)
    VSD>VSG-|VT| (saturation)

    So at Vin = 0V, p-MOS is in linear


    region and n-MOS is cut-off
    At Vin=VDD, p-MOS is cut-off and n-
    MOS is in linear region
    Ideal transfer
    characteristic
    Sudden transition from (3) to (4) indicating a
    good inverter

    When Vout = 0, IDS ~ 0


    Vout = VDD, IDS ~ 0
    So power is consumed during the transition
    only. If the transition can be made abrupt,
    power consumption will be low
    For low Vin, the point from Vin = 0 until the
    slope = -1 can be considered as the low
    noise margin
    For high Vin, the point from the slope = -1
    to Vin = VDD can be considered as the high
    noise margin

    Large noise margin values are preferred

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