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 B.E. (Electronics & Telecommunication / Electronics & Communication Engineering)
Seventh Semester (C.B.S.)
Elective - I : VLSI Signal Processing
P. Pages : 2 TKN/KS/16/7545
Time : Three Hours *1036* Max. Marks : 80
_____________________________________________________________________
Notes : 1. All questions carry marks as indicated.
2. Solve Question 1 OR Questions No. 2.

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3. Solve Question 3 OR Questions No. 4.
4. Solve Question 5 OR Questions No. 6.
5. Solve Question 7 OR Questions No. 8.
6. Solve Question 9 OR Questions No. 10.

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7. Solve Question 11 OR Questions No. 12.
8. Assume suitable data whenever necessary.
9. Use of non programmable calculator is permitted.

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1. a) Explain how pipelining can be used for reducing power consumption. 4

b) Consider the 4 tap filter shown in figure (a). Draw its two way parallel version. What can 9
power saving be achieved if we maintain the same sampling rate?
x (n)

h3
en h2 h1 h0
ud
D D D
y (n)
Fig. (a)

OR
2. a) Explain Parallel processing for Low Power. 6
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b) Design a parallel system with 7

L (level of parallel processing) = 3
n (iteration factor) = 3 k
where k = no. of clock cycle.
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3. a) Explain properties of Retiming. 4

b) Consider the data flow graph, construct the matrix W(U, V) and D (U, V) by manual 10
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inspection construct the set of unequilities for clock cycle of 2. Solve the unequilities by
creating a constraint graph and using Bellman – Ford algorithm find retimed graph.
(1)
1

D
Na

D
2D
(1) 2 3
(2)

Fig. (b)

4
(2)

OR
4. Explain in detail : 14
a) Retiming for clock period minimization. b) Retiming for Register minimization.

TKN/KS/16/7545 1 P.T.O
5. a) Unfold the DFG shown in figure below using unfolding factor 4. 9
D B
A
2D
3D
C

b) Explain in short unfolding Transformation. 4

OR
6. a) Explain how unfolding can be used to design word level parallel processing. 8

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b) Give the properties of unfolding. 5

7. a) Explain register minimization in folded architectures. 5

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b) Consider a DSP program that perform the transpose operation of 3 x 3 matrix, find minimum 8
number of registers required to implement the DSP program & give its folded architectures.

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a b c
The Matrix   d e f 
 
 g h i 
OR
8. a)

b)
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Explain the procedure for folding of multirate system.

Design folded biquad filter by systematic folding technique for the figure shown below.
5

8
(S1/3) (S1/1)
ud
IN D OUT
1 2
a D b

3 5 6
(S1/2) D (S1/0)
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(S2/0) (S2/2) 4
c d
D D
7 8
D
(S2/3) (S2/1)
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Fig. (c)

9. a) Construct a 2 x 2 convolution algorithm using Cook-Toom algorithm with   0,  1 10

b) What is the significance of Winograd algorithm. 4

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OR
10. a) Construct 2 x 3 linear convolution algorithm using Winograd algorithm with 14
m(P)  P(p 1) (p2 1)
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11. a) Construct a 4 x 4 cyclic convolution algorithm using CRT with 13

4 2
m(p)  P 1  (p 1) (p  1) (p  1)
OR
12. a) Construct a 3 x 3 fast convolution algorithm by inspection. 9

b) Give Iterated convolution Algorithm. 4

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TKN/KS/16/7545 2
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