DLD LAB MANUAL Dept.

OF ECE,GIET

lOMoARcPSD|1806675
EXPERIMENT NO-1
Realization of Logic circuit to generate r’s Compliment using Logic Gates. Aim:
To generate r’s compliment using logics gates
Apparatus:

S.No. Name of the Type/ Quantity

Apparatus/Component Range
1 Digital Trainer Kit with Digital 1
bread board Trainer
Kit
2 Integrated Circuit(s) IC 7486 1
IC 7404 1
3 Connecting Wires Single as required
strand
4 Patch Cords 4mm as required

Theory:
1’s (r-1’s) Complement of a binary number:
The ones' complement of a binary number is the value obtained by inverting all the bits in
the binary representation of the number (swapping 0s and 1s). The name "ones' complement"
refers to the fact that such an inverted value, if added to the original, would always produce an
"all ones" number (the term "complement" refers to such pairs of mutually additive inverse
numbers, here in respect to a non-0 base number).
2’s (r’s) Complement of a binary number:
There is a simple algorithm to convert a binary number into 2's complement. To get 2's
complement of a binary number, simply invert the given number and add 1 to the least
significant bit (LSB) of given result.

Pin diagram:
DLD LAB MANUAL Dept. OF ECE,GIET

Circuit diagram:

Truth table:

Inputs Output
A 1 A1 Y=(A1)’
(Logic
High)
0 1 1 0
1 1 0 1

Procedure:
1. Make connections as shown in the circuit diagram.
2. Provide the input data via the input switches and observe the output on output LEDs
3. Verify the Truth Table.

Result: r’s compliment using logic gates is designed and truth table is verified.

Viva Questions:

1. What is radix complement?

2. What is diminished radix complement?
3. How to represent signed binary numbers?
DLD LAB MANUAL Dept. OF ECE,GIET

EXPERIMENT NO-2

Realization of given Boolean function using universal gates and minimizing the same.
Compare the gate count before and after minimization.

Aim: 1. To realize given Boolean function using universal gates.

2. To compare the gate count before and after minimization of a given Boolean
function using universal gates.

Apparatus:

S.No Name of the Type/ Quantity

Apparatus/Component Range
1 Digital Trainer Kit with bread board Digital 1
Trainer
Kit
2 Integrated Circuit(s) IC 7400 3

3 Connecting Wires Single as

strand require
d
4 Patch Cords 4mm as required

THEORY:

In Boolean algebra, the NAND and NOR gates are called universal gates because any digital circuit can
be implemented by using any one of these two gates.

NAND Gate: The NAND gate represents the complement of the AND operation. Its name is an
abbreviation of NOT AND.

The truth table and the graphic symbol of NAND gate is shown in the figure.
DLD LAB MANUAL Dept. OF ECE,GIET

NOR Gate: The NOR gate represents the complement of the OR operation. Its name is an
abbreviation of NOT OR.

The truth table and the graphic symbol of NOR gate is shown in the figure.

Karnaugh maps are the most extensively used tool for simplification of Boolean functions. In an
n- variable K-map there are 2ⁿ cells. Each cell corresponds to one of the combinations
of n variable, since there are 2ⁿ combinations of n variables. A Boolean function can be
represented by a Karnaugh map in which each cell corresponds to a minterm. The cells are
arranged in such a way that any two immediately adjacent cells correspond to two minterms of
distance 1.

Boolean function: Y= A’B’C’+A’B’C+A’BC’+AB’C’+ABC’

Simplification of Boolean function using Boolean

algebra: Y= A’B’C’ + A’B’C + A’BC’ + AB’C’ + ABC’

Y= A’B’C’ + AB’C’ + A’BC’ + ABC’ + A’B’C
Y= B’C’ (A’+A) + BC’ (A’+A) +
A’B’C Y= B’C’ + BC’ +
A’B’C Y= C’ (B + B’) +
A’B’C Y= C’ +
A’B’C Y= C’+ A’B’

Simplification using K-map:

After simplifying using K-Map method, we get Y= C’ + A’B’

Pin diagram:
DLD LAB MANUAL Dept. OF ECE,GIET

Circuit diagram of Boolean function using NAND gates before minimization:

Circuit diagram of Boolean function using NAND gates after minimization:

DLD LAB MANUAL Dept. OF ECE,GIET

Procedure:
1. Design Logic circuit using universal gates without minimization of Boolean function.
2. Simplify the given Boolean expression using 3 Variable K-Map to minimize the number
of literals in the given expression and design the circuit using universal gates.
3. Check the components for their working. Insert the appropriate IC into the IC base.
4. Make connections as shown in the circuit diagram.
5. Provide the input data via the input switches and observe the output on output LEDs
6. Verify the Truth Tables and Compare the universal gates before and after minimization.

Truth Table:

Input Output
s s
A B C Y
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0

Result: The Boolean function using universal gates is simplified and verified.

Viva questions:
DLD LAB MANUAL Dept. OF ECE,GIET

Shadan Womens College Of

Engineering &
Technology

1. What are the different methods to obtain minimal expression?

2. What is a Min term and Max term?
3. State the difference between SOP and POS.
4. What is meant by canonical representation?
5. What is K-map? Why is it used?
DLD LAB MANUAL Dept. OF ECE,GIET

EXPERIMENT NO-3

Design And Realize Full Adder Circuit Using Gates. Implement Full Subtractor Using
Full Adder.

Aim: 1.To design and construct full adder circuit and verify the truth table using logic gates.
2. To design and implement full subtractor using full adder.

Apparatus:

S.No. Name of the Type/Range Quantity

Apparatus/Component
1 Digital Trainer Kit with Digital 1
bread board Trainer
Kit
2 Integrated Circuit(s) IC 7408 1
IC 7486 1
IC 7432 1
IC 7404 1
3 Connecting Wires Singl as required
e
stran
d
4 Patch Cords 4mm as required

ADDER:

Theory:

An Adder is a circuit which performs addition of binary numbers. Producing sum and carry. An
half adder is a digital circuit which performs addition of two binary numbers which are one bit
each and produces a sum and a carry (one bit each). A full adder is a digital circuit which
performs addition of three binary numbers (one bit each), to produce a sum and a carry (one bit
each). Full adders are basic block of any adder circuit as they add two numbers along with the
carry from the previous addition.

Block Diagram of Full Adder:

A SUM
B Full Adder
CARRY
C
 DLD LAB MANUAL Dept. OF ECE,GIET

Pin Diagram:

Truth Table:

K Map for SUM: K Map for CARRY:

 DLD LAB MANUAL Dept. OF ECE,GIET

Circuit diagram of full adder using logic gates:

Procedure:
1. Place the IC in the socket of the trainer kit.
2. Make the connections as shown in the circuit diagram.
3. Verify the truth table for full adder circuit using basic gates.

SUBRATCOR:

Theory:
The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor the logic
circuit should have three inputs and two outputs. A full subtractor subtracts two one bit numbers
along with a borrow (from previous stage) to generate a difference and a borrow
 DLD LAB MANUAL Dept. OF ECE,GIET

Block diagram of full subtractor using full adder:

Truth Table:

Circuit diagram of full subtractor using full adder:

 DLD LAB MANUAL Dept. OF ECE,GIET

Procedure:
1. Place the IC in the socket of the trainer kit.
2. Make the connections as shown in the circuit diagram.
3. Verify the truth table for full adder circuit using basic gates.

Result:
The full adder and full subtractor circuits are designed, constructed and verified the truth
table using logic gates.

Viva Questions:
1. What is a half adder?
2. What is a full adder?
3. What are the applications of adders?
4. What is a half subtractor?
5. What is a full subtractor?
6. What are the applications of subtractors?
7. Obtain the minimal expression for above circuits.
8. Realize a full adder using two half adders
9. Realize a full subtractors using two half subtractors
DLD LAB MANUAL Dept. OF ECE,GIET

EXPERIMENT NO- 4

Design A 2-Bit Comparator Using Basic Gates. Realize 4-Bit Comparator Using 2- Bit
Comparator.

Aim: 1.To design a 2-bit comparator using basic gates.

2. To realize 4- bit comparator using 2-bit comparator.

Apparatus:

S.No Name of the Type/Range Quantity

Apparatus/Component
1 Digital Trainer Kit with Digital 1
bread board Trainer
Kit
2 Integrated Circuit(s) IC 7404 1
IC 7408 1
IC 7432 1
IC 7485 1
3 Connecting Wires Single strand as required

4 Patch Cords 4mm as required

Theory:
A magnitude digital comparator is a combinational circuit that compares two digital or binary
numbers in order to find out whether one binary number is equal, less than or greater than the
other binary number. We logically design a circuit for which we will have two inputs one for A
and other for B and have three output terminals, one for A > B condition, one for A = B
condition and one for A < B condition.
2-Bit Magnitude Comparator:
A comparator used to compare two binary numbers each of two bits is called a 2-bit magnitude
comparator. It consists of four inputs and three outputs to generate less than, equal to and
greater than between two binary numbers.

4-Bit Magnitude Comparator:

A comparator used to compare two binary numbers each of four bits is called a 4-bit magnitude
comparator. It consists of eight inputs each for two four-bit numbers and three outputs to
generate less than, equal to, and greater than between two binary numbers.

Block diagram:
 DLD LAB MANUAL Dept. OF ECE,GIET

Circuit diagram of 2 –bit magnitude comparator:

Truth table:
DLD LAB MANUAL Dept. OF ECE,GIET

Pin diagram of 7485:

4 bit comparator using 2-bit comparator:

 DLD LAB MANUAL Dept. OF ECE,GIET

Truth table:

Procedure:
1. Place the IC in the socket of the trainer kit.
2. Make the connections as shown in the circuit diagram.

3. Verify the truth tables for 2-bit comparator circuit using basic gates
and 4-bit comparator.

Result:
2 bit comparator and 4 bit comparator are designed, and the truth table is verified.

Viva Questions:
1. What is a comparator?
2. What are the applications of comparator?
3. Derive the Boolean expressions of one bit comparator and two bit comparators.
4. How do you realize a higher magnitude comparator using lower bit comparator?
5. Design a 2 bit comparator using a single Logic gates?
6. Design an 8 bit comparator using a two numbers of IC 7485?
DLD LAB MANUAL Dept. OF ECE,GIET

EXPERIMENT NO-5

Realize 2:1 Mux Using the given gates and Design 8:1 Using 2:1 Mux

Aim: 1.To design 2:1 MUX using the given gates.

2. To design 8:1 MUX using 2:1 MUX.

Apparatus:

S.No Name of the Type/Range Quantity

Apparatus/Component
1 Digital Trainer Kit with Digital 1
bread board Trainer
Kit
2 Integrated Circuit(s) IC 7404 1
IC 7408 1
IC 7432 1
IC 74LS157 1
3 Connecting Wires Single strand as required
4 Patch Cords 4mm as required

Theory:
The multiplexer or MUX is a digital switch, also called as data selector. It is a Combinational
Logic Circuit with more than one input line, one output line and more than one select line. It
accepts the binary information from several input lines or sources and depending on the set of
select lines, a particular input line is routed onto a single output line.
2X1 MUX:
A 2-to-1 multiplexer consists of two inputs D0 and D1, one select input S and one output Y.
Depending on the select signal, the output is connected to either of the inputs. Since there are
two input signals, only two ways are possible to connect the inputs to the outputs, so one select is
needed to do these operations. If the select line is low, then the output will be switched to D0
input, whereas if select line is high, then the output will be switched to D1 input.
DLD LAB MANUAL Dept. OF ECE,GIET

Shadan Womens College Of

Engineering &
Technology

8X1 MUX:
The general multiplexer circuit has 2n input signals, n control/select signals and 1 output signal.
8 X 1 Multiplexer has 8 input signals and one output signal, three data control or select lines.
These data control lines are nothing but 3-bit binary code on the data control signal inputs which
will allow the data on the corresponding data input to pass through to the data output

Block diagram:

Circuit diagram of 2X1 MUX:

DLD LAB MANUAL Dept. OF ECE,GIET

Truth Table of 2X1 MUX:

Input Output
s s
S D0 D1 Y

0 0 X 0

0 1 X 1

1 X 0 0

1 X 1 1

Pin diagram:
DLD LAB MANUAL Dept. OF ECE,GIET

Block diagram of 8X1 MUX using 2X1 MUX:

Circuit diagram of 8X1 MUX:

DLD LAB MANUAL Dept. OF ECE,GIET

Truth Table:

Procedure:
1. Connect the circuit as shown in the figure.
2. Apply E=0 to enable the circuit.
3. Apply A=0, B=0, C=0 to select the input ‘I0’ at the output for both ‘0’ and ‘1’.
4. Repeat step for various values of A, B, C to select different inputs (I1 – I7) at output.
5. Draw and verify the truth table.

Result:
1. 2X1 Mux is designed and truth table is verified.
2. 8X1 Mux is designed using 2X1 Mux and the truth table is verified.

Viva Questions:
1. What is a multiplexer?
2. What is a de-multiplexer?
3. What are the applications of multiplexer and de-multiplexer?
4. Derive the Boolean expression for multiplexer and de-multiplexer.
5. How do you realize a given function using multiplexer?
6. What is the difference between multiplexer & demultiplexer?
DLD LAB MANUAL Dept. OF ECE,GIET

EXPERIMENT NO-6

Implement The Given Boolean Function Using The Given Mux.

Aim: To implement full adder using 4X1 MUX.

Apparatus:

S.No Name of the Type/Range Quantity

Apparatus/Component
1 Digital Trainer Kit with bread board Digital 1
Trainer
Kit
2 Integrated Circuit(s) IC 74153 1

3 Connecting Wires Single strand as required

4 Patch Cords 4mm as required

Theory:
Multiplexers are very useful components in digital systems. They transfer a large number of
information units over a smaller number of channels, (usually one channel) under the control of
selection signals. Multiplexer means many to one. A multiplexer is a circuit with many inputs
but only one output. By using control signals (select lines) we can select any input to the output.
Multiplexer is also called as data selector because the output bit depends on the input data bit
that is selected. The general multiplexer circuit has 2n input signals, n control/select signals and
1 output signal.

Pin diagram:
 DLD LAB MANUAL Dept. OF ECE,GIET

Circuit diagram of full adder using 4X1 MUX:

Truth table:

Procedure:
1. Place the IC in the socket of the trainer kit.
2. Make the connections as shown in the circuit diagram.
3. Verify the truth table for full adder circuit using basic gates.

Result: Full adder is designed using 4X1 MUX and truth table is verified.
DLD LAB MANUAL Dept. OF ECE,GIET

Viva Questions:
1. What is a multiplexer?
2. What is a de-multiplexer?
3. What are the applications of multiplexer and de-multiplexer?
4. Derive the Boolean expression for multiplexer and de-multiplexer.
5. How do you realize a given function using multiplexer?
6. What is the difference between multiplexer & demultiplexer?
7. In 2n to 1 multiplexer how many selection lines are there?
8. How to get higher order multiplexers?
9. Implement an 8:1 mux using 4:1 mux?
 DLD LAB MANUAL Dept. OF ECE,GIET

EXPERIMENT NO-7

Realize A 2x4 Decoder Using Logic Gates And Implement 3x8 Decoder Using 2x4 Decoder.

Aim: 1. To design 2X4 decoder using logic gates.

2. To design 3X8 decoder using 2X4 decoder.

Apparatus:

S.No Name of the Type/Range Quantity

Apparatus/Component
1 Digital Trainer Kit with bread board Digital 1
Trainer
Kit
2 Integrated Circuit(s) IC 7404 1
IC 7408 1
IC 74139 1
3 Connecting Wires Single strand as required
4 Patch Cords 4mm as required

Theory:
Decoder is a combinational circuit that has 'n' input lines and maximum of 2 n output lines. One
of these outputs will be active High based on the combination of inputs present, when the
decoder is enabled. That means decoder detects a particular code.
2:4 Decoder:
The 2-to-4 line binary decoder depicted above consists of an array of four AND gates. The 2
binary inputs labelled A and B are decoded into one of 4 outputs, hence the description of 2-to-4
binary decoder. Each output represents one of the minterms of the 2 input variables, (each output
= a minterm).
3:8 Decoder:
The 3 to 8 line decoder is also known as binary to octal decoder . In a 3 to 8 line decoder, there
is a total of eight outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and three outputs, i.e., A0, A1,
and A2. This circuit has an enable input 'E'. When enable 'E' is set to 1, one of these four outputs
will be 1. The block diagram and the truth table of the 3 to 8 line encoder are given below.
DLD LAB MANUAL Dept. OF ECE,GIET

Block diagram:

Circuit diagram of 2X4 decoder:

DLD LAB MANUAL Dept. OF ECE,GIET

Truth table of 2X4 decoder:

Pin diagram:
DLD LAB MANUAL Dept. OF ECE,GIET

Circuit diagram of 3X8 decoder using 2X4 decoder:

Truth table:
DLD LAB MANUAL Dept. OF ECE,GIET

Procedure:
1. Place the IC in the socket of the trainer kit.
2. Make the connections as shown in the circuit diagram.
3. Verify the truth table for full adder circuit using basic gates.

Result: 1. 2X4 decoder is designed and truth table is verified.

2. 3X8 decoder is designed using 2X4 decoder and truth table is verified.

Viva Questions:

1. Define decoder?
2. Define encoder?
3. Define binary decoder?
4. Differentiate between decoder and encoder.
5. Applications of decoder.
DLD LAB MANUAL Dept. OF ECE,GIET

EXPERIMENT NO-8

Implement the Given Boolean Function Using Decoders

Aim: To implement Boolean function F= ∑ m (1, 2, 3, 7) using 3:8 decoders.

Apparatus:

S.No Name of the Type/Range Quantity

Apparatus/Component
1 Digital Trainer Kit with bread board Digital 1
Trainer
Kit
2 Integrated Circuit(s) IC 74138 1

3 Connecting Wires Single strand as required

4 Patch Cords 4mm as required

Theory:
Decoder is a combinational circuit that has 'n' input lines and maximum of 2 n output lines. One
of these outputs will be active High based on the combination of inputs present, when the
decoder is enabled. That means decoder detects a particular code.
3:8 Decoder:
The 3 to 8 line decoder is also known as binary to Octal Decoder. In a 3 to 8 line decoder,
there is a total of eight outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and three outputs, i.e., A0,
A1, and A2. This circuit has an enable input 'E'. When enable 'E' is set to 1, one of these four
outputs will be 1. The block diagram and the truth table of the 3 to 8 line encoder are given
below.
Block diagram:
DLD LAB MANUAL Dept. OF ECE,GIET

Pin diagram ( 3 : 8 Decoder ):

Circuit diagram:

Procedure:
1. Place the IC in the socket of the trainer kit.
2. Make the connections as shown in the circuit diagram.
3. Verify the truth table for full adder circuit using basic gates.
DLD LAB MANUAL Dept. OF ECE,GIET

Truth Table:

Input Output
s s
E1’ E2’ E3 A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 F

H X X X X X H H H H H H H H 0
X H X X X X H H H H H H H H 0
X X L X X X H H H H H H H H 0
L L H 0 0 0 L H H H H H H H 0
L L H 0 0 1 H L H H H H H H 1
L L H 0 1 0 H H L H H H H H 1
L L H 0 1 1 H H H L H H H H 1
L L H 1 0 0 H H H H L H H H 0
L L H 1 0 1 H H H H H L H H 0
L L H 1 1 0 H H H H H H L H 0
L L H 1 1 1 H H H H H H H L 1

Result:
The given Boolean function using decoder is implemented and verified with the truth

table. Viva Questions:

1. Define decoder?
2. Define encoder?
3. Define binary decoder?
4. Differentiate between decoder and encoder.
5. Applications of decoder.
DLD LAB MANUAL Dept. OF ECE,GIET

EXPERIMENT NO-9

Convert Demultiplexer to Decoder And Vice Versa

Aim: 1. To convert demultiplexer to decoder

2. To convert decoder to demultiplexer.

Apparatus:

S. Name of the Type/Range Quantity

No. Apparatus/Component
1 Digital Trainer Kit with bread board Digital Trainer 1
Kit
2 Integrated Circuit(s) IC 74138 1
IC 74154 1
3 Connecting Wires Single strand as
require
d
4 Patch Cords 4mm as
required

Theory:

Let us try to understand the Terminology of Multiplexer, Demultiplexer, Encoder and Decoder.

Multiplex -> Many to One

DeMultiplex -> One to
Many

Encode -> Converting a message to

number Decode -> Converting a
number to message.

Demultiplexer - an electronic device that separates a multiplex signal into its component parts. De-
Multiplexer is a combinational circuit that performs the reverse operation of Multiplexer. It has single
input, 'n' selection lines and maximum of 2n outputs. The input will be connected to one of these
outputs based on the values of selection lines.
The demultiplexer takes one single input data line and then switches it to any one of a number of
individual output lines one at a time. The demultiplexer converts a serial data signal at the input to a
DLD LAB MANUAL Dept. OF ECE,GIET

parallel data at its output lines. It consists of 1 input line, 'n' output lines and 'm' select lines. In this, m
select lines are required to produce 2m possible output lines (consider 2m = n).
For example, a 1-to-4 demultiplexer requires 2 (22 = 4) select lines to control the 4 output lines. The
different types of demultiplexers are 1-2 Demux, 1-4 Demux, 1-8 Demux, 1-16 Demux or 1-32
Demux. In demultiplexer, the selection of output line can be controlled through n-selection lines bit
values.

Figure: Truth Table of 1:2 Demultiplexer Figure: Block Diagram of 1:2 Demultiplexer

Figure: Logic Diagram of 1:2 Demultiplexer

Figure: Block Diagram of 1:8 Demultiplexer

DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Truth Table of 1:8 Demultiplexer

Figure: Logic Diagram of 1:8 Demultiplexer

DLD LAB MANUAL Dept. OF ECE,GIET

Figure: 74LS138 3-to-8-line Decoder/Demultiplexer IC (74138 IC) DIP-16 Package.

Features of IC 74138: It is very fast and high-speed IC. It consumes very low power because it
consists of low power Schottky diodes. It has a demultiplexing facility. It has a very short
propagation delay. Appropriate operating Temperature.

IC 74138 Applications: It is a decoder IC, the main application is to decode the digital signal. They
are used in digital memory circuits. They are used in data routing applications. They are used for
demultiplexing of digital signals.

74138 is a demultiplexer or decoder IC. The IC 74LS138 is a 3-to-8-line decoder integrated circuit
from the 74xx family of transistor-transistor-logic-gates. The main function of this IC is to decode
otherwise demultiplex the applications. The setup of this IC is accessible with 3-inputs to 8-output
setup.
DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Function Table of 74138 IC

74LS138 is a 3-line to 8-line decoder / demultiplexer. The 74LS138 can be used as an 8- output
demultiplexer by using one active LOW Enable input as data input & the other Enable inputs as
strobes.

The combinational circuits that convert the binary data into 2N output lines are called Decoders.
Decoder is a combinational circuit that has 'n' input lines and maximum of 2n output lines. One of
these outputs will be active High based on the combination of inputs present, when the decoder is
enabled. That means decoder detects a particular code.

Figure: Block Diagram of N: 2N Decoder

DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Block Diagram of N: 2N Decoder (with enable input)

Figure: Block Diagram of 3x8 Decoder Figure: Truth Table of 3X8 Decoder
DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Logic Diagram of 3x8 Decoder

We take the popular 3 to 8 decoder Integrated Circuit 74138. The Integrated Circuit is of 16 pins.
We have three input pins which are actively in high state and are classified as I2, I1 and I0.
DLD LAB MANUAL Dept. OF ECE,GIET

Shadan Womens College Of

Engineering &
Technology

Figure: Comparison of demultiplexer and decoder

Figure: 74154 is a monolithic 4−line−to−16−line decoder in a 24−Lead DIP type package

DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Function Table of 74154 4−line−to−16−line decoder

DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Block Diagram of 1x16 Demultiplexer

Figure: Logic Diagram of 1x16 Demultiplexe

DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Truth Table of 1x16 Demultiplexer

74HC154 (74154) is a 4-Line to 16-Line Decoder/Demultiplexer IC. The 74154 is a monolithic

4−line−to−16−line decoder in a 24−Lead DIP type package and utilizes TTL circuitry to decode four
binary−coded inputs into one of sixteen mutually exclusive outputs when both the strobe inputs, G1
and G2, are low.

In 1×16 de-multiplexer, there are total of 16 outputs, i.e., Y 0, Y1, …, Y16, 4 selection lines, i.e., S0, S1,
S2, and S3 and single input, i.e., A. On the basis of the combination of inputs which are present at the
selection lines, the input will be connected to one of these outputs.

The select lines of the demultiplexer is treated as input lines of decoder and the single input line of
demultiplexer is considered as an enable input of decoder. If enable is 1, only decoder’s output
corresponding to input bits will be 1, all other outputs will be in 0. Thus acting similar to a
demultiplexer

A 4x16 decoder has 4 inputs and 16 outputs, with the outputs going high for the corresponding 4-bit
input. Normally the IC are made to work multipurpose that is to act as decoder and demultiplexer both.
Normally, decoder is of form n to 2 n line decoder, having n input lines, and 2 n line output, with enable
line. For this decoder to work as demultiplexer, it's enabled pin is used as input and n input lines of

decoder as select lines and 2n output lines.

DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Block Diagram and Truth Table of 4:16 Decoder

DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Logic Diagram of 4:16 Decoder

Procedure:
1. Implement connections (or design as) per the logic or IC pin out diagram.
2. Switch on the power supply
3. Understand output as per truth table only.
4. Observe the output on LEDs
5. Verify the truth table as per digital circuit for given set of input combinations.
DLD LAB MANUAL Dept. OF ECE,GIET

Result: Hence, demultiplexer is converted to decoder and vice versa.

Precautions:
1. All the connections should be correct. Avoid loose contact.
2. Make the connections according to the IC pin diagram. The Vcc and ground should be
applied carefully at the specified pin only.
3. Digital lab kits and ICs should be handled with utmost care.
4. While making connections main voltage should be kept switched off.
5. Never touch live and naked wires
Viva Questions:

1) What is multiplexer, demultiplexer, encoder and decoder?

2) Define the term “enable”. Explain its importance.
3) Write truth-table and logic diagram of multiplexer and demultiplexer.
4) Write truth-table and logic diagram of encoder.
5) Write truth-table and logic diagram of decoder
DLD LAB MANUAL Dept. OF ECE,GIET

EXPERIMENT NO-10

Verification of Truth Tables of Flipflops using different clocks (level triggering, positive and
negative edge triggering) Also Converts the given Flipflop from one type to other.

Aim: To verify truth tables of flip-flops.

Apparatus:

S. Name of the Type/Range Quantity

No. Apparatus/Component
1 Digital Trainer Kit with bread board Digital Trainer 1
Kit
2 Integrated Circuit(s) as required 1

3 Connecting Wires Single strand as

require
d
4 Patch Cords 4mm as
required

Theory:
In electronics, flip-flops and latches are circuits that have two stable states that can store information.
The circuit can be made to change state by signals applied to one or more control inputs and will
output its state (often along with its logical complement too). It is the basic storage element in
sequential logic.
Flip-flops and latches are fundamental building blocks of digital electronics systems used in
computers, communications, and many other types of systems. Flip-flops and latches are used as data
storage elements to store a single bit (binary digit) of data; one of its two states represents a "one" and
the other represents a "zero". Such data storage can be used for storage of state, and such a circuit is
described as sequential logic in electronics.
DLD LAB MANUAL Dept. OF ECE,GIET

SR FLIP FLOP:

The SR flip-flop, also known as a SR Latch, can be considered as one of the most basic sequential logic
circuit possible. This simple flip-flop is basically a one-bit memory bistable device that has two inputs,
one which will “SET” the device (meaning the output = “1”), and is labelled S and one which will
“RESET” the device (meaning the output = “0”), labelled R.
Then the SR description stands for “Set-Reset”. The reset input resets the flip-flop back to its original
state with an output Q that will be either at a logic level “1” or logic “0” depending upon this set/reset
condition.
A basic NAND gate SR flip-flop circuit provides feedback from both of its outputs back to its opposing
inputs and is commonly used in memory circuits to store a single data bit. Then the SR flip-flop
actually has three inputs, Set, Reset and its current output Q relating to it’s current state or history.
The term “Flip-flop” relates to the actual operation of the device, as it can be “flipped” into one logic
Set state or “flopped” back into the opposing logic Reset state.

SEQUENTIAL LOGIC – THE NAND GATE SR FLIP-FLOP

The simplest way to make any basic single bit set-reset SR flip-flop is to connect together a pair of
cross- coupled 2-input NAND gates as shown, to form a Set-Reset Bistable also known as an active
LOW SR NAND Gate Latch, so that there is feedback from each output to one of the other NAND
gate inputs. This device consists of two inputs, one called the Set, S and the other called the Reset, R
with two corresponding outputs Q and its inverse or complement Q (not-Q) as shown below.

Figure: Symbol and circuit diagram of SR flip-flop.

DLD LAB MANUAL Dept. OF ECE,GIET

THE SET STATE

Consider the circuit shown above. If the input R is at logic level “0” (R = 0) and input S is at logic level
“1” (S = 1), the NAND gate Y has at least one of its inputs at logic “0” therefore, its output Q must be
at
a logic level “1” (NAND Gate principles). Output Q is also fed back to input “A” and so both inputs
to NAND gate X are at logic level “1”, and therefore its output Q must be at logic level “0”.
Again NAND gate principals. If the reset input R changes state, and goes HIGH to logic “1” with S
remaining HIGH also at logic level “1”, NAND gate Y inputs are now R = “1” and B = “0”. Since one
of its inputs is still at logic level “0” the output at Q still remains HIGH at logic level “1” and there is
no change of state. Therefore, the flip-flop circuit is said to be “Latched” or “Set” with Q = “1” and Q
= “0”.

RESET STATE
In this second stable state, Q is at logic level “0”, (not Q = “0”) its inverse output at Q is at logic level
“1”, (Q = “1”), and is given by R = “1” and S = “0”.
As gate X has one of its inputs at logic “0” its output Q must equal logic level “1” (again NAND gate
principles). Output Q is fed back to input “B”, so both inputs to NAND gate Y are at logic “1”,
therefore, Q = “0”. If the set input, S now changes state to logic “1” with input R remaining at logic
“1”, output Q still remains LOW at logic level “0” and there is no change of state. Therefore, the flip-
flop circuits “Reset” state has also been latched and we can define this “set/reset” action in the
following truth table.

POSITIVE NAND GATE SR FLIP-FLOP

Figure: NAND gate-based circuit diagram and truth table of SR flip-flop.
DLD LAB MANUAL Dept. OF ECE,GIET

QUAD SR BISTABLE LATCH 74LS279

Figure: Internal architecture or pin diagram of IC 74LS279 (NAND gate based circuit diagram of
SR flip-
flop.)
 DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Truth table of SR flip-flop

JK FLIP FLOP:

Unlike the JK Flip-flop, the basic S-R NAND flip-flop circuit has many advantages and uses in
sequential logic circuits but it suffers from two basic switching problems.
• 1. the Set = 0 and Reset = 0 condition (S = R = 0) must always be avoided
• 2. if Set or Reset change state while the enable (EN) input is high the correct latching action may not occur
Then to overcome these two fundamental design problems with the SR flip-flop design, the JK flip
Flop was developed.
This simple JK flip Flop is the most widely used of all the flip-flop designs and is considered to be a
universal flip-flop circuit. The two inputs labelled “J” and “K” are not shortened abbreviated letters of
other words, such as “S” for Set and “R” for Reset, but are themselves autonomous letters chosen by its
inventor Jack Kilby to distinguish the flip-flop design from other types.
The sequential operation of the JK flip flop is exactly the same as for the previous SR flip-flop with the
same “Set” and “Reset” inputs. The difference this time is that the “JK flip flop” has no invalid or
forbidden input states of the SR Latch even when S and R are both at logic “1”.
The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry that
prevents the illegal or invalid output condition that can occur when both inputs S and R are equal to
logic level “1”. Due to this additional clocked input, a JK flip-flop has four possible input
combinations, “logic 1”, “logic 0”, “no change” and “toggle”. The symbol for a JK flip flop is similar
to that of an SR Bistable Latch as seen in the previous tutorial except for the addition of a clock input.
DLD LAB MANUAL Dept. OF ECE,GIET

THE BASIC JK FLIP-FLOP

Both the S and the R inputs of the previous SR bistable have now been replaced by two inputs called the
J and K inputs, respectively after its inventor Jack Kilby. Then this equates to: J = S and K = R.

Figure: Logic Symbol and Circuit diagram of JK flip-flop.

DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Truth table of JK flip-flop.

DLD LAB MANUAL Dept. OF ECE,GIET

Figure: ICs for JK flip-flopFigure: Internal architecture or pin diagram of IC 7476

Figure: Truth table of JK flip-flop

DLD LAB MANUAL Dept. OF ECE,GIET

D FLIP FLOP:

The D-type Flip-flop overcomes one of the main disadvantages of the basic SR NAND Gate
Bistable circuit in that the indeterminate input condition of SET = “0” and RESET = “0” is forbidden.
But in order to prevent this from happening an inverter can be connected between the “SET” and the
“RESET” inputs to produce another type of flip flop circuit known as a Data Latch, Delay flip flop, D-
type Bistable, D-type Flip Flop or just simply a D Flip Flop as it is more generally called.
The D Flip Flop is by far the most important of all the clocked flip-flops. By adding an inverter (NOT
gate) between the Set and Reset inputs, the S and R inputs become complements of each other ensuring
that the two inputs S and R are never equal (0 or 1) to each other at the same time allowing us to
control the toggle action of the flip-flop using one single D (Data) input.

Then this Data input, labelled “D” and is used in place of the “Set” signal, and the inverter is used to
generate the complementary “Reset” input thereby making a level-sensitive D-type flip-flop from a
level- sensitive SR-latch as now S = D and R = not D as shown.
DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Logic Symbol and Circuit diagram of D flip-flop.

D-TYPE FLIP-FLOP CIRCUIT

One single input is called the “DATA” input. If this data input is held HIGH the flip flop would be
“SET” and when it is LOW the flip flop would change and become “RESET”.
To avoid this an additional input called the “CLOCK” or “ENABLE” input is used. The effect is that D
input condition is only copied to the output Q when the clock input is active. This then forms the basis
of another sequential device called a D Flip Flop.
The “D flip flop” will store and output whatever logic level is applied to its data terminal so long as the
clock input is HIGH. Once the clock input goes LOW the “set” and “reset” inputs of the flip-flop are
both held at logic level “1” so it will not change state.

Figure: Truth table of D flip-flop

DLD LAB MANUAL Dept. OF ECE,GIET

Figure: ICs for JK flip-flop.

Figure: Internal architecture or pin diagram of IC 7474

T-TYPE FLIP-FLOP CIRCUIT

A T Flip-Flop (also known as a toggle or TFF) is a basic circuit that changes polarity (from on to off
or off to on) its input signal changes from off to on. This is very useful for many reasons, such as
halving the speed of a clock, or changing a 2-state system to a 4-state one, etc. A T Flip-Flop has a
single input T and one output Q. There is also an optional output Q̅ (“Q bar” or “Not Q”) which is
always the opposite of Q.
DLD LAB MANUAL Dept. OF ECE,GIET

A T flip-flop is a device which swaps or "toggles" state every time it is triggered if the T input
is asserted, otherwise it holds the current output. This behavior is described by the
characteristic equation:

Figure: Symbol of T flip-flop

and can be described either of the following tables:

Figure: Truth table and excitation of T flip-flop

Figure: Logic diagram of NAND gate-based T flip-flop.

DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Internal architecture or pin diagram of IC 7410 Figure: Pin diagram of IC 7410

Figure: Internal architecture or pin diagram of IC 7400 Figure: Pin diagram of IC 7400

Procedure:
1. Implement connections (or design as) per the logic or IC pin out diagram.
2. Switch on the power supply
3. Understand output as per truth table only.
4. Observe the output on LEDs.
5. Verify the truth table as per digital circuit for given set of input combinations.

Result: All types of flip-flops are studied and their truth tables are verified.
DLD LAB MANUAL Dept. OF ECE,GIET

Precautions:
1. All the connections should be correct. Avoid loose contact.
2. Make the connections according to the IC pin diagram. The Vcc and ground should be
applied carefully at the specified pin only.
3. Digital lab kits and ICs should be handled with utmost care.
4. While making connections main voltage should be kept switched off.

Viva Questions:

1. What is flip-flop?
2. Define the term “negative-edge triggered and positive-edge triggered clock”.
Explain its importance.
3. Write truth-table and logic diagram of SR and JK Flip-Flop.
4. Write truth-table and logic diagram of D Flip-Flop.
5. Write truth-table and logic diagram of T Flip-Flop.
DLD LAB MANUAL Dept. OF ECE,GIET

EXPERIMENT NO-11

Designing Of Universal N-Bit Shift Register Using Flipflops And Multiplexers. Draw The
Timing Diagram Of The Shift Register.

Aim: To design and realize universal n-bit (4-bit parallel load serial out shift register
right and left) shift register using flipflops and multiplexer.

Apparatus:

S. Name of the Apparatus/Component Type/Range Quantity

No.
1 Digital Trainer Kit with bread board Digital Trainer 1
Kit
2 Integrated Circuit(s) as required as
required
3 Connecting Wires Single strand as
require
d
4 Patch Cords 4mm as
required

Theory:
A shift registers are the sequential logic circuits. These are capable of transferring/shifting the data
either towards the right or left in serial and parallel modes. Based on the mode of input/output
operations, shift registers can be used as a serial-in-parallel-out shift register, serial-in-serial-out shift
register, parallel-in- parallel-out shift register, parallel-in-parallel-out shift register. A register that
can store the data and /shifts the data towards the right and left along with the parallel load capability
is known as a universal shift register. It can be used to perform input/output operations in both serial
and parallel modes. It is also known as a parallel-in-parallel-out shift register or shift register with
the parallel load. It can perform 3 operations as listed below. Parallel load operation – stores the
data in parallel as well as the data in parallel. Shift left operation – stores the data and transfers the
data shifting towards left in the serial path. Shift right operation
– stores the data and transfers the data by shifting towards right in the serial path.Hence, Universal
shift registers can perform input/output operations with both serial and parallel loads. The design of
a 4-bit universal shift register using multiplexers and flip-flops is shown below.
 DLD LAB MANUAL Dept. OF ECE,GIET

Parallel Inputs

Figure: Shift Register Using Multiplexer and Flip-Flops.

 Serial input for shift-right control enables the data transfer towards the right and all the serial input and
output lines are connected to the shift-right mode.
 Serial input for shift-left enables the data transfer towards the left and all the serial input and output
lines are connected to shift-left mode.
 In parallel data transfer, all the parallel inputs and outputs lines are associated with the parallel load.
Clear pin clears the register and set to 0. CLK pin provides clock pulses to synchronize all the
operations. If the register operates with a parallel load and shifts the data towards the right and left, then
it acts as a universal shift register.
 If the selected pins S0= 0 and S1 = 0, then this register doesn’t operate in any mode. That means it will be
in a Locked state or no change state even though the clock pulses are applied.
 If the selected pins S0 = 0 and S1 = 1, then this register transfers or shifts the data to left and stores the data.
 If the selected pins S0 = 1 and S1 = 0, then this register shifts the data to right and hence performs the
shift-right operation.
 If the selected pins S0 = 1 and S1 = 1, then this register loads the data in parallel. Hence it performs the
parallel loading operation and stores the data.
 From the above table, we can observe that this register operates in all modes with serial/parallel inputs
using 4×1 multiplexers and flip-flops.
DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Internal architecture or pin diagram of IC 7474

Figure: Pin diagram of IC 7474

DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Function Table of IC 7474

DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Logic Diagram of 4x1 multiplexer

Figure: Symbol of 4x1 multiplexer

Figure: Truth table of 4 by 1 multiplexer

DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Pin description of IC 74153

Figure: Function table of IC 74153

DLD LAB MANUAL Dept. OF ECE,GIET

There are different kinds of 4-bit registers are available in the form of IC 74291, IC 74395.

Procedure:
1. Implement connections (or design as) per the logic or IC pin out diagram.
2. Switch on the power supply
3. Understand output as per truth table only.
4. Observe the output on LEDs.
5. Verify the truth table as per digital circuit for given set of input combinations.

Result: All types flip-flop are studied and their truth tables are verified.

Precautions:
1. All the connections should be correct. Avoid loose contact.
2. Make the connections according to the IC pin diagram. The Vcc and ground should be
applied carefully at the specified pin only.
3. Digital lab kits and ICs should be handled with utmost care.
4. While making connections main voltage should be kept switched off.
5. Never touch live and naked wires

Viva Questions:
1. What is flip-flop?
2. Define the term “negative-edge triggered and positive-edge triggered clock”.
Explain its importance.
3. Write truth-table and logic diagram of all Flip-Flops.
4. Write truth-table and logic diagram of multiplexer.
5. Write truth-table and logic diagram of shift-register.
 DLD LAB MANUAL Dept. OF ECE,GIET

EXPERIMENT NO-12

DESIGN A SYNCHRONOUS BINARY COUNTER USING D-FLIPFLOP/GIVEN

FLIPFLOP.

Aim: To design and realize a synchronous binary counter using d-flipflop/given flipflop.

Apparatus:

S. Name of the Apparatus/Component Type/Range Quantity

No.
1 Digital Trainer Kit with bread board Digital Trainer 1
Kit
2 Integrated Circuit(s) as required as
required
3 Connecting Wires Single strand as
require
d
4 Patch Cords 4mm as
required

Theory:
In digital logic and computing, a counter is a device which stores (and sometimes displays) the number
of times a particular event or process has occurred, often in relationship to a clock.
The most common type is a sequential digital logic circuit with an input line called the clock and
multiple output lines. The values on the output lines represent a number in the binary or BCD number
system. Each pulse applied to the clock input increments or decrements the number in the counter.
A counter circuit is usually constructed of several flip-flops connected in a cascade. Counters are a
very widely used component in digital circuits, and are manufactured as separate integrated circuits
and also incorporated as parts of larger integrated circuits.
Counters are generally classified as either synchronous or asynchronous.
In synchronous counters, all flip-flops share a common clock and change state at the same time.
In asynchronous counters, each flip-flop has a unique clock, and the flip-flop states change at different
times.
Synchronous counters are categorized in various ways.
For example:

 Modulus counter–counts through a particular number of states.

 Decade counter – modulus ten counter (counts through ten states).
 Up/down counter – counts up and down, as directed by a control input.
 Ring counter – formed by a "circular" shift register.
 Johnson counter – a twisted ring counter.
 Gray-code counter – outputs a sequence of Gray codes.
DLD LAB MANUAL Dept. OF ECE,GIET

Up counter: This type of counter counts from zero to the maximum number of
counts. Down counter: This type of counter counts from the maximum value to zero
value.

Figure: Comparison of an asynchronous and a synchronous counter

DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Internal architecture or pin diagram of IC 7474

Figure: Pin diagram of IC 7474

 DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Function table of IC 7474

Figure: (2-bit) binary (up) counter using D-flip flop Figure: (2-bit) binary (up) counter using D-flip flop
(with reset input)
DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Truth table of (2-bit) binary (up) counter

Figure: Truth table of (2-bit) binary (down) counter

Procedure:
1. Implement connections (or design as) per the logic or IC pin out diagram.
2. Switch on the power supply
3. Understand output as per truth table only.
4. Observe the output on LEDs.
5. Verify the truth table as per digital circuit for given set of input combinations.
DLD LAB MANUAL Dept. OF ECE,GIET

TIMING DIAGRAM:

Figure: Timing diagram of (2-bit) binary (up) counter

Figure: State diagram of (2-bit) binary (up) counter

DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Timing diagram of (2-bit) binary (down) counter

Result: Synchronous (up and down) counter are designed and realized. Their
timing diagrams are studied. Their truth tables are verified.

Precautions:
1. All the connections should be correct. Avoid loose contact.
2. Make the connections according to the IC pin diagram. The Vcc and ground should be
applied carefully at the specified pin only.
3. Digital lab kits and ICs should be handled with utmost care.
4. While making connections main voltage should be kept switched off.
5. Never touch live and naked wires

Viva Questions:
1. What is flip-flop?
2. Compare “synchronous counter and asynchronous counter”.
3. Write truth-table and logic diagram of synchronous counter.
4. Write truth-table and logic diagram of asynchronous counter.
5. Write truth-table and logic diagram of all flip-flops.
 DLD LAB MANUAL Dept. OF ECE,GIET

EXPERIMENT NO - 13

Design An Asynchronous Counter For The Given Sequence Using Given Flip-Flops.

Aim: To design and realize an asynchronous counter using flipflop.

Apparatus:

S. Name of the Apparatus/Component Type/Range Quantity

No.
1 Digital Trainer Kit with bread board Digital Trainer 1
Kit
2 Integrated Circuit(s) as required as
required
3 Connecting Wires Single strand as
require
d
4 Patch Cords 4mm as
required

Theory:
In digital logic and computing, a counter is a device which stores (and sometimes displays) the number
of times a particular event or process has occurred, often in relationship to a clock.
The most common type is a sequential digital logic circuit with an input line called the clock and multiple
output lines. The values on the output lines represent a number in the binary or BCD number system.
Each pulse applied to the clock input increments or decrements the number in the counter.
A counter circuit is usually constructed of several flip-flops connected in a cascade. Counters are a very
widely used component in digital circuits, and are manufactured as separate integrated circuits and also
incorporated as parts of larger integrated circuits.
Counters are generally classified as either synchronous or asynchronous.
In synchronous counters, all flip-flops share a common clock and change state at the same time.
In asynchronous counters, each flip-flop has a unique clock, and the flip-flop states change at different
times.
Synchronous counters are categorized in various ways.
For example:

 Modulus counter–counts through a particular number of states.

 Decade counter – modulus ten counter (counts through ten states).
 Up/down counter – counts up and down, as directed by a control input.
 Ring counter – formed by a "circular" shift register.
 Johnson counter – a twisted ring counter.
 Gray-code counter – outputs a sequence of Gray codes.

Up counter: This type of counter counts from zero to the maximum number of counts.
DLD LAB MANUAL Dept. OF ECE,GIET

Down counter: This type of counter counts from the maximum value to zero value.

Figure: Comparison of an asynchronous and a synchronous counter

DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Internal architecture or pin diagram of IC 7476

Figure: Function Table of IC 7476

 DLD LAB MANUAL Dept. OF ECE,GIET

87

Figure: Logic Diagram of (2-bit) binary (up) counter Figure: Logic Diagram of (2-bit) binary (up) counter
with reset

Figure: Truth table of (2-bit) binary (up) counter

DLD LAB MANUAL Dept. OF ECE,GIET

Shadan Womens College Of

Engineering &
Technology

Figure: Truth table of (2-bit) binary (down) counter

TIMING DIAGRAM:

Figure: Timing diagram of (2-bit) binary (up) counter

DLD LAB MANUAL Dept. OF ECE,GIET

Figure: State diagram of (2-bit) binary (up) counter

Figure: Timing diagram of (2-bit) binary (up) counter

Procedure:

1. Implement connections (or design as) per the logic or IC pin out diagram.
2. Switch on the power supply.
3. Understand output as per truth table only.
4. Observe the output on LEDs.
5. Verify the truth table as per digital circuit for given set of input combinations.

Result: Synchronous (up and down) counter are designed and realized. Their
timing diagrams are studied. Their truth tables are verified.

Precautions:
1. All the connections should be correct. Avoid loose contact.
2. Make the connections according to the IC pin diagram. The Vcc and ground should be
applied carefully at the specified pin only.
3. Digital lab kits and ICs should be handled with utmost care.
DLD LAB MANUAL Dept. OF ECE,GIET

4. While making connections main voltage should be kept switched off.

5. Never touch live and naked wires

Viva Questions:
1) What is flip-flop?
2) Compare “synchronous counter and asynchronous counter”.
3) Write truth-table and logic diagram of synchronous counter.
4) Write truth-table and logic diagram of asynchronous counter.
5) Write truth-table and logic diagram of all flip-flops.
DLD LAB MANUAL Dept. OF ECE,GIET

EXPERIMENT NO - 14

Designing Of Mod 8 Counter Using Jk Flipflops.

Aim: To design and realize a mod-8 counter using flipflop.

Apparatus:

S. Name of the Apparatus/Component Type/Range Quantity

No.
1 Digital Trainer Kit with bread board Digital Trainer 1
Kit
2 Integrated Circuit(s) as required as
required
3 Connecting Wires Single strand as
require
d
4 Patch Cords 4mm as
required

Theory:

JK FLIP FLOP:

The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry that
prevents the illegal or invalid output condition that can occur when both inputs S and R are equal to
logic level “1”. Due to this additional clocked input, a JK flip-flop has four possible input combinations,
“logic 1”, “logic 0”, “no change” and “toggle”.

THE BASIC JK FLIP-FLOP

Both the S and the R inputs of the previous SR bistable have now been replaced by two inputs called the
J and K inputs, respectively after its inventor Jack Kilby. Then this equates to: J = S and K = R.
DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Logic symbol and logic diagram of JK flip flop

Counters whose values “wrap around” back to zero when they reach the value n are called modulo-n
counters.
DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Internal architecture or pin diagram of IC 7476

Figure: Logic circuit and timing diagram of (3-bit) binary Mod-8 counter

Figure: State Transition diagram of M0d-8 Counter

DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Truth table of mod-8 binary counter

Procedure:

1. Implement connections (or design as) per the logic or IC pin out diagram.
2. Switch on the power supply.
3. Understand output as per truth table only.
4. Observe the output on LEDs.
5. Verify the truth table as per digital circuit for given set of input combinations.

Result: Mod-8 counter are designed and realized. Their timing diagrams are studied.
Their truth tables are verified.

Precautions:
1. All the connections should be correct. Avoid loose contact.
2. Make the connections according to the IC pin diagram. The Vcc and ground should be
applied carefully at the specified pin only.
3. Digital lab kits and ICs should be handled with utmost care.
4. While making connections main voltage should be kept switched off.
5. Never touch live and naked wires

Viva Questions:

1) What is flip-flop?
2) Compare “synchronous counter and asynchronous counter”.
3) Write truth-table and logic diagram of mod-8 counter.
4) Define “Modulus Counter”.
5) Write truth-table and logic diagram of all flip-flops.
DLD LAB MANUAL Dept. OF ECE,GIET

EXPERIMENT NO - 15

Designing Of Sequence Detecting State Machine With Minimal States Using The Given Flipflops.

Aim: To design and realize sequence detecting state machine using flipflop.

Apparatus:

S. Name of the Apparatus/Component Type/Range Quantity

No.
1 Digital Trainer Kit with bread board Digital Trainer 1
Kit
2 Integrated Circuit(s) as required as
required
3 Connecting Wires Single strand as
require
d
4 Patch Cords 4mm as
required

Theory:

A Moore Machine is a Finite State Machine (FSM) whose output depends only on the present state.
The block diagram of a Moore FSM is shown in the figure below:

Figure: Block Diagram of FSM

DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Internal architecture or pin diagram of IC 7408

Figure: Internal architecture or pin diagram of IC 7432

DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Internal architecture or pin diagram of IC 7474

Figure: Internal architecture or pin diagram of IC 7400

DLD LAB MANUAL Dept. OF ECE,GIET

Figure: State transition diagram of FSM

Figure: Truth table of FSM

DLD LAB MANUAL Dept. OF ECE,GIET

Figure: K-map of FSM

Figure: Logic Diagram of FSM

Procedure:
1. Implement connections (or design as) per the logic or IC pin out diagram.
2. Switch on the power supply.
3. Understand output as per truth table only.
4. Observe the output on LEDs.
5. Verify the truth table as per digital circuit for given set of input combinations.
DLD LAB MANUAL Dept. OF ECE,GIET

Result: Mod-8 counter are designed and realized. Their timing diagrams are studied.
Their truth tables are verified.

Precautions:
1. All the connections should be correct. Avoid loose contact.
2. Make the connections according to the IC pin diagram. The Vcc and ground should be
applied carefully at the specified pin only.
3. Digital lab kits and ICs should be handled with utmost care.
4. While making connections main voltage should be kept switched off.
5. Never touch live and naked wires

Viva Questions:
1. What is Finite State Machine?
2. Compare all flip-flops.
3. Write truth-table and logic diagram of all flip-flops.
4. Define the term “Sequence Detector”.
5. Distinguish “Mealy” and “Moore” machines.
DLD LAB MANUAL Dept. OF ECE,GIET

EXPERIMENT NO - 16

Designing Of Parity Bit (Even/Odd) Generator Using The Given Flipflops.

Aim: To design and realize parity bit (even/odd) generator using the given flipflops.

Apparatus:

S. Name of the Apparatus/Component Type/Range Quantity

No.
1 Digital Trainer Kit with bread board Digital Trainer 1
Kit
2 Integrated Circuit(s) as required as
required
3 Connecting Wires Single strand as
require
d
4 Patch Cords 4mm as
required

Theory:

A Parity Generator is a combinational logic circuit that generates the parity bit in the transmitter. On the
other hand, a circuit that checks the parity in the receiver is called Parity Checker. A combined circuit or
device of parity generators and parity checkers are commonly used in digital systems to detect the single
bit errors in the transmitted data. EVEN PARITY AND ODD PARITY The sum of the data bits and
parity bits can be even or odd. In even parity, the added parity bit will make the total number of 1s an
even number, whereas in odd parity, the added parity bit will make the total number of 1s an odd
number. The basic principle involved in the implementation of parity circuits is that sum of odd number
of 1s is always 1 and sum of even number of 1s is always 0. Such error detecting and correction can be
implemented by using Ex-OR gates (since Ex-OR gate produce zero output when there are even number
of inputs).

PARITY GENERATOR It is combinational circuit that accepts an n-1 bit data and generates the
additional bit that is to be transmitted with the bit stream. This additional or extra bit is called as a Parity
Bit. In even parity bit scheme, the parity bit is ‘0’ if there are even number of 1s in the data stream and
the parity bit is ‘1’ if there are odd number of 1s in the data stream. In odd parity bit scheme, the parity
bit is ‘1’ if there are even number of 1s in the data stream and the parity bit is ‘0’ if there are odd
number of 1s in the data stream. Let us discuss both even and odd parity generators.

EVEN PARITY GENERATOR Let us assume that a 3-bit message is to be transmitted with an even
parity bit. Let the three inputs A, B and C are applied to the circuit and output bit is the parity bit P. The
DLD LAB MANUAL Dept. OF ECE,GIET

total number of 1s must be even, to generate the even parity bit P. The figure below shows the truth
table of even parity generator in which 1 is placed as parity bit in order to make all 1s as even when the
number of 1s in the truth table is odd.

Figure: Logic Diagram of even parity generator

Figure: Truth Table of Even Parity:

 DLD LAB MANUAL Dept. OF ECE,GIET

3- bit Odd Parity Generator:

Suppose at the transmitting end now we have a 3-bit message signal, and we wish to transmit it using odd parity.
Then, the parity bit generated, P, would be as a result of odd parity generation. The total number of 1s in the
input bits must be odd for the odd parity bit. If the total number of 1s in input bits is odd, then P gets the value 0,
and if it is even then, P is assigned the value 1.

Figure: Logic Diagram of odd parity generator

Figure: Truth Table of odd parity generator

DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Pin diagram of IC 74180

Figure: Logic Diagram of even parity generator using D flip-flop

DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Internal architecture or Pin Diagram of IC 7474 (D flip-flop)

Figure: Internal architecture or Pin Diagram of IC 7486. Function Table of IC 7486

Procedure:

1. Implement connections (or design as) per the logic or IC pin out diagram.
2. Switch on the power supply.
3. Understand output as per truth table only.
4. Observe the output on LEDs.
5. Verify the truth table as per digital circuit for given set of input combinations.
DLD LAB MANUAL Dept. OF ECE,GIET

Result: Even parity generator using D-flip flop is designed and realized. Its truth
tables are verified.

Precautions:
1. All the connections should be correct. Avoid loose contact.
2. Make the connections according to the IC pin diagram. The Vcc and ground should be
applied carefully at the specified pin only.
3. Digital lab kits and ICs should be handled with utmost care.
4. While making connections main voltage should be kept switched off.
5. Never touch live and naked wires

Viva Questions:
1. What is parity generator?
2. Compare parity generator and parity checker.
3. Write truth-table of even and odd parity generator.
4. Explain the importance of D-Flip Flop.
5. Distinguish all Flip-Flop.
DLD LAB MANUAL Dept. OF ECE,GIET

EXPERIMENT NO-17

Realize All Logic Gates Using Ttl Logic Aim:

To realize all logic gates using Transistor-Transistor Logic (TTL) logic.

Apparatus:

S. Name of the Apparatus/Component Type/Range Quantity

No.
1 Digital Trainer Kit with bread board Digital Trainer 1
Kit
2 PN junction diode (1N4001) as required as
required
3 Transistor (BJT BC107) as required as
required
4 Connecting Wires Single strand as
require
d
5 Patch Cords 4mm as
required

Theory:
Figure: Logic Gates - Types
DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Types of Logic Gates – their symbols, description, and Boolean expression

Figure: Types of Logic Gates – their symbols, Boolean Expressions and Truth Table
DLD LAB MANUAL Dept. OF ECE,GIET
DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Two input inverter circuit using Transistor-Transistor Logic (TTL)

Figure: Two input NOR gate circuit using Transistor-Transistor Logic (TTL)
DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Two input OR gate using Transistor-Transistor Logic (TTL)

DLD LAB MANUAL Dept. OF ECE,GIET

Figure: TTL input and output voltage levels

Figure: Two input NAND and AND gate circuit using Transistor-Transistor Logic (TTL)
DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Two input NOR and OR ate circuit using Transistor-Transistor Logic (TTL)

Procedure:

1. Implement connections (or design as) per the logic or IC pin out diagram.
2. Switch on the power supply.
3. Understand output as per truth table only.
4. Observe the output on LEDs.
5. Verify the truth table as per digital circuit for given set of input combinations.

Result: All basic logic gates are realized. Its truth tables are verified.

Precautions:
1. All the connections should be correct. Avoid loose contact.
2. Make the connections according to the IC pin diagram. The Vcc and ground should be
applied carefully at the specified pin only.
3. Digital lab kits and ICs should be handled with utmost care.
4. While making connections main voltage should be kept switched off.
5. Never touch live and naked wires

Viva Questions:
1. Discuss input and output voltage levels in TTL logic.
2. Compare all logic gates.
3. Write truth-table of all logic gates.
4. Explain the importance of EX-OR AND EX-NOR gates..
5. Compare TTL and DTL logic.
DLD LAB MANUAL Dept. OF ECE,GIET

EXPERIMENT NO-18

REALIZE ALL LOGIC GATES USING DTL LOGIC

Aim: To realize all logic gates using Diode-Transistor Logic (DTL).

Apparatus:

S. Name of the Apparatus/Component Type/Range Quantity

No.
1 Digital Trainer Kit with bread board Digital Trainer 1
Kit
2 PN junction diode (1N4001) as required as
required
3 Transistor (BJT BC107) as required as
required
4 Connecting Wires Single strand as
require
d
5 Patch Cords 4mm as
required

Theory:
Figure: Logic Gates - Types

Figure: Types of Logic Gates – their symbols, description, and Boolean expression
DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Types of Logic Gates – their symbols, Boolean Expressions and Truth Table
DLD LAB MANUAL Dept. OF ECE,GIET
DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Two input NAND gate circuit using Transistor-Transistor Logic (TTL)

Figure: Three input NOR gate circuit using Transistor-Transistor Logic (TTL)
DLD LAB MANUAL Dept. OF ECE,GIET

Figure: Two input NAND gate circuit using Diode-Transistor Logic (TTL)

Figure: Basic gate circuit diode (such as AND gate, diode OR gate)

Procedure:

1. Implement connections (or design as) per the logic or IC pin out diagram.
2. Switch on the power supply.
3. Understand output as per truth table only.
4. Observe the output on LEDs.
5. Verify the truth table as per digital circuit for given set of input combinations.
6. NOTE: Another problem with DTL is that it that the AND and OR gates are non-
regenerative; that is they have a voltage drop across them which when linked together can
cause the voltage to fall significantly and create errors.

Result: All basic logic gates are realized. Its truth tables are verified.

Precautions:
1) All the connections should be correct. Avoid loose contact.
2) Make the connections according to the IC pin diagram. The Vcc and ground should be
applied carefully at the specified pin only.
3) Digital lab kits and ICs should be handled with utmost care.
4) While making connections main voltage should be kept switched off.
5) Never touch live and naked wires

Viva Questions:
1. Discuss input and output voltage levels in DTL logic.
2. Compare all logic gates.
3. Write truth-table of all logic gates.
4. Explain the importance of EX-OR AND EX-NOR gates.
5. Compare TTL and DTL logic.