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6.magnitude Comparator

This document describes the design and implementation of a 2-bit and 8-bit magnitude comparator. It provides the theory of magnitude comparison, truth tables for 2-bit and 4-bit comparators, pin diagrams for the 7485 IC, and logic diagrams. The experiment aims to design a 2-bit comparator using basic gates and an 8-bit comparator using the 7485 IC. Connections are made according to the provided diagrams and inputs are given to observe and verify the outputs against the truth tables.

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Sudhan Hari
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0% found this document useful (0 votes)
92 views3 pages

6.magnitude Comparator

This document describes the design and implementation of a 2-bit and 8-bit magnitude comparator. It provides the theory of magnitude comparison, truth tables for 2-bit and 4-bit comparators, pin diagrams for the 7485 IC, and logic diagrams. The experiment aims to design a 2-bit comparator using basic gates and an 8-bit comparator using the 7485 IC. Connections are made according to the provided diagrams and inputs are given to observe and verify the outputs against the truth tables.

Uploaded by

Sudhan Hari
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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We have A<B, the sequential comparison can be expanded as

EXP NO: 6 DESIGN AND IMPLEMENTATION OFMAGNITUDE


A>B = A3B31 + X3A2B21 + X3X2A1B11 + X3X2X1A0B01
COMPARATOR
A<B = A31B3 + X3A21B2 + X3X2A11B1 + X3X2X1A01B0
AIM:

The same circuit can be used to compare the relative magnitude of two
To design and implement
(i) 2 – bit magnitude comparator using basic gates. BCD digits.
(ii) 8 – bit magnitude comparator using IC 7485. Where, A = B is expanded as,
A = B = (A3 + B3) (A2 + B2) (A1 + B1) (A0 + B0)
APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY. 2 BIT MAGNITUDE COMPARATOR


LOGIC DIAGRAM:
1. AND GATE IC 7408 2
2. X-OR GATE IC 7486 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. 4-BIT MAGNITUDE IC 7485 2
COMPARATOR
6. IC TRAINER KIT - 1
7. PATCH CORDS - required

THEORY:

The comparison of two numbers is an operator that determine one number


is greater than, less than (or) equal to the other number. A magnitude
comparator is a combinational circuit that compares two numbers A and B
and determine their relative magnitude. The outcome of the comparator is
specified by three binary variables that indicate whether A>B, A=B (or) A<B.
A = A3 A2 A1 A0
B = B3 B2 B1 B0
The equality of the two numbers and B is displayed in a combinational
circuit designated by the symbol (A=B). This indicates A greater than B,
then inspect the relative magnitude of pairs of significant digits starting from
most significant position. A is 0 and that of B is 0.
K MAP

TRUTH TABLE
A1 A0 B1 B0 A>B A=B A<B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0
PIN DIAGRAM FOR IC 7485: TRUTH TABLE:

A B A>B A=B A<B


0000 0000 0 1 0
0000 0000

0001 0000 1 0 0
0001 0000

0000 0001 0 0 1
0000 0001
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

LOGIC DIAGRAM:
8 BIT MAGNITUDE COMPARATOR
RESULT:
Thus the 2-bit and 8-bit magnitude comparator was designed and
verified using the logic gates.

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