Set B

Reg. No.

ROYAL UNIVERSITY OF BHUTAN

COLLEGE OF SCIENCE AND TECHNOLOGY
PHUENTSHOLING : BHUTAN

SUMMER SEMESTER EXAMINATION: 2011

Class : BE Third Year Electrical Engineering

Module : Microprocessor and Interfacing

Module Code : E 65

Max. Marks : 50

Max. Time : 3 Hrs

General Instructions:
1. Answer all the questions.

Page 1 of 11
Question No.1 [ 2,2]
1.1 Explain these terms: SSI, MSI, LSI and VLSI.
SSI (Small-scale integration) is the process of a designing a few
circuits on a single chip in the early 1960s. MSI (Medium-scale
integration) is the process of designing more than a hundred
gates on s single chip. LSI (Large-scale integration) is the
process of designing more than a thousand gates on s single chip.
VLSI (Very large-scale integration) is the process of designing
more than a hundred thousand gates on s single chip.
Each 0.5 mark
1.2 Draw the hierarchical relationship between computer hardware
and software. Each 0.4 mark

Computer
Hardware
Operating System

Utility Programs

Assembly and High-level Languages

Application Programs

Page 2 of 11
Question No.2 [ 1,2,5]
2.1 Find the Hex machine code for the following instructions from
the instruction set listed on the 8085 instruction summary, and
identify the number of bytes of each instruction.
MVI B,F0H ;Load the first byte
MVI C,6AH ;Load the second byte
DCR B ;Decrement B by 1
MOV A,C ;Copy C to A
ORI 0CH ;Set 1 for D3–D2
SUI 78H ;Subtract 78H from A
STA 8010H ;Save the result in 8010H
HLT ;End of program
MVI B,F0H Hex machine code = 06 F0 Two-byte instruction 0.1 mark
MVI C,6AH Hex machine code = 0E 6A Two-byte instruction 0.1 mark
DCR B Hex machine code = 05 One-byte instruction 0.1 mark
MOV A,C Hex machine code = 79 One-byte instruction 0.1 mark
ORI 0CH Hex machine code = F6 0C Two-byte instruction 0.2 mark
SUI 78H Hex machine code = D6 78 Two-byte instruction 0.1 mark
STA 8010H Hex machine code = 32 10 80 Three-byte instruction 0.2 mark
HLT Hex machine code = 76 One-byte instruction 0.1 mark
2.2 In Question 2.1, identify the contents of memory location 8010H
after all the instructions are executed.
F6H 2 mark
2.3 In Question 2.1, explain the potential results of the program if
the code 0CH of the ORI instruction is omitted, and identify the
contents of memory location 8010H after all the instructions are
executed.
The processor assumes the code of the next instruction
(SUI:D6H) as the 8-bit data (operand) of logical ORA, logically
ORAs the contents of A with the 8-bit data D6H, and the result
46H is stored in the A. The next code (78H) is assumed as the
instruction MOV A,B, and the contents of B; EFH is copied to
the A. The following two instructions STA 8010H and HLT are
unchanged. 3 mark
Finally, the 8-bit data EFH is stored in the memory location
8010H. 2 mark

Page 3 of 11
Question No.3 [ 1,2,2]
3.1 In the following figure, specify the output line that goes low if
the input (including the enable lines) to the 4-to-16 decoder is
A7 A6 A5 A4 A3 A2 A1 A0
1 1 1 1 1 0 0 1

The line 7 (O7). (01112 = 7H) 1 mark

3.2 List the high-order, low-order, and don‟t care address lines in
the following figure. How many pages of memory does the chip
include?

The high-order address lines are A15-A14, 0.5 mark

the low-order address lines are A11-A0, 0.5 mark
and the don‟t care address line are A13-A12. 0.5 mark
The chip includes 16 pages (4096/256 = 16) 0.5 mark
3.3 In the above figure, identify the memory addresses, assuming all
the don‟t care address lines at logic 1.
The memory addresses range
from 7000H (= 01 11 0000000000002) 1 mark
to 7FFFH (= 01 11 1111111111112). 1 mark
Page 4 of 11
Question No.4 [ 8,8]
4.1 In the following figure, specify the memory address of ROM1,
ROM2, R/WM1, and R/WM2.
The memory addresses of ROM1 range
from 4000H (= 010 00000000000002) 1 mark
to 5FFFH (= 010 11111111111112). 1 mark
The memory addresses of ROM2 range
from A000H (= 101 00000000000002) 1 mark
to BFFFH (= 101 11111111111112). 1 mark
The memory addresses of RW/M1 range
from 6800H (= 011010 00000000002) 1 mark
to 6BFFH (= 011010 11111111112). 1 mark
The memory addresses of RW/M2 range
from 7800H (= 011110 00000000002) 1 mark
to 7BFH (= 011110 11111111112). 1 mark
4.2 In the following figure, eliminate the second [lower] decoder
and connect ( ̅̅̅̅̅) of the first [upper] decoder to (̅̅̅̅ ) of the
R/WM2, and connect (̅̅̅̅̅) of the first [upper] decoder to (̅̅̅̅)
of the R/WM1. Then, identify the primary address ranges and
the mirror (foldback) address ranges of the R/WM1 and R/WM2.
The primary memory addresses of R/WM1 range
from E000H (= 111 000 00000000002) 1 mark
to E3FFH (= 111 000 11111111112). 1 mark
The foldback memory addresses of R/WM1 range
from E400H (= 111 001 00000000002) 1 mark
to FFFFH (= 111 111 11111111112). 1 mark
The primary memory addresses of R/WM2 range
from 6000H (= 011 000 00000000002) 1 mark
to 63FFH (= 011 000 11111111112). 1 mark
The foldback memory addresses of R/WM2 range
from 6400H (= 011 001 00000000002) 1 mark
to 7FFFH (= 011 111 11111111112). 1 mark

Page 5 of 11
Question No.5 [ 2,2,3,1]
5.1 In the following figure, identify the primary port address and the
foldback (mirror) port address for the input device.
The primary port address is F6H (= 1111 01102). 1 mark
The foldback (mirror) port address is FEH (= 1111 11102). 1 mark
5.2 In the following figure, identify the primary port address and the
foldback (mirror) port address for the output device.
The primary port address is F0H (= 1111 00002). 1 mark
The foldback (mirror) port address is F8H (= 1111 10002). 1 mark
5.3 In the following figure, write instructions to read the data from
the input port and write the data to the output port. Use only the
primary address.
IN F6H 1 mark
OUT F0H 1 mark
HLT 1 mark
5.4 In the following figure, which switches should be turned on to
display the number “3”?
S0, S1, S2, S3, and S6 1 mark

Page 6 of 11
Question No.6 [ 2,2,5]
6.1 In the following figure, identify the primary port address and the
foldback (mirror) port address for the common-anode seven-
segment LED port (first digit).
The primary port address is 2FH (= 001 0 11112). 1 mark
The foldback (mirror) port address is 3FH (= 001 1 11112) 1 mark
The primary port addresses are 2FH and 3FH 0.5 marks
The foldback port addresses are 2FH and 3FH 0.5 marks
6.2 In the following figure, identify the primary port address and the
foldback (mirror) port address for the common-anode seven-
segment LED port (second digit).
The primary port address is AFH (= 101 0 11112). 1 mark
The foldback (mirror) port address is BFH (= 101 1 11112) 1 mark
The primary port addresses are AFH and BFH 0.5 marks
The foldback port addresses are A3H and BFH 0.5 marks

Page 7 of 11
6.3 In the following figure, write instructions to display the number
“85” at the common-anode seven-segment LED ports. Use the
primary port address for both of the common-anode seven-
segment LED ports. Final instruction is HLT.
MVI A,80H ;Code for „8‟ to upper LED 1 mark
OUT AFH ;Display at upper LED 1 mark
MVI A,92H ;Code for „5‟ for lower LED 1 mark
OUT 2FH ;Display at lower LED 1 mark
1 mark
HLT ;End of the program

Page 8 of 11
 Appendix 8085 Instruction Summary

Mnemonic Hex Mnemonic Hex Mnemonic Hex Mnemonic Hex

MOV A,A 7F MOV D,C 51 MOV L,E 6B LHLD adr 2A
MOV A,B 78 MOV D,D 52 MOV L,H 6C LDA adr 3A
MOV A,C 79 MOV D,E 53 MOV L,L 6D STAX B 02
MOV A,D 7A MOV D,H 54 MOV L,M 6E STAX D 12
MOV A,E 7B MOV D,L 55 MOV M,A 77 SHLD adr 22
MOV A,H 7C MOV D,M 56 MOV M,B 70 STA adr 32
MOV A,L 7D MOV E,A 5F MOV M,C 71 ADD A 87
MOV A,M 7E MOV E,B 58 MOV M,D 72 ADD B 80
MOV B,A 47 MOV E,C 59 MOV M,E 73 ADD C 81
MOV B,B 40 MOV E,D 5A MOV M,H 74 ADD D 82
MOV B,C 41 MOV E,E 5B MOV M,L 75 ADD E 83
MOV B,D 42 MOV E,H 5C XCHG EB ADD H 84
MOV B,E 43 MOV E,L 5D MVI A,byte 3E ADD L 85
MOV B,H 44 MOV E,M 5E MVI B,byte 06 ADD M 86
MOV B,L 45 MOV H,A 67 MVI C,byte 0E ADC A 8F
MOV B,M 46 MOV H,B 60 MVI D,byte 16 ADC B 88
MOV C,A 4F MOV H,C 61 MVI E,byte 1E ADC C 89
MOV C,B 48 MOV H,D 62 MVI H,byte 26 ADC D 8A
MOV C,C 49 MOV H,E 63 MVI L,byte 2E ADC E 8B
MOV C,D 4A MOV H,H 64 MVI M,byte 36 ADC H 8C
MOV C,E 4B MOV H,L 65 LXI B,dble 01 ADC L 8D
MOV C,H 4C MOV H,M 66 LXI D,dble 11 ADC M 8E
MOV C,L 4D MOV L,A 6F LXI H,dble 21 SUB A 97
MOV C,M 4E MOV L,B 68 LXI SP,dble 31 SUB B 90
MOV D,A 57 MOV L,C 69 LDAX B 0A SUB C 91
MOV D,B 50 MOV L,D 6A LDAX D 1A SUB D 92

Page 9 of 11
Mnemonic Hex Mnemonic Hex Mnemonic Hex Mnemonic Hex
SUB E 93 INX H 23 ANA E A3 CMP L BD
SUB H 94 INX SP 33 ANA H A4 CMP M BE
SUB L 95 DCR A 3D ANA L A5 ADI byte C6
SUB M 96 DCR B 05 ANA M A6 ACI byte CE
SBB A 9F DCR C 0D XRA A AF SUI byte D6
SBB B 98 DCR D 15 XRA B A8 SBI byte DE
SBB C 99 DCR E 1D XRA C A9 ANI byte E6
SBB D 9A DCR H 25 XRA D AA XRI byte EE
SBB E 9B DCR L 2D XRA E AB ORI byte F6
SBB H 9C DCR M 35 XRA H AC CPI byte FE
SBB L 9D DCX B 0B XRA L AD JMP adr C3
SBB M 9E DCX D 1B XRA M AE JNZ adr C2
DAD B 09 DCX H 2B ORA A B7 JZ adr CA
DAD D 19 DCX SP 3B ORA B B0 JNC adr D2
DAD H 29 DAA 27 ORA C B1 JC adr DA
DAD SP 39 CMA 2F ORA D B2 JPO adr E2
INR A 3C STC 37 ORA E B3 JPE adr EA
INR B 04 CMC 3F ORA H B4 JP adr F2
INR C 0C RLC 07 ORA L B5 JM adr FA
INR D 14 RRC 0F ORA M B6 PCHL E9
INR E 1C RAL 17 CMP A BF CALL adr CD
INR H 24 RAR 1F CMP B B8 CNZ adr C4
INR L 2C ANA A A7 CMP C B9 CZ adr CC
INR M 34 ANA B A0 CMP D BA CNC adr D4
INX B 03 ANA C A1 CMP E BB CC adr DC
INX D 13 ANA D A2 CMP H BC CPO adr E4

Page 10 of 11
Mnemonic Hex Mnemonic Hex
CPE adr EC POP H E1
CP adr F4 POP PSW F1
CM adr FC XTHL E3
RET C9 SPHL F9
RNZ C0 OUT byte D3
RZ C8 IN byte DB
RNC D0 DI F3
RC D8 EI FB
RPO E0 NOP 00
RPE E8 HLT 76
RP F0 RIM 20
RM F8 SIM 30
RST 0 C7
RST 1 CF
RST 2 D7
RST 3 DF
RST 4 E7
RST 5 EF
RST 6 F7
RST 7 FF
PUSH B C5
PUSH D D5
PUSH H E5
PUSH PSW F5
POP B C1
POP D D1

Page 11 of 11