Expt 1

Experiment 1:
Digital trainer and SSI Gates Familiarization
OBJECTIVES
1. To identify the input and output terminals of a gate in an IC package.

2. To identify the supply terminals of SSI IC.
3. To determine the state of input and output terminals of SSI gates using Logic Probe.
4. To be able to use the digital trainer properly
5. To able to determine and understand the functions of the different parts of digital
trainer.
BASIC INFORMATION
Digital Trainer
The different parts of the digital trainer are designed so that it will be convenient to
construct and test simple digital circuits.
Parts of the Digital Trainer:
1. Breadboard/ Protoboard
The breadboard or protoboard serves as the temporary circuit board for

experimental circuit. The components are placed in the board and connected using
solid wires (jumpers). Additional breadboard can be used if the circuit is large and
cannot be accommodated in the board provided in the trainer.
2. Power Supply
The power supply provides a constant or regulated DC output voltage of 5V. this
power supply is the same power used all throughout the trainer.
3. LEDs
There are eight LEDs available. These are activated by supplying a TTL high to
each of the corresponding terminal block pins.
4. Switches
There are eight available switches in the kit, six (Sw0 to Sw0) of which are ordinary
toggle switched while the two others are debounced switches (Sw6 & Sw7). The
common node of the single pole double throw switches is connected to the wire
holder while the other two nodes to ground and Vcc.
5. 7-segment Display
The two seven segment displays are driven by 7447 BCD-to-seven-segment

display decoders/drivers. The said driver has 4 inputs corresponding to the binary
code of the desired decimal output on the seven segment display. Inputs not
connected to any value are considered as ‘floating’ HIGH, thus causing the display
to turn off when not in use.
6. Digital Clocks
Two clocks are provided by the kit, one having a fix frequency of 1KHz and the
other having a variable frequency of 3-50Hz. “OUT” is for the fix clock, and
“OUT*” is for variable clock.
7. The Logic Probe
Two logic probes are provided with logic LOW, HIGH, UNDEFINED/OPEN (not high
or low) CIRCUIT indicator. It is labeled “LP1” and “LP2”
SSI Gates
Some TTL circuits as shown in Figure 1-1. Each IC is enclosed within a 14 or 16

pin package. A notch placed on the left side of the package is used as reference for the
pin numbers. The pins are numbered along the two sides starting from the notch and
continuing counterclockwise. The inputs and outputs of the gates are connected to the
package pins.
The TTL IC’s are distinguished by their numerical designation, e.g. the 5400 and
7400 series. The former has a wide temperature range is suitable for military use, while
the latter has a narrower temperature range and is suitable for commercial use. The
numerical designation of the 7400 series means that the IC packages are numbered as
7400, 7401, 7402, etc.
The differences between the various TTL series are in their electrical
characteristics, e.g., power dissipation, propagation delay, and switching speed. They do
not differ in pin assignment NOR on the logic operation performed by the internal circuits.
For example, all the ICS listed in Table 1-1 with an 86 number, no matter what the prefix,
contain four exclusive OR gates with the same pin assignment in each package.
MATERIALS
1 Logic Probe 1 Long Nose Pliers

1 Fixed Power Supply 1 Wire Stripper Pliers
1 Protoboard Connecting Wires
1 Digital Trainer
Integrated Circuits (ICs)
1 74LS00 1 74LS08
1 74LS02 1 74LS32
1 74LS04 1 74LS86
PROCEDURES
1. Examine the ICs supplied to you. The IC number is printed on the surface of each
IC.
2. Connect the 74LS00 as shown in Figure 1-2. Supply the IC with 5V and Ground.
3. Using the logic probe, test the status condition or logic level at the input and output
terminals.
4. Of each gate in the IC. Record the logic values in the corresponding tables.
5. Remove the IC mounted on the protoboard and replace it with another IC.
6. Repeat step 3 for each of the other ICs.
7. Repeat steps 2 to 4 using the digital trainer. Compare results.
14 13 12 11 10 9 8 14 13 12 11 10 9 8
Vcc Vcc
GND GND
1 2 3 4 5 1 2 3 4 5
6 7 6 7
74LS08 - Quad 2-Input AND Gate 74LS00 - Quad 2-Input NAND Gate
14 13 12 11 10 9 8 14 13 12 11 10 9 8
Vcc Vcc
GND GND
1 2 3 4 5 1 2 3 4 5
6 7 6 7
74LS32 - Quad 2-Input OR Gate 74LS86 - Quad 2-Input XOR Gate
14 13 12 11 10 9 8 14 13 12 11 10 9 8
Vcc
Vcc
GND GND
1 2 3 4 5 6 7 1 2 3 4 5
6 7
74LS02 - Quad 2-Input NOR Gate 74LS04 - Hex Inverter
Figure 1-1 Basic Gates Pin Configuration

Figure 1-2 Experimental Circuit Set-up
DATA AND RESULTS
Table 1-1 Test Results for 74LS00 IC Table 1-2 Test Results for 74LS02 IC
Input Terminals Output Terminals Input Terminals Output Terminals
Pin Logic Pin Logic Pin Logic Pin Logic
No. Level No. Level No. Level No. Level
1 3 2 1
2 6 3 4
4 8 5 10
5 11 6 13
9 8
10 9
12 11
13 12
1 3 1 3
2 6 2 6
4 8 4 8
5 11 5 11
9 9
10 10
12 12
13 13

1 3 1 2
2 6 3 4
4 8 5 6
5 11 9 8
9 11 10
10 13 12
12
13
QUESTIONS
1. What is the logical equivalent of the “hang” input?
2. Identify the following ICs with the same pin configuration.
3. Describe the pin configurations of 74LS02 and 74LS04 ICs.
4. Describe the functionalities of the Digital trainer.
5. What are the possible benefits in using digital trainer in the

construction of digital circuits?

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Experiment 1:

Digital trainer and SSI Gates Familiarization

1. To identify the input and output terminals of a gate in an IC package.

The breadboard or protoboard serves as the temporary circuit board for

The two seven segment displays are driven by 7447 BCD-to-seven-segment

7. The Logic Probe

Some TTL circuits as shown in Figure 1-1. Each IC is enclosed within a 14 or 16

1 Logic Probe 1 Long Nose Pliers

Figure 1-1 Basic Gates Pin Configuration

Input Terminals Output Terminals Input Terminals Output Terminals

3. Describe the pin configurations of 74LS02 and 74LS04 ICs.

4. Describe the functionalities of the Digital trainer.

5. What are the possible benefits in using digital trainer in the

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