2017 IEEE 3rd International Conference on Sensing, Signal Processing and Security (ICSSS)

Low Voltage Low Power Sub-threshold Operational

Amplifier in 180nm CMOS
Chetali Yadav1, Sunita Prasad2
VLSI Design Deptt, CDAC
Noida, India

Abstract—A two-stage operational amplifier for biomedical Where W= gate width, L = gate length, Vgs = applied gate to
applications is presented in this paper. In the Op-Amp design, all source voltage, Vth= Threshold voltage of the MOSFET,VT =
transistors have been operated in sub-threshold region for low kT/q=26mv (at room temperature), n=non ideality factor
voltage low power application. The proposed Op-Amp has been ( ≈1.53 for PMOS ≈1.48 for NMOS), I0 is a process
designed based on TSMC foundry 180nm process and simulated
parameter.
in Cadence analog design environment. The proposed circuit
generates a 40dB gain, 114 KHz UGBW, 72 deg phase margin &
total power consumption is just 112nW with 0.8V battery.

Keywords—Operational Amplifier; Sub-threshold; Low Power;

Analog IC design; Biomedical

I. INTRODUCTION

The implantable devices in biomedical application such as

pacemaker & monitoring of Neuro-muscular activities etc
require biomedical sensors with very low power consumption
so that implanted battery can work for more numbers of years.
For reducing power consumption in the operational amplifier,
we will operate MOSFETs at low supply voltage and low
current. The current consumption & characteristics of a Fig 1: Different operating regions of MOSFET
MOSFET varies with respect to its operating region. Among
these different regions sub-threshold region is used for ultra Normally << 1
low power circuit designing. Sub-threshold biased MOSFET
can operate with lower voltage power supply. It is generally This diffusion current is given by:
assumed that the current through the MOSFET is zero when
gate voltage drops below threshold voltage, but in fact it W −
decreases exponentially. And if a MOSFET is operated with = exp
the gate voltage just below threshold voltage i.e. in sub- L
threshold or weak inversion region, the power consumption is The current of MOSFET varies exponentially similar to
reduced[2]. The biomedical signals are low frequency signals current of a BJT. Therefore the MOSFET behaves similar to
with frequency less than few kilohertz. Also biomedical BJT in the sub-threshold region.
signals are very weak signals order of a few microvolts. The
biomedical signals are slow & does not require very high slew In sub-threshold region, the trans-conductance and drain
rate[1]. These requirements can be met with operational resistance are given by
amplifier operating in sub-threshold region.

= =
II. SUB-THRESHOLD OPERATED MOSFET

Where =
The different operating regions of MOSFET are shown in fig
1. The MOSFET will operate in sub-threshold or weak
inversion region for Vgs < VTH & Vds approximately greater 1
= =
than 4* KT/q . The current of MOSFET in the sub-threshold
region is a diffusion current[3-5].
Where, D is the DIBM coefficient.
−
= 1−

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 2017 IEEE 3rd International Conference on Sensing, Signal Processing and Security (ICSSS)

III. SUBTHRESHOLD OPERATIONAL AMPLIFIER

=
The first stage of the op amp is a differential amplifier. The | |
input of first stage has been implemented using NMOS pair.
The load is implemented using PMOS current mirror. This
combination of NMOS input transistors with PMOS current The resistance of NMOS in deep triode region
mirror load provides high gain because trans-conductance of
NMOS transistor is higher compared to PMOS. For output
stage a common source amplifiers has been used which
=
( )
provides higher gain as well as higher output voltage swing. A
complete schematic of op amp is shown in figure 2. The nulling resistor is implemented using transmission gate
for increasing input signal dynamic range.

M3 M4 M6 IV. SIMULATION RESULTS

IBIAS M9
CC
VOUT
- M1 M2 CL The sub-threshold operational amplifier circuit given in Fig. 2
M10
VIN has been simulated using TSMC 180nm CMOS process
+ library and Cadence Analog Design Environment. The power
M5
M7 supply of +0.8V is used for biasing operational amplifier. The
M8 capacitor of 0.5pF is used as load at the output for simulation.

50.00
40.00
30.00
Fig 2: Two stage Sub-threshold Operational Amplifier
Gain (dB)

20.00
10.00
0.00
= -10.00
+ + -20.00
-30.00
1E+0 1E+2 1E+4 1E+6
= Freq(Hz)
( )( )

Gain bandwidth product 0.00

= -50.00
Phase(deg)

-100.00
Slew rate
-150.00
=
-200.00
Resistance of NMOS M9 in parallel with PMOS M10 used 1E+0 1E+2 1E+4 1E+6
as variable resistor shall be
Freq (Hz)

1 + Fig 3: Gain and Phase plot of op amp with frequency

∥ =
Figure 3 shows the frequency response of op amp. The result
For reducing effect of right hand plane zero, a nulling resistor shows small-signal voltage gain which is 40 dB and phase
RZ along with Compensation capacitor Cc is used. The nulling margin of 72°. It can also be seen that the unity gain
resistor has been implemented using a transmission gate (TG). bandwidth (UGB) of op amp is 114 KHz.
The gate of NMOS transistor is connected to VDD while gate
of PMOS transistor M10 is biased at VSS. The resistance of
PMOS in deep triode region is given by

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 2017 IEEE 3rd International Conference on Sensing, Signal Processing and Security (ICSSS)

100.00 V. LAYOUT

80.00
CMRR (dB)

60.00
40.00
20.00
0.00
1E+0 1E+2 1E+4 1E+6
Freq (Hz)

Fig 4: CMRR of OP AMP with Frequency

Fig 6: Layout of Sub-threshold Operational Amplifier
The operational amplifier was simulated using differential-
mode and common mode inputs. The ratio of differential The layout of Sub-threshold OP AMP is shown in fig 6. The
mode and common mode gain provides the CMRR of 80 dB. DRC and LVS check on layout were successfully completed.
This implies that op amp has a very good rejection to the Post layout simulation after Parasitic extraction provides
common-mode noise. approximately same results. The chip area required for the
layout is approximately 0.009mm2.

VI. CONCLUSION

In this paper, we presented design of a two-stage operational

amplifier for low voltage and low power systems using 180nm
CMOS technology. The designed circuit has been validated
using professional software of Cadence. This OP AMP
provides 40dB gain, 72 degree phase margin, 80dB CMRR &
consumes just 112nW making it fit for biomedical systems
such as cardiac pacemaker, electrocardiogram (ECG) etc.
Fig 5: Slew rate of Operational Amplifier where there is no requirement of high bandwidth and slew
rate.
Using transient analysis, the change between the output-
voltage with respect to time is obtained for calculating the
slew rate. The slope of output-voltage with respect to time ACKNOWLEDGMENT
calculated as 5V/msec. Authors would like to give special thanks to faculty members
of VLSI department of CDAC NOIDA for their support &
The OP amp consumes 140nA current at power of 0.8V. The encouragement. Authors are thankful to the director &
total power consumption is 112nW which is quite low. Scientists/ Engineers of Semiconductor Laboratory (ISRO)
Mohali, India for their expert guidance.
The simulated results of OP Amp are summarized in table
below
REFERENCES
Parameters Simulated results
Supply Voltage 0.8V [1] Sanjay Singh Rajput, Ashish Singh, Ashwani K. Chandel, Rajeevan
Chandel, “Design of Low-Power High-Gain Operational Amplifier for
Current Consumption 140nA Bio-Medical Applications”, 2016 IEEE Computer Society Annual
Power Consumption 112nW Symposium on VLSI , Pages: 355 – 360.
DC Gain 40dB [2] Farzin Akbar, Marco Ramsbeck, Elias Kögel, “Design, Fabrication, and
Unity gain BW 114KHz Characterization of Ultralow Current Operational-Amplifier in the Weak
Inversion Mode in XFAB-XT018 Technology,” IEEE SOI-3D-
CMRR 80dB Subthreshold Microelectronics Technology Unified Conference (S3S)
PSRR 50dB Year: 2016, Pages: 1–3.
Slew Rate 5V/msec [3] Arun Katara, Riya Balwani , Priya Wagh, Prachi Salankar, “Design of
Phase Margin 72 Deg OP-AMP using CMOS Technology & Its Application”, IEEE
International Conference on Electrical, Electronics, and Optimization
Chip Area 0.009mm2 Techniques (ICEEOT) – 2016, pages 3633-3636.
Process 180nm CMOS [4] Yushun Guo, “An accurate design approach for two-stage CMOS
operational amplifiers,” IEEE Asia Pacific Conference on Circuits and
Systems (APCCAS)Year: 2016, Pages: 563 – 566.

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 2017 IEEE 3rd International Conference on Sensing, Signal Processing and Security (ICSSS)

[5] Ken Ueno,Tetsuya Hirose Tetsuya Asai, Yoshihito Amemiya, “1-μW

600-ppm/◦C Current Reference Circuit Consisting of Subthreshold
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