2017 2nd International Conference on Telecommunication and Networks (TEL-NET 2017)

Performance analysis of a low power high speed

full adder
Paro Bajpai, Priyanka Mittal Amita Rana, Bhupesh Aneja
Department of ECE, IGDTUW Department of ICE, JSSATE
Delhi, India Noida, India
[email protected], [email protected] [email protected], [email protected]
Abstract— the paper presents a performance analysis of a low
power high speed full adder which shows that how power Two important characteristics of CMOS devices are high
dissipation become low using the different technologies in a
noise immunity and low static power consumption. Significant
Cadence Virtuoso tool. The design was first implemented in
power is only drawn when the transistors in the CMOS device
250nm technology for 16 CMOS transistor further it was
implemented in various other technologies. In paper the first part
are switching between on and off states. Consequently, CMOS
deals with the implementation and then the comparison of 16 devices do not produce as much waste heat as other forms of
transistors in all technologies like 250nm, 180nm, 90nm, 45nm, logic. CMOS also allows a high density of logic functions on a
32nm, 22nm and 16nm. The next part deals with the chip. It was primarily for this reason that CMOS became the
implementation of full adder circuit by reduce the number of most used technology to be implemented in VLSI chips [5].
transistors from 16 to 6 CMOS transistor. We observe that the The phrase "metal– oxide–semiconductor" is a reference to the
power dissipation become very low using 6 transistors in 250nm physical structure of certain field-effect transistors, having a
technology as compared with the 16 transistors in various other metal gate electrode placed on top of an oxide insulator, which
technologies. in turn is on top of a semiconductor.
In this paper different full adders are compared using
Keywords—Hybrid Design; Full Adder; CMOS Transistor; different technologies such as 250nm, 180nm, 90nm, 45nm,
Power Dissipation; Cadence Virtuoso tool. 32nm, 22nm and 16nm.

I. INTRODUCTION In this paper the CMOS circuit design is implemented in

As the technology is changing and the electronic market various technologies with different number of transistors.
becoming more competitive The battery operated portable Section II explains the basic module of sum and carry. In
devices such as mobile phones, tablet, i-phone are very much section III 16T Transistor circuit is implemented in 250nm
in demand in which longer battery life is required. In these the technology. The various technologies comparison of 16T and
VLSI and ultra large-scale integration designs are used in also the 6T implementation is explain in section IV.
which the fundamental and essential block is a full adder. The
adder plays an important role in the complexity of the circuit. II. MODULE OF SUM AND CARRY
Full Adder consists of three input and two outputs. It can
The power consumed for any given function in CMOS add 3 digits at a time. The bits A and B which are to be added
circuit must be reduced for either of the two different reasons:
come from the two registers and the third input come from the
One of these reasons is to reduce heat dissipation in order to
carry generated by the previous addition. It produces two
allow a large density of functions to be incorporated on an IC
outputs: SUM and CARRY OUT. Simplified expression for
chip. Any amount of power dissipation is worthwhile as long
as it doesn‟t degrade overall circuit performance. The other the output variables sum (S) and output carry (Cout) are
reason is to save energy in battery operated instruments same given in following equations.
as electronic watches where average power is in microwatts Sum = A ⊕ B ⊕ Cin (1.1)
[9]. Carry = AB + BCin + ACin (1.2)
TABLE I. TRUTH TABLE OF FULL ADDER
Several Full Adders logic circuits designs have been used A B Cin Sum Cout
so far. Each designs have their own merits and demerits. The 0 0 0 0 0
full adder is used for performing arithmetic operations such as
0 0 1 1 0
addition, subtraction, multiplication and division. To reduce
overall power consumption of chip the power consumption of 0 1 0 1 0
full adder has to be reduced. The low power CMOS logic 0 1 1 0 1
circuit is highly appreciable in all. CMOS logic circuits 1 0 0 1 0
consist of PMOS and NMOS transistors. Number of 1 0 1 0 1
transistors used are also the major constraint for the power 1 1 0 0 1
dissipation. Reducing the number of transistors may lead to
1 1 1 1 1
reduces power but sometimes does not improve.
 2017 2nd International Conference on Telecommunication and Networks (TEL-NET 2017)

There are two factors affecting the performance of a full input carry signal passes or propagates through only one
adder design: one is the full adder logic architecture, and the transmission gate, i.e., Mn90 and Mp98. Hence it reduces path
other is the circuit design techniques to perform the logic required for carry propagation. Large channel width transistors
architecture function. Therefore, the full adder design are used for transmission gates. Here Mn90, Mp98, Mn91 and
approach requires using different types of logic architecture Mp99 form the transmission gates. Hence it results in reducing
and circuit design technique to improve the total performance the delay for some extent [4].
[2].
The truth table gives all possible input/output relationships
for the full adder. A and B are the inputs from the respective
digits of the registers to be added and Ci is the input for any
carry generated by the previous stage. The SUM output gives
binary addition of A, B, Cin. The other output generates the
carry Cout to be added to the next stage.

By considering these SUM and CARRY Module we

construct a Full Adder Circuit with 16T first in 250nm
technology and then work on its Power Dissipation.

III. 16T CMOS CIRCUIT IN 250NM TECHNOLOGY

We implement the 16T Full Adder circuit [10] in 250nm

technology. 16T full adder consists of 16 CMOS transistors.
Fig. 1. Schematic Diagram of XNOR module [10]
A, B and Cin are the inputs and sum and carry are the outputs.
The problem we face in designing this circuit is that it more
complicated. As the power we obtained in this is considerably
low it is about 2.77mw. But our aim is to reduce this power
also.

Fig. 2. Schematic Diagram of Carry Generation Module [10]

Fig. 4. Schematic Diagram of 16T Full Adder

VOLTAGE SOURCE CURRENTS

NAME CURRENT
Fig. 3. Hybrid Full Adder [10] V-V1 -1 232E-04

In this there is a significant reduction in power as it makes V-V3 -1 154E-04

use of a weak inverter (transistors having small channel V-V4 -1 118E-04
width). The XOR/XNOR circuits that are designed in prior
literatures uses 6 transistors to give better output swing. Here V-V5 -1 232E-04
also XNOR module consists of 6 transistors but, the V-V6 -1 000E+00
arrangement of transistors are different. It is arranged in such a
manner that, it gives lower power and higher speed compared Total Power Dissipation 2.77E-03 Watts.
to other literatures [4].
The schematic of carry generation module is given in
Fig.2. The transistors Mp98, Mn90, Mp99 and Mn91 are
implemented in order to achieve the output carry signal. Here
 2017 2nd International Conference on Telecommunication and Networks (TEL-NET 2017)

IV. COMPARISON OF VARIOUS TECHNOLOGIES Total Power Dissipation 9.38E-04 Watts.

To implement the circuit in various other technologies we
go for the technologies like 180nm, 90nm,, 45nm, 32nm,
22nm and 16nm. First we implement the same circuit in
180nm technology. All simulation of proposed full adder
circuit is performed in Cadence Virtuoso tool. In this we found
that first it increases the power. By this we come to this result
that it doesn’t mean that the power dissipation reduces as if we
decrease the technology. The results are:

VOLTAGE SOURCE CURRENTS

NAME CURRENT
V_V1 -3.061E-04
V_V3 7.429E-12
Fig. 5. Schematic Diagram of 6T Full Adder
V_V2 3.061E-04
V_V5 -3.130E-04
V_V6 3.060E-04
Total Power Dissipation 3.10E-03 Watts.

After this we tried it into 45nm technology. In this we

observe that the power is become low but not upto a such
extent. We further opt a new technology i.e. 32nm in which
we found surprising result that power does not change as it is
equal to the 45nm. Now further as we changes technologies no
change were found. The result are almost same for all the
technologies which are shown below:

VOLTAGE SOURCE CURRENTS

NAME CURRENT
V_V5 -1.932E-04
Fig. 6. 6T Full Adder Simulation Result
V_V6 1.894E-04
V_V1 -1.896E-04
The power become extremely low from 1.91mw it reduces to
V_V2 1.896E-04 .98mw. This is surprisingly good result. The performance
V_V7 6.221E-13 analysis of each hybrid full adder in different technologies
having different number of transistors are studied and
Total Power Dissipation 1.91E-03 Watts. tabulated. Table II shows the details in a tabular form.

Then we go for the next circuit which is of 6T. 6T full

adder consists of 6 CMOS transistors. A, B and Cin are the TABLE II. SUMMARY OF THE POWER AND NO. OF TRANSISTORS USED
inputs and sum and carry are the outputs. We tried so many
circuits in 6T with capacitor without capacitors. But the circuit S. No. Technologies No. of Power
which gives the good result is shown in fig.5 is by 6T in Transistors Dissipation
250nm technology.
1 250nm 16T 2.77mw
Circuit of 6T also shows a good result.
2 180nm 16T 3.10mw
VOLTAGE SOURCE CURRENTS
NAME CURRENT 3 45nm 16T 1.91mw
4 32nm 16T 1.91mw
V_V1 0.000E+00
V_V2 3.241E-19 5 22nm 16T 1.91mw
V_V3 0.000E+00 6 16nm 16T 1.91mw
V_V4 1.875E-04 7 250nm 6T 0.98mw
V_V5 -1.875E-04
 2017 2nd International Conference on Telecommunication and Networks (TEL-NET 2017)

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