Scribd
Upload
50 views7 pages

Digital Circuits (2) - CH - 4 - Problems #2

The document contains problems and solutions related to digital logic circuits. Problem 4.53 asks to develop and simulate a structural model of a decimal adder circuit. The solution provides a module that models the decimal adder circuit using continuous assignments. It performs full adder logic on the input bits A, B and carry in to calculate the sum and output carry. The output carry is then fed back and added to the sum to generate the final output.

Uploaded by

jameg20458
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
50 views7 pages

Digital Circuits (2) - CH - 4 - Problems #2

The document contains problems and solutions related to digital logic circuits. Problem 4.53 asks to develop and simulate a structural model of a decimal adder circuit. The solution provides a module that models the decimal adder circuit using continuous assignments. It performs full adder logic on the input bits A, B and carry in to calculate the sum and output carry. The output carry is then fed back and added to the sum to generate the final output.

Uploaded by

jameg20458
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 7

Al-Azhar University

Faculty of Engineering
Electrical Engineering Dep.
2nd Year Communication

Chapter 4
Problems #2

Eng. Abdallah Mohamed


module ALU_16_bit (
output reg [15:0] Y ,
input [15:0] A,B,
input [2 :0] Sel );
always@(*)
case( Sel)
3'd0: Y <= 16'b0 ;
3'd1: Y <= A & B ;
3'd2: Y <= A | B ;
3'd3: Y <= A ^ B ;
3'd4: Y <= ~ A ;
3'd5: Y <= A - B ;
3'd6: Y <= A + B ;
3'd7: Y <= 16'hff ;
endcase
endmodule

2
4.48: Develop and modify the eight-bit ALU specified in Problem 4.44 so that it has three-
state output controlled by an enable input, En . Write a test bench and simulate the circuit.

module ALU_16_bit ( output reg [15:0] Y , module t_ALU_16_bit;


input [15:0] A,B, input [2 :0] Sel, wire [15:0] Y ;
input en ); reg [15:0] A,B; reg [2 :0] Sel;
always@(*) reg en;
if (~en) Y <= 8'dz; ALU_16_bit M(Y, A, B, Sel);
else initial
case( Sel) begin
3'd0: Y <= 16'b0 ; A=0; B=0; Sel=0; en=0;
3'd1: Y <= A & B ; #100 A=16'd20; B=16'd10; en=1;
3'd2: Y <= A | B ; end
3'd3: Y <= A ^ B ; always
3'd4: Y <= ~ A ; #100 Sel=Sel+1;
3'd5: Y <= A - B ; always
3'd6: Y <= A + B ; #300 en=~en;
3'd7: Y <= 16'hff ; endmodule
endcase
endmodule

3
4.51: Develop and simulate a behavioral model of the ABCD-to-seven-
segment decoder described in Problem 4.9.
module Seven_Segment_Dec (
output reg [6:0] Y,
input [3:0]BCD );
always@(*) module t_Seven_Segment_Dec;
case ( BCD) wire [6:0] Y;
//abcdefg Common Cathod reg [0:3]BCD;
0: Y=7'b1111110; //f Seven_Segment_Dec M(Y ,BCD);
1: Y=7'b0110000; initial
2: Y=7'b1101101; begin
3: Y=7'b1111001; BCD=0;
4: Y=7'b0110011; repeat (10) #100 BCD=BCD+1;
5: Y=7'b1011011; end
6: Y=7'b1011111; endmodule
7: Y=7'b1110000;
8: Y=7'b1111111;
9: Y=7'b1111011;
endcase
endmodule
4
4.52: Using a continuous assignment, develop and simulate a dataflow model of
(a) The four-bit incrementer described in Problem 4.11(a).
(b) The four-bit decrementer described in Problem 4.11(b).
(a): incrementer
module Sim_Incrementer_4_Bit;
module Incrementer_4_Bit ( wire [3:0]Sum;
output [3:0]Sum, output Carry, wire Carry;
input [3:0]A ); reg [3:0] A;
assign {Carry, Sum} = A+1; Incrementer_4_Bit M(Sum, Carry, A);
initial
endmodule
begin
A=4'b0000;
#100 A=4'b0001;
#100 A=4'b0010;
end
endmodule

5
4.52: Using a continuous assignment, develop and simulate a dataflow model of
(a) The four-bit incrementer described in Problem 4.11(a).
(b) The four-bit decrementer described in Problem 4.11(b).
(b): decrementer
module Sim_Incrementer_4_Bit;
module Incrementer_4_Bit ( wire [3:0]Sum;
output [3:0]Sum, output Carry, wire Carry;
input [3:0]A ); reg [3:0] A;
assign {Carry, Sum} = A-1; Incrementer_4_Bit M(Sum, Carry, A);
initial
endmodule
begin
A=4'b0000;
#100 A=4'b0001;
#100 A=4'b0010;
end
endmodule

6
4.53: Develop and simulate a structural model of the decimal adder shown in Fig. 4.14

module Decimal_adder(
output [3:0] Sum, output Output_carry,
input [3:0] A,B, input Carry_in);
wire [3:0] Z, Addend_i;
wire and_1, and_2, K;
assign {K, Z}=A + B + Carry_in;
assign and_1 = Z[3] & Z[2];
assign and_2 = Z[3] & Z[1];
assign Output_carry=and_2 | and_1 | K;
assign Addend_i ={1'b0, Output_carry, Output_carry,1'b0};
assign Sum = Addend_i + Z;
endmodule

You might also like