Chapter 9

Analog-to-Digital (ATD) Converter

Chapter Problems

• Fundamental

1. An analog signal has a spectrum (frequency content) which varies from 400 Hz to 5.9 KHz. It is to be
sampled at a rate of 10,000 samples per second. Is the sampling rate adequate to allow reconstruction
of the signal?

Answer: The Nyquist criterion indicates that a signal should be sampled at a minimum of twice the
highest frequency content in the signal. Applying the Nyquist criterion, the analog signal should be
sampled at a least 11.8 KHz. Therefore, the sampling rate of 10,000 Hz is not adequate.
2. The HC12 analog-to-digital converter system converts each analog sample to an eight bit unsigned bi-
nary value. What is the resolution of the converter? Assume that the reference voltages for the HC12
designated as VRH and VRL are 4 volts and 1 volt, respectively.
Answer:

Resolution = (VRH − VRL )/(number of steps)

(4 V − 1 V )/(256 steps) = 11.72 millivolts/step

3. The S12 microcontroller allows the selection of either 8-bit or 10-bit ATD resolution, what is the reso-
lution of the S12 ATD converter when the converter is set for 8-bit resolution? What if the converter
is set for 10-bit resolution? Assume that the reference voltages VRH and VRL are 5 volts and 0 volt,
respectively.
Answer: The two reference levels chosen for our ATD converter is 5.0 volts for VRH and 0 volts for
VRL . If we divide the voltage span between these two references into 256 identically spaced levels, the
voltage difference (quantum) represented by each step is:

(5 V − 0 V)/(256 steps) = 19.53 millivolts/step

85
86 CHAPTER 9. ANALOG-TO-DIGITAL (ATD) CONVERTER

Intuitively, if we increase the number of steps between the two voltage references, the individual voltage
steps become smaller or the converter resolution improves. In general, resolution may be described by:

Resolution = (VRH − VRL )/(number of steps)

We can tie together all of these concepts with:

Resolution = (VRH − VRL )/2b

Assume that the reference voltages for the S12 designated as VRH and VRL are 5 volts and 0 volts,
respectively. The resolution is given by:

Resolution = (VRH − VRL )/(2b ) = (5 − 0)/(1024) = 4.88V

4. What is the advantage of using ATD 10-bit resolution over 8-bit resolution? Is there a disadvantage?
Why not always set the microcontroller for 10-bit resolution?
Answer: With 10 bits unknown voltages can be resolved to 4.88 mV; whereas, with 8 bits resolution is
19.56 mV. The results of a 10-bit ATD conversion requires an unsigned integer variable for representa-
tion; whereas, an 8-bit result may be represented with an unsigned character variable. The resolution
must be chosen for the application at hand.
5. A 2 KHz square wave is to be sampled using an analog-to-digital conversion system. What should the
sampling frequency be?

Answer: The Nyquist criterion indicates that a signal should be sampled at a minimum of twice the
highest frequency content in the signal. A square wave has significant frequency content up to 10 times
the fundamental frequency or in this example 20 KHz. Applying the Nyquist criterion, the analog signal
should be sampled at a least 40 KHz.
6. In the question above, how many bits of binary data is generated per second assuming an eight bit
analog-to-digital converter?

Answer: With the signal sampled at 40,000 times per second, 320 Kbytes per second are generated
(40,000 samples x 8 bits/sample).
7. What is the dynamic range of the ATD system aboard the HC12? Explain.

Answer: DR(dB) = 6.02n = 6.02(8) = 48.16 dB

8. What is aliasing? Describe two methods to avoid aliasing?

Answer: If unwanted frequency components cause the Nyquist criterion to be violated, frequency
folding or aliasing will occur. In the process of recovering the signal, the folded part of the spectrum
causes distortion in the recovered signal which can not be removed by filtering from the recovered signal.
Frequency folding is eliminated by using a LPF which has a cutoff frequency corresponding to fh , the
expected frequency content of the signal.
9. If VRH = 5.0 V and VRL = 0 V, what digital value is returned when the ATD system converts the
following voltage assuming an 8 bit conversion?
– 5.0 volts
– 0.0 volts
– 2.7 volts
– 3.2 volts
– 1.2 volts
 89

0 volts = 500 mV ∗ K + B

K = -9.33, B = 4.72 volts

13. What analog value corresponds to the HC12 converter’s maximum digital output (all 1’s) when VRH =
5.0 V and VRL = 0 V ?

Answer:

Vmax = F S(1 − 2−n )

Vmax = 5(1 − 2−8 ) = 4.98 volts

14. Repeat the question above for the S12 processor.
Answer:

Vmax = F S(1 − 2−n )

Vmax = 5(1 − 2−10 ) = 4.995 volts

• Advanced
1. Specify the contents of the ATDCTL2 register to power up the ATD system and set the ATD for fast
flag clearing operations.
Answer: To power up the Analog-to-Digital (ATD) converter, the ATD Power Up (ADPU) bit (bit 7)
of the ATD Control Register (ATDCTL2) must be set to logic “1.” To enable the ATD for fast flag
clearing, the ATD Fast Flag Clear All (AFFC) bit (bit 6) must be set to logic “1.”
Therefore, a “1100 0000” ($C0) must be loaded into the ATDCTL2 register.
2. What is meant by fast flag clearing operations?
Answer: Fast flag clearing means that any access to a result register (ATD0-7) will cause the associated
CCF flag to clear automatically if it was set at the time.
3. Specify the contents of the ATDCTL5 register to configure the ATD system for a continuous sequence
of conversions with 4 conversions per sequence on ATD channels 4 through 7? Where will the results of
these conversions be placed?

Answer: The Select 8 Channel Mode (S8CM) bit (bit 6) must be set to logic “0” to set a conversion
sequence of four conversions. The Enable Continuous Channel Scan (SCAN) bit (bit 5) must be set
to logic “1” for a continuous conversion sequence. The Enable Multichannel Conversion (MULT) bit
(bit 4) must be set to logic “1” to configure the ATD sequencer to perform sequential conversions in a
specific channel group. The “CD” and “CC” bit must be set to “01” to scan channels AN4 through AN7.
Putting all this information together provides the control word “0011 01XX”. Where “XX” indicates
don’t care bit values. Therefore, a $34 should be loaded to the ATD Control Register 5 (ATDCTL5).
The results of the conversions will be placed in ATD Converter Result Registers 0-3.
4. Repeat the question above for the S12 processor.
Answer: The S12 ATD registers should be set in the following manner:
– ATDCTL2: $80 (ADPU = 1, AFFC = 0)
94 CHAPTER 9. ANALOG-TO-DIGITAL (ATD) CONVERTER

based ATD system similar to the HC12. However, the S12 ATD has additional enhanced features. These
powerful enhanced features which include:
– Selectable 8 or 10 bit resolution,
– Left/right justified and signed/unsigned result data,
– External trigger control,
– Flexible 1 to 8 conversion sequence length configuration, and
– Multiple ATD Channels.
• Challenging
1. Write a subroutine that reads channel 1 of the ATD, calculates the average value of the last 8 data
points, and outputs the value to PORT B of the HC12.
Answer: The structure chart for this program is shown in Figure 9.5. We will use the “INIT” routine
from the text. We will modify the “CONVERT” subroutine and modify the control word sent to
“ATDCTL5” with the following values:
– S8CM = 1, 8 channel conversions
– SCAN = 0, single conversion
– MULT = 0, single channels
– CD,CC,CB,CA = “0001”, channel signal 1
– ATDCTL5 control word = $41
INCLUDE ’HC12REG.ASM’
;—————————————-
;MAIN PROGRAM ;
;—————————————-
ORG $7000 ;User RAM at $7000
FIFTEEN EQU $0F ;loop control constant

;MAIN
BSR INIT ;Branch to INIT for initialization
BSR CONVERT ;Branch to CONVERT for conversion
DONE BSA DONE ;Branch to self

;—————————————-
;Subroutine INIT: Initialize ATD ;
;—————————————-

INIT LDAA #$80 ;config word to turn on ADPU,

STAA ATDCTL2 ;flags clr normal, disable interrupts
BSR DELAY ;branch to subroutine DELAY
LDAA #$00 ;select continue conversions in
STAA ATDCTL3 ;active background mode
LDAA #$01 ;select final sample time = 2 ATD clocks,
STAA ATDCTL4 ;prescalar = 4 (PRS4:0 = 1)
RTS ;Return from subroutine
The code for subroutine delay is:
;—————————————-
;Subroutine DELAY: delays 100 uS ;
;—————————————-
DELAY LDAA #$C8 ;load accumulator with 100 uS delay
NOTYET DECA ;Decrement ACC
BNE NOTYET ;Branch if not equal to zero
RTS
 95

convert
main initialize
accumulator D

initialize
initialize
convert ATD
conversions
initiate
conversion sequence

conversion
complete?
yes
sum eight
conversions

divide sum
by eight

output result
to PORT B

RTS

Figure 9.5: Structure and flow chart for problem Challenging 1

96 CHAPTER 9. ANALOG-TO-DIGITAL (ATD) CONVERTER

;—————————————-
;Subroutine CONVERT ;
;—————————————-
;Set-up ATD, make 8 conversions on channel 1, average conversions
;send results to Port B

CONVERT LDD #$0000 ;initialize D register

LDAA #$41 ;ATD S8CM=1,SCAN=0,MULT=0,CD,CC,CB,CA=0001
;write clears flag
STAA ATDCTL5 ;8 conversions on single sequence
WTCONV BRCLR ATDSTAT2,#$40, WTCONV
;wait Seq Comp Flag
ADDD ADR0H ;sum 8 conversions
ADDD ADR1H ;
ADDD ADR2H ;
ADDD ADR3H ;
ADDD ADR4H ;
ADDD ADR5H ;
ADDD ADR6H ;
ADDD ADR7H ;
LSRD ;divide by 2
LSRD ;divide by 2
LSRD ;divide by 2
STAB PORTB ;only lower half of D
RTS

2. Repeat the question above for the S12 microcontroller. Choose an appropriate output port for data
output.
Answer: The code solution will be very similar. Change the register values to the following values:
– ATDCTL2: $80 (ADPU = 1, AFFC = 0)
– ATDCTL3: $44 (FIFO = 1, S8C:4C:2C:1C = 1000)
– ATDCTL4: $80 (SRES8 = 1)
– ATDCTL5: $21 (DIM = 0, DSGN = 0, SCAN = 1, MULT = 0, CC:CB:CA = 001)
3. Write a subroutine that continuously senses the voltage at PAD3. If the voltage is between 0 and 1 volt,
bit 0 on PORT B is set high. If the voltage is between 1 and 2 volts, bit 1 on PORT B is set high. If
the voltage is between 2 and 3 volts, bit 2 on PORT B is set high. If the voltage is between 3 and 4
volt, bit 3 on PORT B is set high. If the voltage is between 4 and 5 volts, bit 4 on PORT B is set high.
Answer: The structure chart for this problem is provided in Figure 9.6. The flow chart for subroutine
“CONVERT” is also provided. The subroutine will convert the voltage on PAD3 and then compare the
converted value in turn with the hexadecimal equivalent for 1V, 2V, 3V, and 4 Volts. The proper mask
is sent to Port B when the voltage level is determined. The voltage comparison values and the mask
values are also provided in the figure.

INCLUDE ’HC12REG.ASM’
;—————————————-
;MAIN PROGRAM ;
;—————————————-
ORG $7000 ;User RAM at $7000
VOLT1 EQU $33 ;1 volt comparison value
VOLT2 EQU $66 ;2 volt comparison value
VOLT3 EQU $99 ;3 volt comparison value