Zynq Small

Model 8-Channel A/D & D/A in a Rugged Small Form

UltraScale+ Form
6353 Factor Enclosure
RFSoC - Gen 3 Factor

Features
n Small form factor rugged enclosure
n Conduction-cooled
n Designed to the IP67 specification
for dust and water immersion
n Sealed military-grade circular
connectors
n Incorporates Xilinx® Zynq®
UltraScale+™ RFSoC
n 16 GB of DDR4 SDRAM
n On-board GPS receiver
n Optional dual 100 GigE UDP optical
interface
n Optional fan cooling for benchtop use
n Navigator® BSP for software development
n Navigator® FDK for custom IP development
n Free lifetime applications support

Applications

n High-bandwidth data streaming

n Waveform signal generator
n Multimode data acquisition system
n Communication receiver and transmitter
n Electronic Warfare transponder
n Analog I/O for digital recording and playback
n Remote monitoring
n Sensor interfaces

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 Model 6353

General Information Extendable IP Design

The Quartz® Model 6353 is a high-performance, For applications that require specialized functions,
small form factor system based on the Xilinx Zynq users can install their own custom IP for data pro-
UltraScale+ RFSoC. The RFSoC integrates eight cessing. The Pentek Navigator FPGA Design Kit
RF-class A/D and D/A converters into the Zynq’s (FDK) includes the board’s entire FPGA design as a
multiprocessor architecture, creating a mul- block diagram that can be edited in Xilinx’s
tichannel data conversion and processing solution Vivado® IP Integrator. In addition to the IP Integ-
on a single chip. rator block diagrams, all source code and complete
IP core documentation is included. Developers can
integrate their own IP along with the Pentek fact-
ory-installed functions or use the Navigator kit to
completely replace the Pentek IP with their own.

The Navigator Board Support Package (BSP), the

companion product to the Navigator FDK, provides
a complete C-callable library for control of the
6353’s hardware and IP. The Navigator FDK and
BSP libraries mirror each other where each IP func-
tion is controlled by a matching software function,
The Model 6353 delivers RFSoC performance in
simplifying the job of keeping IP and software
small footprint with a complete system in a rug-
development synchronized.
gedized enclosure ideal for deployment in harsh
environments. The Navigator BSP includes support for Xilinx's
PetaLinux running on the ARM Cortex-A53 pro-
cessors. When running under PetaLinux, the Nav-
igator BSP libraries enable complete control of the
6353 either from applications running locally or on
the ARMs, or using the Navigator API control and
Complementing the RFSoC’s on-chip resources are command from remote system computers.
the 6353’s sophisticated clocking section, a low-
noise front end for RF input and output, 16 GBytes
of DDR4, a gigabit serial optical interface capable
of supporting dual 100 GigE connections, an
optional GPS receiver, and general purpose I/O sig-
nal paths to the FPGA.

Architecture
The 6353 design places the RFSoC as the corner-
stone of the architecture. All control and data
paths are accessible by the RFSoC’s programmable
logic and processing system. A full suite of Pentek-
developed IP and software functions utilize this
architecture to provide data capture, processing
and waveform generating solutions for many of
the most common application requirements.

One Park Way n Upper Saddle River, NJ 07458 n (201) 818-5900 www.pentek.com
 Model 6353

6353 Block Diagram

FREQUENCY EMMC
SYNTHESIZER MEMORY

A/D Clocks
TIMING BUS
Reference Clk DDR4 POWER POWER
GENERATOR D/A Clocks POWER
CLOCK SDRAM POWER 12 V 12 V 24 V Circular
MANAGEMENT
MANAGEMENT 8 GB MANAGEMENT
MANAGEMENT SUPPLY Connector
SysRef

64
Gate / Trigger

RF In 1 BALUN SGMII 1 GigE Circular

GTR ENET PHY
Connector
RF In 2 BALUN
RF SIGNAL RS-232 RS-232
RF In 3 BALUN CHAIN DRIVER
RF In 2 Circular
RF In 4 BALUN
A/D INPUT JTAG Connector
through 7 USB 2.0
RF In 5 BALUN 1 -8
5 GHz ZYNQ PROCESSING
RF In 6 BALUN 14-BIT ULTRASCALE+ SYSTEM DDR4
RF In 7 BALUN A/D & DDC 64 SDRAM
RFSoC FPGA 8 GB
CHANNELS
RF In 8 BALUN 1-8
CONFIG
FLASH
RF Out 1 BALUN 10 GHz
14-BIT
RF Out 2 BALUN
D/A & DUC USB 2.0
RF Out 3 BALUN CHANNELS Circular
1-8 RS-485 Connector
D/A OUTPUT LVDS DRIVER
RF Out 4 BALUN
RF Out 2 12
1 -8 PROGRAMMABLE
RF Out 5 BALUN through 7 LOGIC GTY
X8
RF Out 6 BALUN
RF Out 7 BALUN Model 6003 QuartzXM eXpress Module
RF Out 8 BALUN

BATTERY Dual
Antenna In GPS JTAG POWER
BATTERY
MANAGEMENT
MANAGEMENT X8 25 Gb/sec OPTICAL 100 GigE Circular
VPX VBAT TRANSCEIVER
(Optional) Connector

Model 6353 Quartz

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 Model 6353

A/D Converter Stage Memory Resources

The 6353 accepts analog IF or RF inputs on eight The 6353 architecture supports 8 GBytes of DDR4
front panel coax connectors. These inputs are SDRAM memory accessible from the Programmable
transformer-coupling into the RF signal chain of Logic. User-installed IP, which, along with the pentek-
the RFSoC. Inside the RFSoC, the analog signals supplied DDR4 controller core within the FPGA can
are routed to eight 5 GSPS, 14-bit A/D converters. take advantage of the memory for custom applic-
Each converter has built-in digital downconverters ations. An additional 8 GBytes bank of DDR4 SDRAM
with programmable 1x, 2x, 3x, 4x, 5x, 6x, 8x, 10x, is available to the Processing System as program
12x, 16x, 20x, 24x, or 40x decimation and inde- memory and storage.
pendent tuning. The A/D digital outputs are
delivered into the Zynq’s programmable logic and 100 GigE Interface
processor system for signal processing, data cap-
ture or for routing to other resources. The Model 6353 supports eight 25 Gb/sec full
duplex optical lanes to a miniature rugged circular
In addition to the A/D’s built-in decimation, an connector. With the dual built-in 100 GigE UDP
additional stage of IP-based decimation provides interfaces or installation of a user provided serial
another 16x stage of data reduction, ideal for protocol, this optical interface enables a high-
applications that need to stream data from all speed gigabit data streaming path between the
eight A/Ds. box and data storage or processing subsystems.

D/A Converter Stage GPS

The RFSoC’s eight D/A converters accept base- A GPS receiver provides time and position inform-
band real or complex data streams from the ation to the FPGA and ARM processors. This inform-
FPGA’s programmable logic. Each 10 GSPS, 14-bit ation can be used for precise data tagging. The
D/A includes a digital upconverter with inde- GPS provides a 1 PPS and 10 MHz reference clock
pendent tuning and interpolations of 1x, 2x, 3x, to the FPGA.
4x, 5x, 6x, 8x, 10x, 12x, 16x, 20x, 24x, or 40x.
Each D/A output is transformer-coupled to a coax
connection located on the front panel.

Clocking and Synchronization

An on-board timing bus generator uses a pro-
grammable frequency synthesizer to generate the
sample clock and all required timing signals. The
on-board sample clock can also be locked to a ref-
erence clock received through a front panel coax
connector. A multifunction gate/trigger input is
also available on the front panel for external con-
trol of data acquisition and playback.

One Park Way n Upper Saddle River, NJ 07458 n (201) 818-5900 www.pentek.com
 Model 6353

Optimized IP
Xilinx has created an integrated processing solution in the RFSoC that is unprecedented. The key to unlocking
the potential of the RFSoC is efficient operation using optimized IP and application software. Pentek helps
streamline the process from development to deployed application by providing a full suite of built-in functions.
These address the data flow and basic processing needed for some of the most common applications.

Several example applications using the Pentek Model 6353 are described below. For each example, the
board’s included IP is all that is needed to demonstrate the application and may satisfy the full set of
requirements for any particular application. These applications can also be the starting point for adding
additional IP from the Pentek Navigator IP library or for adding custom IP.

Example Application 1 - High Bandwidth Data Streaming

The RFSoC's eight 5 GSPS A/Ds are capable of producing an aggregate data rate of 80 GB/sec when all
channels are enabled. While capturing this much raw data is not feasible, the A/Ds' built-in digital down con-
verters can reduce this data throughput in many applications to a rate reasonable for the data streaming
and storage components downstream in the system.

In some applications capturing the raw, full bandwidth data is crucial. The 6353’s dual 100 GigE UDP
engine provides a high bandwidth path for moving data off of the board (shown with blue arrows). Along
with the built-in data acquisition IP with the A/Ds running at 4 GSPS, the 6353 can stream two full band-
width A/D data streams over optical cable to a downstream storage or processing subsystem. Other con-
verter speeds and bandwidths are possible with user installed IP.

The 6353’s built-in IP functions also provide paths for capturing data in the DDR4 SDRAM memory for
retrieval by the ARM processing system or the FPGA programmable logic (shown with red arrows) and for
sending data over the ARM’s 1 GigE interface (shown in yellow arrows).

One Park Way n Upper Saddle River, NJ 07458 n (201) 818-5900 www.pentek.com
 Model 6353

Example Application 2 - Analog Loopback and Waveform Generator

The 6353’s IP supports multiple D/A signal source options. A simple loopback path allows samples received
by the A/Ds to be output through the D/As (shown with a red arrow) . A CW signal generator produces a
sine output with programmable frequency (shown with a yellow arrow). A chirp generator, ideal for radar
applications, outputs sweep signals with programmable frequency, ramp, phase offset, gain offset and
length (shown with a blue arrow). The generators also include flexible trigger options with both internal and
external triggering.

Designed for Harsh Environments

The Model 6353 delivers the signal and processing performance of the Quartz RFSoC family in a Small Form
Factor (SFF) rugged package. Optimized for SWaP (size, weight and power), the 6353 measures 3.53” H
5.65” W 9.57” D and weighs in at just under 8 pounds.

Designed for use in rugged environments, the 6353 is designed to the IP67 specification for dust and water
immersion. It’s internal ‘I-beam’ construction creates a chassis that is both extremely rugged and efficient
for moving heat out of the box, making it ideal for deployment in the harshest environments and well
matched to conduction-cooled installations. The 6353 can also be used with an optional fan plate for
desktop development.

One Park Way n Upper Saddle River, NJ 07458 n (201) 818-5900 www.pentek.com
 Model 6353

Navigator Design Suite

For applications that require specialized functions, the Navigator Design Suite allows customers to fully util-
ize the processing power of the FPGA. It includes an FPGA design kit for integrating custom IP into Pentek's
factory-shipped design, and a board support package for creating host applications for control of all hard-
ware and FPGA IP-based functions.

The Navigator FPGA Design Kit (FDK) for the Xilinx® Vivado® Design Suite includes the complete Vivado
project folder for each Pentek product with all design files for the factory-installed FPGA IP. Vivado’s IP
Integrator is a graphical design entry tool that visually presents the complete block diagram of all IP blocks
so the developer can access every component of the Pentek design. Developers can quickly import, delete,
and modify IP blocks and change interconnection paths using simple mouse operations. Navigator FDK
includes Pentek’s IP core library of more than 100 functions representing a wealth of resources for DSP,
data formatting, timing, and streaming operations, all based on the powerful AXI4 standard. Multilevel doc-
umentation for each IP core is a mouse click away, and fully consistent with Xilinx IP cores.

Navigator IP FPGA Design Viewed in IP Integrator

One Park Way n Upper Saddle River, NJ 07458 n (201) 818-5900 www.pentek.com
 Model 6353

The Navigator Board Support Package (BSP) provides software support for Pentek boards. It enables
operational control of all hardware functions on the board and IP functions in the FPGA.

The BSP’s structure is designed to complement the functions of the FDK by maintaining a one-to-one rela-
tionship between FDK and BSP components. For each IP block found in the FDK library, a matching soft-
ware module can be found in the BSP. This organization simplifies the creation and editing of software to
support new IP functions and modifications to existing IP cores.

Because all Pentek boards are shipped with a full suite of built-in IP functions and numerous software
examples, new applications can be developed by building on the provided software examples or built
entirely new with the BSP’s extensive libraries. All BSP libraries are provided as C-language source for full
access and code transparency.

One Park Way n Upper Saddle River, NJ 07458 n (201) 818-5900 www.pentek.com
 Model 6353

The Navigator BSP includes the Signal Viewer, a full-featured analysis tool, that displays data in time and
frequency domains. Built-in measurement functions display 2nd and 3rd harmonics, THD (total harmonic
distortion), and SINAD (signal to noise and distortion). Interactive cursors allow users to mark data points
and instantly calculate amplitude and frequency of displayed signals. With the Signal Viewer users can
install the Pentek hardware and Navigator BSP and start viewing analog signals immediately.

One Park Way n Upper Saddle River, NJ 07458 n (201) 818-5900 www.pentek.com
 Model 6353

Connections

The front panel of Model 6353 has the following connectors:

n Eight SMA connectors labeled IN 1-8, which provide A/D input to the A/D converters on the 6353.
n Eight SMA connectors labeled OUT 1-8, which provide D/A output from the D/A converters on the 6353.

The rear panel of Model 6353 has the following connectors:

n GATE: Provides a trigger input. This trigger input is DC-coupled and compatible with the LVTTL levels,
but is 5V tolerant.
n REF: Provides an input for an external 10 MHz reference. This signal can be used to lock the on-board
sample clock synthesizer to an external reference.
n USB 2.0 / RS485: Interfaces to the RFSoC processor's USB 2.0 Port 0.
n 1000 BASE-T: Provides an Ethernet connection to the 6353 at 1000 Base-T mode.
n JTAG / RS-232: Used to download to the FPGA and program QSPI configuration memory.
n 24V DC IN: Provides power to the 6353.
n 2 x 100GbE: Provides an optical connector for the 6353.
n GPS: For input of an antenna RF signal for the onboard GPS receiver.

One Park Way n Upper Saddle River, NJ 07458 n (201) 818-5900 www.pentek.com
 Model 6353

Specifications Gate/Trigger
Source: Programmable through software or
Field Programmable Gate Array external connector
Type: (standard) Xilinx Zynq UltraScale+ RFSoC External Source Location: Rear Panel (GATE)
XCZU47DR Connector Type: SMA
Option -048: Xilinx Zynq UltraScale+ RFSoC Level: TTL
XCZU48DR GPS
Speed: (standard) -1 speed grade
Source: On-board
Option -002: -2 speed grade
Antenna Connector Location: Rear panel (GPS)
RFSoC RF Signal Chain Connector Type: SMA
Analog Inputs RFSoC Processing System
Quantity: 8
ARM Cortex-A53:
Location: Front panel (IN 1-8)
Quantity: 4
Connector Type: SMA
Speed: 1.5 GHz
Input Type: Transformer-coupled
ARM Cortex-R5:
Transformer Type: Mini-Circuits TCM1-83X+
Quantity: 2
Full Scale Input: +8 dBm into 50 ohms
A/D Converters Speed: 600 MHz
Processor I/O:
Quantity: 8
Interfaces: USB 2.0 and RS-485
Sampling Rate: 5.0 GHz
Location: Rear panel (USB2.0/RS485)
Resolution: 14 bits
Digital Downconverters Connector Type: Circular, Glenair Mighty Mouse
Quantity: 1 per A/D Series
Decimation Range: 1x, 2x, 3x, 4x, 5x, 6x, 8x, Interface: 1 GigE
Location: Rear Panel (1000BASE-T)
10x, 12x, 16x, 20x, 24x, and 40x (not all decim-
Connector Type: Circular, Glenair Mighty Mouse
ations are supported by default IP)
LO Tuning Freq. Resolution: 48 bits, 0 to ƒs
Series
Interface: RS-232
Filter: 80% pass band, 89 dB stop-band
Location: Rear Panel (JTAG/RS-232)
attenuation
Connector Type: Circular, Glenair Mighty Mouse
Analog Outputs
Series
Quantity: 8
Location: Front panel (OUT 1-8) FPGA I/O
Connector Type: SMA Optical (Option -110): 8X full duplex optical lanes @
Output Type: Transformer-coupled 25 Gb/sec
Transformer Type: Mini-Circuits TCM1-83X+ Location: Rear panel (2x 100GbE)
Full Scale Output: 0 dBm into 50 ohms Connector Type: circular, Glenair SuperNine Series
D/A Converters Protocol: Factory-installed dual 100 GigE UDP IP
Quantity: 8
cores provides greater than 24 GB/sec data transfers,
Sampling Rate: 10 GHz
other protocols supported with user-installed IP
Resolution: 14 bits
Digital Upconverters JTAG
Quantity: 1 per D/A Location: Rear Panel (JTAG/RS-232)
Interpolation Range: 1x, 2x, 3x, 4x, 5x, 6x, 8x, Connector Type: Circular, Glenair Mighty Mouse Series
10x, 12x, 16x, 20x, 24x, and 40x (not all
interpolations are supported by default IP) Memory
LO Tuning Freq. Resolution: 48 bits Processing System:
Filter: 80% pass band, 89 dB stop-band Type: DDR4 SDRAM
attenuation Size: (standard) 8 GB
Sample Clock Speed: 1200 MHz (2400 MHz DDR)
Source: On-board programmable clock Type: eMMC
Reference Clock Size: 64 GB
Source: On-board oscillator, on-board GPS, or Programmable Logic:
external source Type: DDR4 SDRAM
External Source Location: Rear panel (REF) Size: (standard) 8 GB
Connector Type: SMA Speed: 1200 MHz (2400 MHz DDR)
Level: -10 dBm to +24 dBm FPGA Configuration FLASH (QSPI NOR Flash):
Type: QSPI NOR Flash
Size: 2x 1 Gb

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 Model 6353

Environmental Lifetime Applications Support

Option -703: Level L3 (conduction-cooled)
Operating Temp: –20° to 60° C (with 50° C cold plate) Pentek offers the worldwide military embedded com-
Storage Temp: –50° to 100° C puting community shorter development time, reli-
Relative Humidity: 0 to 100% able, rugged solutions for a variety of environments,
Physical reduced costs, and mature software development
Dimensions:
tools. We offer free lifetime support from our engin-
Depth: 243.08 mm (9.57 in) eering staff, which customers can depend on
Height: 89.66 mm (3.53 in) through phone and email, as well as software
Width: 143.51 mm (5.65 in) updates. Take advantage of Pentek's 30 years of
Weight: 8 lbs. experience in delivering high-performance radar,
Power: communications, SIGINT, EW, and data acquisition
Voltage: +12 to +28 VDC (+24 VDC nominal)
MIL-Aero solutions worldwide.
Location: Rear Panel (24VDC IN)
Connector Type: Circular, Glenair Mighty Mouse Series
Maximum Power Consumption: 46.62 Watts

Ordering Information
Model Description

6353 8-Channel A/D & D/A Zynq UltraScale+ RFSoC Gen 3

Processor in a Rugged Small Form Factor Enclosure

Options Description

-002 -2 FPGA speed grade, -1 standard

-048 XCZU48DR FPGA (XCZU47DR is standard)
-110 Optical interface
-703 Conduction-cooled, L3
Contact Pentek for compatible option combinations and complete spe-
cifications of rugged and conduction-cooled versions. Options may change, so
be sure to contact Pentek for the latest information.

Accessory Products
Model Description

2187 6353 Accessories

Options Description

-150 Development cable set without optical cable

-151 Development cable set with optical cable
-701 Top cover plate with built-in fan, replaces standard top
plate for benchtop cooling

Pricing and Availability

To learn more about our products or to discuss
your specific application please contact your local
representative or Pentek directly:

Pentek, Inc.
One Park Way
Upper Saddle River, NJ 07458 USA
Tel: +1 (201) 818-5900
Email: [email protected]

One Park Way n Upper Saddle River, NJ 07458 n (201) 818-5900 www.pentek.com