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There Are 4 Packets

1) There are 4 packets with numbers 19, 31, 8, 5; 2, 20, 17, 4; 28, 18, 22, 3; 14, 1. 2) A 2-bit predictor is 79% accurate, incorrectly predicting at indexes 1 and multiples of 5. 3) The document discusses different techniques for improving processor performance including pipelining, super scalar execution, and out-of-order execution.
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0% found this document useful (0 votes)
11 views3 pages

There Are 4 Packets

1) There are 4 packets with numbers 19, 31, 8, 5; 2, 20, 17, 4; 28, 18, 22, 3; 14, 1. 2) A 2-bit predictor is 79% accurate, incorrectly predicting at indexes 1 and multiples of 5. 3) The document discusses different techniques for improving processor performance including pipelining, super scalar execution, and out-of-order execution.
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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1) There are 4 packets

19 , 31 , 8 , 5
2 , 20 , 17 , 4
28 , 18 , 22 , 3
14 , 1

2) The 2bit predictor predicts the wrong outcome at i =1 and multiples of 5


This shows that the accuracy is 1 – 21/100 which is 79% accuracy

For a 2 level branch predictor

I= Predictor in prediction Outcome New state


use
1 00 T NT WNT
2 10 T NT WNT
3 01 T NT WNT
4 10 NT NT SNT
5 00 NT T WT
6 11 T NT WNT
7 00 T NT WNT
8 10 NT NT SNT
9 01 NT NT SNT
10 10 NT T WNT
11 00 NT NT SNT
12 11 NT NT SNT
13 00 NT NT SNT
14 10 NT NT SNT
15 01 NT T WNT
16 10 NT NT SNT
17 00 NT NT SNT
18 11 NT NT SNT
19 00 NT NT SNT
20 10 NT T WNT
21 01 NT NT SNT
22 10 NT NT SNT
23 00 NT NT SNT
24 11 NT NT SNT
25 00 NT T WNT
26 10 NT NT SNT
27 01 NT NT SNT
28 10 NT NT SNT
29 00 NT NT SNT
30 11 NT T WNT

00 , 01 , 10 predictors give final out come as 00


11 predictor has final out come 01

So the accuracy = 1- 25/100 = 0.75

3) 11=(p*c)+(q*b)+(r*a) 12=(p*i)+(q*h)+(r*g) 13=(p*l)+(q*k)+(r*j)


21=(f*c)+(e*b)+(d*a) 22=(f*i)+(e*h)+(d*g) 23=(f*l)+(e*k)+(d*j)
31=(y*c)+(x*b)+(z*a) 32=(y*i)+(x*h)+(z*g) 33=(y*l)+(x*k)+(z*j)

4) x7= 0x DEBCDEFFBFBFFF78

5) 1) simple pipelining
Clock 1 2 3 4 5 6 7
cycle
fetch add mul div sub sd

Decode add mul div sub sd

execute add mul div sub sd

2)super scalar execution


Clock 1 2 3 4 5 6
cycle
fetch add mul div sub
sd
Decode add mul div sub
sd
execute add mul div sub
sd

3) out of order execution


Clock 1 2 3 4 5 6
cycle
fetch add mul div sub
sd
Decode add mul div sub
sd
execute add mul div sub
sd

6) E A B C
D 6 7 F

1110 1010 1011 1100


1101 0110 0111 1111

1100 0000 0011 1011


C 0 3 B

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