Phase 3: Finite Impulse Response Filter

Introduction
The specifications for this phase include the use of paramatizable d-flip flops which have an asynchronous clear and paramatizable ripple carry
adders in conjunction with multipliers to construct the overall structure of the fir filter. The block diagram of the filter was assembled by using the
above components and a list of coefficients were extracted to be used with the filter from a filter code provided in the matlab format.

What is expected?

To explain what an fir filter does; it can be simply be put as that a finite impulse response filter is a type of a signal processing filter whose
impulse response (or response to any finite length input) is of finite duration, and therefore it is expected that in a finite time the impulse response
should die to zero.

N-bit D-flip flop

The dynamic N bit flip flop was one of the elements being used to construct the filter in this phase, the way it works is that, whatever is forced in
the input of the flip flop comes out only on the rising edge of the clock. An asynchronous clear was used to control the activity of the flip-flop, so
the output gets cleared when the clear is forced to zero otherwise it carries its normal function as mentioned above.
N-Bit D-flip flop code

Figure 1: N bit dff code.

Test Bench

Figure 2: Testbench for paramatizable d-flip flop.

Tester Code
A tester was created to test the flip flop. Sensible values were used to carry out the testing; the simulations below reveal that the output follows
the input at every rising edge of the clock and when the asynchronous clear is true the output goes to zero.

Figure3: tester code for the paramatizable d-flip flop.

Model Sim

Figure4: Model simulation for the paramatizable d-flipflop.

Ripple Adder
Ripple Adder Code

Figure 5: Ripple carry adder code.

Rtl Schematics

Figure6: Rtl schematics of the Ripple Carry Adder.

Model Sim
These are some simulations taken to check the adder, the diagrams below show the results in both decimal and binary.

Figure7: Model simulation for the ripple carry adder in binary and decimal.
Phase3
The figures below show the zoomed in/out versions of the fir filter block diagram on graphical view in VHDL. It consists of 30 d-fliop flops
cascaded In parallel with branches connectiong to the multipliers which have furthur branches connecting to the adders.

Figure8: Block diagram of the fir filter.

Figure 9 shows a zoomed in region of the block diagram of the fir filter; before the signal is passed to the filter output it gets truncated by 5 bits as the signal sumout21
going in is 25 bits long and the one coming out is 19 bits long(24 downto 5). This means that the last 5 bits of the output signal get omitted before it comes out at the filter
output, this can also be seen in the model simulation of the filter .

Figure 9: Block diagram of the filter output and modelsimulation showing the output signal getting truncated.
Coefficient bank
A coefficient bank was constructed to store the 31 coefficient values that were obtained from matlab. Figure 10 shows the coefficient bank and the values each coefficient
holds in binary and decimal respectively.
Test bench
An extra output port from the sumout21 was made in the fir filter so that it enabled the user to see what they get before the signal gets truncated when using the test
bench.
Tester Code (impulse response)
Model Sim(Impulse Response)

Radix fixpoint was set to 9 to see the actual coefficients at the sumout21. This was done to change the binray point representation of the coefficients to include the floating
point numbers.

Simulations showing the truncated coefficients and actual coefficients coming out of the filter, and shows tat the input ultimately dies to zero after a finite number of
clocks.

As you can see in the figures above the sumout21 shows the actual coefficients coming out of the filter which then get truncated by 5 bits from the LSB therefore the
output at the filter_output shows a binary value of 19 bits.
Heres a comparision between the expected coefficients that were extracted from matlab, and the actual coefficients values achieved from vhdl simulations. Its evident that
the two values are very close to each other .

Matlab Coefficients (expected) Model Sim Values(actual)

0.0020 0.00195313
0.0020 0.00195313
0 0
-0.0020 -0.00195313
-0.0039 -0.00390625
-0.0098 -0.00976563
-0.0137 -0.0136719
-0.0156 -0.015625
-0.0098 -0.00976563
0.0039 0.00390625
0.0293 0.0292969
0.0605 0.0605469
0.0957 0.0957031
0.1289 0.128906
0.1504 0.150391
0.1602 0.160156
0.1504 0.150391
0.1289 0.128906
0.0957 0.0957031
0.0605 0.0605469
0.0293 0.0292969
0.0039 0.00390625
-0.0098 -0.00976563
-0.0156 -0.015625
-0.0137 -0.0136719
-0.0098 -0.00976563
-0.0039 -0.00390625
0.0020 -0.00195313
0 0
0.0020 0.00195313
0.0020 0.00195313
Tester code (Unit Step)
Model Sim (Unit Step)
Another comparison was made for the unit step response. It can be seen that the values of the coefficients add with each other on every clock until all the coefficients have
been added together; on the left hand side of the table are the expected values that should be seen when testing with a unit step and on the right hand side are the actual
values.

Matlab Coefficients (expected) Model Sim Values(actual)

0.0020 0.00195313
0.0040 0.00390625
0.0040 0.00390625
0.0020 0.00195313
-0.0019 -0.00195313
-0.0117 -0.0117188
-0.0254 -0.0253906
-0.041 -0.0410156
-0.0508 -0.0507813
-0.0469 -0.046875
-0.0176 -0.0175781
0.0429 0.0429688
0.1386 0.138672
0.2675 0.267578
0.4179 0.417969
0.5781 0.578125
0.7285 0.728516
0.8574 0.857422
0.9531 0.953125
1.0136 1.01367
1.0429 1.04297
1.0468 1.04688
1.037 1.03711
1.0214 1.02148
1.0077 1.00781
0.9979 0.998047
0.994 0.994141
0.996 0.992188
0.996 0.992188
0.998 0.994141
1 0.996094
It can be seen from the figure above that when -512 is forced into Din_h, because the asynchronous clear was set to true everything else besides the very first multiplier
were passing a zero down towards the output, and also because the very first coefficient has a value of one therefore -512 x 1 allowed-512 to pass all the way to the
sumout of the filter. Since the filter output is truncated by 5 bits (24 downto 5) the first five bits from the LSB get discarded hence giving our -16 at the filter output.