COMPUTER ARCHITECTURE AND

ORGANIZATION I
CSC 3305
Usman Alhaji Abdurrahman
 Introduction
• As we know that computers have now become a part of our
routine life.
• The smart work that it performs with a given instruction is
worth exploring.
• It may be a question in our mind as we keep ourselves
thinking that what kind of process is going on in a computer
when any instruction is given.
• What happens inside it?
 Introduction
• Computer Architecture is concerned with the structure and
behaviour of the various functional modules of the computer
and how they interact to provide the processing needs of the
user.
• The discipline of Computer Architecture has three main
subcategories:
– Instruction Set Architecture (ISA): The ISA defines the codes that a
central processor reads and acts upon. It is the machine language,
including the instruction set, word size, memory address modes,
processor registers and address and data formats.
 Introduction
– Microarchitecture (Computer Organization): This describes the data
paths, data processing elements and data storage elements, and
describes how they should implement the ISA.
– System Design: This includes all of the other hardware components
within a computing system, which includes;
• Data paths, such as computer buses and switches
• Memory controllers and hierarchies
• Data processing other than the CPU, such as direct memory access
(DMA)
• Miscellaneous issues such as virtualization, multiprocessing and
software features.
 Introduction
Why study Computer Architecture and Organization?
• The IEEE/ACM Computer Curricula 2001 lists Computer
Architecture as one of the core subjects that should be in the
curriculum of all students in Computer Science and Computer
Engineering.
• The computer lies at the heart of computing. Without it most
of the computing disciplines today would be a branch of
theoretical mathematics.
• To be a professional in any field of computing today, one
should not regard the computer as just a black box that
executes programs by magic.
 Introduction
• All students of computing should acquire some understanding
and appreciation of a computer system’s functional
components, their characteristics, their performance, and
their interactions.
• Students need to understand computer architecture in order
to structure a program so that it runs more efficiently on a
real machine.
• In selecting a system to use, they should be able to
understand the trade-off among various components, such as
CPU clock speed Vs. memory size.
 Course Outline
• Fundamental Building Blocks, Logic Expressive Immunization,
Sum of Product Forms;
• Register Transfer Notation, Physical Considerations;
• Data Representation and Number Bases, Fixed and Floating
Point Systems, Representation of Memory Systems
Organization and Architecture.
 Number Systems

• The binary number system is the most important one in digital

systems, but several others are also important.
• The decimal system is important because it is universally used
to represent quantities outside a digital system.
• This means that there will be situations where decimal values
must be converted to binary values before they are entered
into the digital system.
• Likewise, there will be situations where the binary values at
the outputs of a digital system must be converted to decimal
values for presentation to the outside world.
 Number Systems

• As you will see, it is not easy to simply look at a large binary

number and convert it to its equivalent decimal value.
• It is very tedious to enter a long sequence of 1s and 0s on a
keypad, or to write large binary numbers on a piece of paper.
• It is especially difficult to try to convey a binary quantity while
speaking to someone.
• The hexadecimal (base-16) number system has become a very
standard way of communicating numeric values in digital
systems.
• The great advantage is that hexadecimal numbers can be
converted easily to and from binary.
 Number Systems

• Other methods of representing decimal quantities with

binary-encoded digits have been devised that are not truly
number systems but offer the ease of conversion between the
binary code and the decimal number system.
• Other codes that use 1s and 0s to represent things such as
alphanumeric characters will be covered because they are so
common in digital systems.
 Decimal System
• The decimal system is composed of 10 numerals or symbols.
• These 10 symbols are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9; using these
symbols as digits of a number, we can express any quantity.
• The decimal system, also called the base-10 system because it
has 10 digits, has evolved naturally as a result of the fact that
people have 10 fingers.
• In fact, the word digit is derived from the Latin word for
“finger.”
 Decimal System
• The decimal system is a positional-value system in which the
value of a digit depends on its position.
• For example, consider the decimal number 453. We know that
the digit 4 actually represents 4 hundreds, the 5 represents 5
tens, and the 3 represents 3 units.
• In essence, the 4 carries the most weight of the three digits; it
is referred to as the most significant digit (MSD). The 3 carries
the least weight and is called the least significant digit (LSD).
 Decimal System
• This is illustrated in Figure 1, where the number 2745.214 is
represented. The decimal point separates the positive powers
of 10 from the negative powers.
• The number 2745.214 is thus equal to

(2 103 )  (7 102 )  (4 101 )  (5 100 )  (2 101 )  (1102 )  (4 103 )

 Binary System

• Unfortunately, the decimal number system does not lend

itself to convenient implementation in digital systems.
• For example, it is very difficult to design electronic equipment
so that it can work with 10 different voltage levels (each one
representing one decimal character, 0 through 9).
• On the other hand, it is very easy to design simple, accurate
electronic circuits that operate with only two voltage levels.
• For this reason, almost every digital system uses the binary
(base-2) number system as the basic number system of its
operations.
 Binary System

• In the binary system there are only two symbols or possible

digit values, 0 and 1.
• Even so, this base-2 system can be used to represent any
quantity that can be represented in decimal or other number
systems.
• The binary system is also a positional value system, wherein
each binary digit has its own value or weight expressed as a
power of 2.
• The number 1011.101 is shown represented in the figure.
 Binary System

• To find its equivalent in the decimal system, we simply take

the sum of the products of each digit value (0 or 1) and its
positional value:
 Binary-to-Decimal Conversions
• As explained above, the binary number system is a positional
system where each binary digit (bit) carries a certain weight
based on its position relative to the LSB.
• Any binary number can be converted to its decimal equivalent
simply by summing together the weights of the various
positions in the binary number that contain a 1.
• To illustrate, let’s change 11011 to its decimal equivalent.
 Binary-to-Decimal Conversions
• Let’s try another example with a greater number of bits:
 Decimal-to-Binary Conversions

• There are two ways to convert a decimal whole number to its

equivalent binary-system representation.
• The first method is the reverse of the process described
above.
• The decimal number is simply expressed as a sum of powers
of 2, and then 1s and 0s are written in the appropriate bit
positions.
• To illustrate:
 Decimal-to-Binary Conversions

• Another example is the following:

 Decimal-to-Binary Conversions

• Another method for converting decimal integers uses

repeated division by 2.
• The conversion, illustrated below for , requires repeatedly
dividing the decimal number by 2 and writing down the
remainder after each division until a quotient of 0 is obtained.
• Note that the binary result is obtained by writing the first
remainder as the LSB and the last remainder as the MSB.
Decimal-to-Binary Conversions
 Octal Number System
• It has a base of 8 which means that it has eight distinct
counting digits:
• 0,1,2,3,4,5,6 and 7
• These digits 0 through 7, have exactly the same physical
meaning as in decimal system.
• For counting beyond 7, 2-digit combinations are formed
taking the second digit followed by the first, then the second
followed by the second and so on.
• Hence, after 7, the next octal number is 10 (second digit
followed by first), then 11 (second digit followed by second)
and so on.
 Octal Number System
• Hence, the octal numbers are:
• 0, 1, 2, 3, 4, 5, 6, 7,
• 10, 11, 12, 13, 14, 15, 16, 17,
• 20, 21, 22, 23, 24, 25, 26, 27,
• 30, 31, 32, 33, 34, 35, 36, 37,
• ……
• The position value (or weight) for each digit is given by different
powers of 8 as shown below:
83 82 81 80 . 8-1 8-2 8-3

↑
Octal point
 Octal to Decimal Conversion

Example 1: Convert 3528 to decimal

Solution:
3 5 2
82 81 80
64 8 1 =

OR
 Octal to Decimal Conversion

Example 2: Convert 127.248 to decimal

Solution:
 Octal to Decimal Conversion

Example 3: Convert 206.1048 to decimal

Solution:
2 0 6 . 1 0 4
82 81 80 8-1 8-2 8-3
 Decimal to Octal Conversion
In this method, 8 is used as the multiplying factor for the
integers and the dividing factor for fraction.
Example 1: Convert 17510 into its octal equivalent
Solution:
with remainder of 7
with remainder of 5
with remainder of 2
 Decimal to Octal Conversion
Example 2: Convert 0.1510 to its octal equivalent
Solution:

with a carry of 1
with a carry of 1
with a carry of 4

As seen, here carries have been taken forward direction i.e. from
top to bottom.
 Binary to Octal Conversion
• In this method, the given binary number is arranged into
groups of 3 bits (called binary triplet) starting from the octal
point and then each group is converted to its equivalent octal
number.
• At the same time, extra 0s can be added in the left end of the
binary number (where necessary) to complete groups of
three.
 Binary to Octal Conversion
Example 1: Convert 1010112 into its octal equivalent
Solution: Converting the bits into groups of three, we have
Now, 1012 is 58 and 0112 is 38
Thus,

Example 2: Convert 1111101112 to Octal

Solution: Split the number into groups of three bits. Then each
group is given its octal number as shown below:
1112 is 78, 1102 is 68 and 1112 is 78
Thus,
 Octal to Binary Conversion
In this kind of conversion, each digit of the given octal number is
converted to its equivalent binary triplet
Example 1: Convert 758 to binary
Solution: Here, 78 is 1112 and 58 is 1012
Thus,
 Octal to Binary Conversion
Example 2: Convert 74,5628 to binary
Solution:
7 4 5 6 2
↓ ↓ ↓ ↓ ↓
111 100 101 110 010

Thus,

Note: The number of digits in octal numbers is one-third of that

in equivalent binary numbers.
 Hexadecimal Number System

• The hexadecimal number system uses base 16.

• Thus, it has 16 possible digit symbols.
• It uses the digits 0 through 9 plus the letters A, B, C, D, E, and
F as the 16 digit symbols.
• The digit positions are weighted as powers of 16 as shown in
Fig. 6.3, rather than as powers of 10 as in the decimal system.

164 163 162 161 160 ● 16-1 16-2 16-3

Hexadecimal Point
 Hexadecimal Number System

• Table 1 shows the relationships among hexadecimal, decimal,

and binary.
• Note that each hexadecimal digit represents a group of four
binary digits. It is important to remember that hex
(abbreviation for “hexadecimal”) digits A through F are
equivalent to the decimal values 10 through 15.
Hexadecimal Number System
TABLE 1
 Hex-to-Decimal Conversion
• A hex number can be converted to its decimal equivalent by
using the fact that each hex digit position has a weight that is
a power of 16.
• The LSD has a weight of the next higher digit position
has a weight of the next has a weight of and
so on.
• The conversion process is demonstrated in the examples
below.
 Hex-to-Decimal Conversion
Example 1: Convert 35616 to decimal
Solution:

Example 2: Convert 2AF16 to decimal

Solution:

Note: In the second example, the value 10 was substituted for A

and the value 15 for F in the conversion to decimal.
 Decimal-to-Hex Conversion

• Recall that we treated decimal-to-binary conversion using

repeated division by 2.
• Likewise, decimal-to-hex conversion can be done using
repeated division by 16.
• The following example contains two illustrations of this
conversion.
 Decimal-to-Hex Conversion

Example 1: Convert 42310 to hex

Solution:
• + remainder of 7

• + remainder of 10

• + remainder of 1
 Decimal-to-Hex Conversion

Example 2: Convert 21410 to hex

Solution:
• + remainder of 6

• + remainder of 13

Note: The remainders of the division processes form the digits of

the hex number. Also note that any remainders that are greater
than 9 are represented by the letters A through F.
 Hex-to-Binary Conversion

• The hexadecimal number system is used primarily as a

“shorthand” method for representing binary numbers.
• It is a relatively simple matter to convert a hex number to
binary.
• Each hex digit is converted to its four-bit binary equivalent (as
shown in Table 1).
Example 1: Convert 9F216 to binary
Solution:
9F216 = 9 F 2
↓ ↓ ↓
= 1001 1111 0010
Thus, 9F216 = 1001111100102
 Binary to Hex Conversion

• Conversion from binary to hex is just the reverse of the

process above.
• The binary number is grouped into groups of four bits, and
each group is converted to its equivalent hex digit.
• Zeros (shown shaded) are added, as needed, to complete a
four-bit group.
Example 1: Convert 11101001102 to Hex
Solution:
 BCD Code

• When numbers, letters, or words are represented by a special

group of symbols, we say that they are being encoded, and
the group of symbols is called a code.
• Probably one of the most familiar codes is the Morse code,
where a series of dots and dashes represents letters of the
alphabet.
• We have seen that any decimal number can be represented
by an equivalent binary number. The group of 0s and 1s in the
binary number can be thought of as a code representing the
decimal number.
• When a decimal number is represented by its equivalent
binary number, we call it straight binary coding.
 Binary-Coded-Decimal Code

• If each digit of a decimal number is represented by its binary

equivalent, the result is a code called binary-coded-decimal
(hereafter abbreviated BCD).
• Since a decimal digit can be as large as 9, four bits are
required to code each digit (the binary code for 9 is 1001).
• To illustrate the BCD code, take a decimal number such as
874. Each digit is changed to its binary equivalent as follows:
 Binary-Coded-Decimal Code

• As another example, let us change 943 to its BCD-code

representation:
• Once again, each decimal digit is changed to its straight binary
equivalent.
• Note that four bits are always used for each digit.
 Binary-Coded-Decimal Code

• The BCD code, then, represents each digit of the decimal

number by a four-bit binary number.
• Clearly only the four-bit binary numbers from 0000 through
1001 are used.
• The BCD code does not use the numbers 1010, 1011, 1100,
1101, 1110, and 1111.
• In other words, only 10 of the 16 possible four-bit binary code
groups are used.
• If any of the “forbidden” four-bit numbers ever occurs in a
machine using the BCD code, it is usually an indication that an
error has occurred.
 Binary-Coded-Decimal Code

• Example: Convert 0110100000111001 (BCD) to its decimal

equivalent.
• Solution
Divide the BCD number into four-bit groups and convert each to
decimal.
 Binary-Coded-Decimal Code

• Example: Convert the BCD number 011111000001 to its

decimal equivalent.
• Solution
 ASCII Code

• The most widely used alphanumeric code is the American

Standard Code for Information Interchange (ASCII).
• The ASCII (pronounced “askee”) code is a seven-bit code, and
so it has possible code groups.
• This is more than enough to represent all of the standard
keyboard characters as well as the control functions such as
the (RETURN) and (LINEFEED) functions.
• Table 2 shows a listing of the standard seven-bit ASCII code.
ASCII Code
 ASCII Code

• The ASCII code is used for the transfer of alphanumeric

information between a computer and the external devices
such as a printer or another computer.
• A computer also uses ASCII internally to store the information
that an operator types in at the computer’s keyboard.
 ASCII Code

• Example: Use Table 2 to find the seven-bit ASCII code for the
backslash character (\).
• Solution: The hex value given in Table 2 is 5C, translating each
hex digit into four-bit binary produces 0101 1100. The lower
seven bits represent the ASCII code for \, is 1011100.
 ASCII Code

• Example: An operator is typing in a C language program at the

keyboard of a certain microcomputer. The computer converts
each keystroke into its ASCII code and stores the code as a
byte in memory. Determine the binary strings that will be
entered into memory when the operator types in the
following C statement: if (x >3)
 ASCII Code

• Solution: Locate each character (including the space) in Table

2 and record its ASCII code.

• Note that a 0 was added to the leftmost bit of each ASCII code
because the codes must be stored as bytes (eight bits). This
adding of an extra bit is called padding with 0s.
 Binary operations

We shall now consider the following four binary

operations:
• Addition
• Subtraction
• Multiplication
• Division
 Binary Addition
Addition of binary numbers is similar to the
decimal addition. The following points will help
in understanding the rules of binary addition:
–0+0=0
–0+1=1
–1+0=1
– 1 + 1 = 0 with a carry of 1 or = 102
 Binary Subtraction

• It is also performed in a manner similar to that used in

decimal subtraction.
• Because binary system has only two digits, binary subtraction
requires more borrowing operations than decimal
subtraction.
• The four rules for binary subtraction are as under:
 Binary Subtraction
1. 0  0  0

2. 1  0  1

3. 1 1  0

4. 0 1  1 with a borrow of 1 from the next column of the minuend or

10  1  1.
 Binary Subtraction

Example 1: Subtract 01012 from 11102

Solution:
 Complement of a number

• In digital work, two types of complements of a binary number

are used for complemental subtraction:
1’s complement
• The 1’s complement of a binary number is obtained by
changing its each 0 into a 1 and each 1 into a 0.

Example: Find the 1’s complement of 1002 and 11102

Solution: The 1’s complement of 1002 is 0112 and of 11102 is
00012.
 Complement of a number

2’s complement
• The 2’s complement of a binary number is obtained by adding
1 to its 1’s complement.
2’s complement = 1’s complement + 1

Example 1: Find the 2’s complement of 10112.

Solution: Its 1’s complement is 01002. Next, add 1 to get 01012.
Hence 2’s complement of 10112 is 01012.
 Complement of a number

• The complement method of subtraction reduces subtraction

to an addition process.
• This method is popular in digital computers because
– Only adder circuits are needed thus simplifying the circuitry.
– It is easy with digital circuits to get the complements.
 1’s Complement Subtraction

• In this method, instead of subtracting a number, we add its 1’s

complement to the minuend.
• The last carry (0 or 1) is then added to get the final answer.
• The steps for subtraction by 1’s complement are listed below:
– Compute the 1’s complement of the subtrahend by changing all its 1s
to 0s and all its 0s to 1s.
– Add this complement to the minuend.
– Perform the end-around carry of the last 1 or 0.
– If there is no end-around carry (i.e. 0 carry), then the answer must be
recomplemented and a negative sign attached to it.
– If the end-around carry is 1, add it to the final answer and no
recomplementing is necessary.
 1’s Complement Subtraction

Example 1: Subtract 1012 from 1112.

Solution: The procedure is as follows:

111

+ 010

1001

1 end-around carry

010

Where the first 010 is 1’s complement of subtrahend 101 and 1 is the end-
around carry.
 1’s Complement Subtraction

Example 2: Subtract 11012 from 10102

Solution:

1010
0010

1100

As seen, there is no end-around carry in this case. Hence, the answer must
be recomplemented to get 0011 and a negative sign attached to it. Therefore, the
final answer becomes 0011.
 2’s Complement Subtraction

In this case, the steps for carrying this subtraction out are given
below:
• Find the 2’s complement of the subtrahend.
• Add this complement to the minuend.
• Drop the final carry.
• If the carry is 1, the answer is positive and needs no
recomplementing.
• If there is no carry, subtract 1 from the result, recomplement
it and then attach a minus sign.
 2’s Complement Subtraction

Example 1: Using 2’s complement, subtract 10102 from 11012.

Solution: The 1’s complement of 1010 is 0101. The 2’s complement is 0101 +
1 = 0110. We now add it to 1101.

1101

+ 0110

10011

Drop the final carry, the final answer is 00112.

 2’s Complement Subtraction
Example 2: Use 2’s complement to subtract 11012 from 10102.

Solution: The 1’s complement of 1101 is 0010. The 2’s complement is 0011.

1010
0011

1101

In this case, there is no carry. Hence, we have to recomplement the

answer. For this purpose, we first subtract 1 from it to get 1100. Next, we
recomplement it to get 0011. After, attaching the minus sign, the final answer

becomes 00112.
 LOGIC CIRCUITS
• Definition of a logic gate: A logic gate is an electronic circuit
which makes logic decisions. It has one output and one or
more inputs. The output signal appears only for certain
combinations of input signals.
• Logic gates serve as the basic building blocks from which most
of the digital systems are built up.
• They implement the hardware logic function based on the
logical algebra developed by George Boole which is called
Boolean algebra.
• Variables used in Boolean algebra can only be one of the two
values i.e. either 0 or 1.
 LOGIC CIRCUITS
• Digital circuits called logic gates can be constructed from
diodes, transistors, and resistors connected, so that the circuit
output is the result of a basic logic operation (OR, AND, NOT)
performed on the inputs.
 Types of logic gate

• The three types of essential logic gate are:

– AND gate
– OR gate
– NOT gate
• With these three gates, any possible Boolean equation can be
implemented.
 Truth table

• A truth table can be defined as a table which gives the output

state for all possible input combinations.
• In other words, a truth table is a means for describing how a
logic circuit’s output depends on the logic levels present at
the circuit’s inputs.
• Fig. 6.4 illustrates a truth table for one type of two-input logic
circuit.
 Truth table

Figure 6.4: Truth table for two-input

 Truth table

• Note: There are 4 table entries for the two-input truth tables,
8 entries for a three-input truth table and 16 entries for the
four-input truth table.
• The number of input combinations will equal for an N-input
truth table.
 The OR gate

• The truth table for a two-input OR gate is shown in Fig. 6.5 (a)
and its equivalent symbol in Fig. 6.5 (b).
• The two inputs have been marked as A and B and the output
as A+B.
• The table shows that A+B is logic 1 for every combination of
input levels where one or more inputs are 1. The only case
where A+B is a 0 is when both inputs are 0.
 The OR gate

• The OR gate logic operation

– The OR gate has an output of 1 when either A or B or both are 1
otherwise it is 0.

Figure 6.5 (a): Truth table Figure 6.5 (b): OR Gate

The Boolean expression for the OR operation is F  A  B

Note: In this expression, the + sign does not stand for ordinary addition, it
stands for the OR operation and F  A  B is read as “ F equals A OR B”.
 The AND gate
• The truth table for a two-input AND gate is shown in Fig. 6.6
(a) and its equivalent symbol in Fig. 6.6 (b).
• The two inputs have been marked as A and B and the output
as A●B.
• The table shows that A●B is a logic 1 only when both A and B
are at the logic 1 state. For any case where one of the inputs is
0, the output is 0.
 The AND gate
• The AND gate logic operation
– The AND gate has an output of 1 only if all its inputs are 1. Its output
would be 0 if any of its inputs is 0.

Figure 6.6 (a): Truth table Figure 6.6 (b): AND Gate

The Boolean expression for the AND operation is F = A●B

Note: In this expression, the sign ● stands for the Boolean AND operation and
not the multiplication operation. Also note that, the expression F = A●B is read
as “ F equals A AND B”.
 The NOT gate

• It is so called because its output is NOT the same as its input.

• It is also called an inverter because it inverts (compliments)
the input signal.
• All it does is to invert the input as shown in its Fig. 6.7 (a).
• It has one input and one output as shown in Fig. 6.7 (b)
• For example, if the variable A is subjected to the NOT
operation, the result F can be expressed as F = Ā
• Where the over bar represents the NOT operation.
• This expression is read as “F equals NOT A” or “F equals the
inverse of A” or “F equals the compliment of A”.
• Each of these is a common usage and all indicate that the
logic value F = Ā is opposite to the logic value of A.
 The NOT gate

• The truth table in Fig. 6.7 (a) clarifies this for the two cases
and , that is
• because 0 is not 1
• because 1 is not 0

Figure 6.7 (a): Truth table Figure 6.7 (b): NOT Gate
 NOR Gates and NAND Gates

• Two other types of logic gates, NOR gates and NAND gates are
widely used in digital circuits.
• These gates actually combine the basic AND, OR, and NOT
operations, so it is a relatively very simple to write their
Boolean expressions.
 The NOR Gate

• It is a NOT-OR gate. It can also be made out of an OR gate by

combining an inverter in its output.
• The symbol for a two-input NOR gate is shown in Fig. 6.8.
• It is the same as the OR gate symbol except that it has a small
circle on the output.
• The small circle represents the inversion operation.
• Thus, the NOR gate operates like an OR gate followed by an
INVERTER, so that the output expression for the NOR gate is
.
 The NOR Gate

Figure 6.8 (a): Truth table Figure 6.8 (b): NOR Gate
 The NAND Gate

• It is a NOT-AND gate. It can be obtained by connecting a NOT

gate in the output of an AND gate.
• The symbol for a two-input NAND gate is shown in Fig. 6.9 (a).
• It is the same as the AND gate symbol except for the small
circle on its output.
• Once again, the small circle denotes the inversion operation.
• Thus, the NAND operates like an AND gate followed by an
INVERTER, so that the output expression for the NAND gate is
 The NAND Gate

Figure 6.9 (a): Truth table Figure 6.9 (b): NAND Gate
 Types of Logic circuits
• Logic circuits can be classified into Combinational logic circuits
and Sequential logic circuits.
• These are the basic circuits used in most of the digital
electronic devices like Computers, Calculators, Mobile
phones, etc.
 Types of Logic circuits
• Combinational logic circuits:
– Combinational logic circuits are basically made up of digital
logic gates like AND gate, OR gate, NOT gate and universal
gates (NAND gate and NOR gate)
– All these gates are combined together to form a
complicated switching circuit.
– In combinational logic circuit, the output at any instant of
time depends only on present input at that particular time.
– Combinational logic circuits do not have any memory
elements.
– Combinational circuits are used in microprocessor and
microcontroller for designing the hardware and software
components of a computer.
Combinational logic circuit
 Types of Logic circuits
• Sequential logic circuits:
– In sequential circuit the output of the logic device is not
only dependent on the present inputs to the device, but
also on past inputs.
– Unlike combinational circuits, the sequential circuits have
memory devices in order to store the past outputs.
– In fact sequential digital logic circuits are nothing but
combinational circuit with memory.
– Examples of sequential logic circuits are counters, flip
flops, constructed using digital logic gates and memory.
Sequential logic circuit
 Combinational Logic Circuits
• Combinational logic circuits are the ones in which the logic
level at the output depends on the combination of logic levels
present at the inputs.
• A combinational circuit has no memory characteristic, so its
output depends only on the current value of its inputs.
• To simplify the combinational logic circuits, two methods will
be used; one uses Boolean algebra theorems; the other uses a
mapping technique.
 Sum-of-Product Form
• The methods of logic-circuit simplification and design that we
will study require the logic expression to be in a sum-of-
products (SOP) form.
• Some examples of this form are:
1. ABC  ABC
2. AB  ABC  CD  D
3. AB  CD  EF  GK  H L
 Product-of-Sums

• Another general form for logic expressions is sometimes used

in logic circuit design called the product-of-sums (POS) form.
• It consists of two or more OR terms (sums) that are ANDed
together.
• Each OR term contains one or more variables in
complemented or uncomplemented form.
• Here are some product-of-sum expressions:
1. ( A  B  C )( A  C )

2. ( A  B)(C  D) F

3. ( A  C )( B  D)( B  C )( A  D  E )
 Simplifying Logic Circuits
• Once the expression for a logic circuit has been obtained, we
may be able to reduce it to a simpler form containing fewer
terms or fewer variables in one or more terms.
• The new expression can then be used to implement a circuit
that is equivalent to the original circuit but that contains
fewer gates and connections.
Boolean Theorems
 Boolean Theorems
Commutative laws:
x y  yx
x y  y x
Associative laws:
x  ( y  z)  ( x  y)  z  x  y  z
x( yz )  ( xy ) z  xyz
Distributive laws:
x( y  z )  xy  xz
( w  x)( y  z )  wy  xy  wz  xz
DeMorgan’s theorems:

( x  y)  x  y
x  y  ( x  y)
 Algebraic Simplification
The following steps are followed in order to take the given
expressions to their simplest form:
• The original expression is put into SOP form by repeated
application of DeMorgan’s theorems and multiplication of
terms.
• Once the original expression is in SOP form, the product terms
are checked for common factors, and factoring is performed
whenever possible. The factoring should result in the
elimination of one or more terms.
 Algebraic Simplification
Simplify the logic circuit shown in Figure 2 (a)
 Algebraic Simplification
Solution:
 The first step is to determine the expression for the output.

Z  ABC  AB  ( AC )
 Once the expression is determined, it is usually a good idea to break down all large
inverter signs using DeMorgan’s theorems and then multiply out all terms.

Z  ABC  AB( A  C ) [DeMorgan’s theorems ]

Z  ABC  AB( A  C ) [Cancel double inversions]

Z  ABC  ABA  ABC [Multiply out]

Z  ABC  AB  ABC [ A A  A ]
 Algebraic Simplification
 With the expression now in SOP form, we should look for common variables among
the various terms with the intention of factoring. The first and third terms above have
AC in common, which can be factored out:
Z  AC ( B  B)  AB

Since B  B  1, then

Z  AC (1)  AB
Z  AC  AB
We can now factor out A, which results in
Z  A(C  B)
This result can be simplified no further. Its circuit implementation is shown below:

Figure 2 (b)
 Algebraic Simplification
Simplify the expression Z  ABC  ABC  ABC
Solution:
 The expression is already in SOP form
 The first two terms in the expression have the product AB in common, thus,
Z  AB(C  C )  ABC
Z  AB(1)  ABC
Z  AB  ABC
 We can factor the variable A from both terms:
Z  A( B  BC )

 x  xy  x  y 
 Invoking theorem  
 x  xy  x  y 

Thus, Z  A( B  C )
 Algebraic Simplification
OR

 The original expression is Z  ABC  ABC  ABC , the first two terms have AB in
common. The last two terms have AC in common. How do we know whether to

factor AB from the first two terms or AC from the last two terms? Actually, we can

do both by using the ABC term twice. In other words, we can rewrite the expression
as:
Z=ABC  ABC  ABC  ABC
 This is valid and will not change the value of the expression because
ABC  ABC  ABC . Now we can factor AB from the first two terms and AC from
the last two terms:
Z  AB(C  C )  AC ( B  B )
Z  AB  1  AC  1
Z  AB  AC
Z  A( B  C )
 Algebraic Simplification
Simplify Z  AC ( ABD)  ABCD  ABC
Solution:
 First, use DeMorgan’s theorem on the first term:
Z  AC ( A  B  D)  ABCD  ABC
 Multiplying out yields,
Z  ACA  ACB  ACD  ABCD  ABC
Because A  A  0, the first term is eliminated:

Z  ABC  ACD  ABCD  ABC

 This is the desired SOP form. Now we look for common factors.
 The first and last terms have the common factor BC , and the second and third terms
share the common factor AD . Thus,
Z  BC ( A  A)  AD(C  BC )

 Now, because A  A  1 , and C  BC  C  B , we have

Z  BC  AD( B  C )
 Algebraic Simplification
Simplify the expression X  ( A  B)( A  B  D) D
Solution:
 The expression can be put into sum-of-product form by multiplying out all the terms.
X  AAD  ABD  ADD  BAD  BBD  BDD
The result is,
X  ABD  ABD  BD
 We can factor BD from each term to obtain X  BD( A  A  1)
 Clearly, the term inside the parenthesis is always 1, so we finally have,

X  BD
 Algebraic Simplification
Simplify the circuit in Figure 3 (a)

Figure 3 (a)
Solution:
The expression for output Z is
Z  ( A  B)( A  B)
Multiplying out to get the sum-of-product form, we obtain
Z  AA  AB  BA  BB
We can eliminate AA  0 and BB  0 to end up with

Z  AB  AB
 Algebraic Simplification

• This expression is implemented in Figure 3 (b) and if we

compare it with the original circuit, we see that both circuits
contain the same number of gates and connections.
• In this case, the simplification process produced an
equivalent, but not simpler circuit.
 Designing Combinational Logic
Circuits
• When the desired output level of a logic circuit is given for all
possible input conditions, the results can be conveniently
displayed in a truth table.
• The Boolean expression for the required circuit can then be
derived from the truth table.
• For Example:
 Designing Combinational Logic
Circuits
• This same procedure can be extended to examples with more
than two inputs.
• Consider the truth table for a three-input circuit below.
 Designing Combinational Logic
Circuits
• Here there are three cases where the output x is to be 1.
• The required AND term for each of these cases is shown.
• Again, note that for each case where a variable is 0, it appears
inverted in the AND term.
• The sum-of-products expression for x is obtained by ORing the
three AND terms.
 Complete Design Procedure

Any logic problem can be solved using the following step-by-step

procedure.
1. Interpret the problem and set up a truth table to describe
its operation.
2. Write the AND (product) term for each case where the
output is 1.
3. Write the sum-of-products (SOP) expression for the output.
4. Simplify the output expression if possible.
5. Implement the circuit for the final, simplified expression.
 Example 1
Design a logic circuit that has three inputs, A, B, and C, and
whose output will be HIGH only when a majority of the inputs
are HIGH.
Solution:
• Step 1. Set up the truth table.
• On the basis of the problem statement, the output x should
be 1 whenever two or more inputs are 1; for all other cases,
the output should be 0.
 Example 1

• Step 2. Write the AND term for each case where the output is
a 1.
• There are four such cases. The AND terms are shown next to
the truth table. Again note that each AND term contains each
input variable in either inverted or non-inverted form.
• Step 3. Write the sum-of-products expression for the output.
 Example 1
• Step 4. Simplify the output expression.
• This expression can be simplified in several ways. Perhaps the
quickest way is to realize that the last term ABC has two
variables in common with each of the other terms. Thus, we
can use the ABC term to factor with each of the other terms.
The expression is rewritten with the ABC term occurring three
times.

• Factoring the appropriate pairs of terms, we have

• Each term in parentheses is equal to 1, so we have

 Example 1
• Step 5. Implement the circuit for the final expression.
• This expression is implemented in Figure 6. Since the
expression is in SOP form, the circuit consists of a group of
AND gates working into a single OR gate.
 Example 2
Consider the figure below, where an analog-to-digital converter
is monitoring the dc voltage of a 12-V storage battery on an
orbiting spaceship. The converter’s output is a four-bit binary
number, ABCD, corresponding to the battery voltage in steps of 1
V, with A as the MSB. The converter’s binary outputs are fed to a
logic circuit that is to produce a HIGH output as long as the
binary value is greater than 01102 = 610; that is, the battery
voltage is greater than 6 V. Design this logic circuit.
 Example 2
• Solution
 Example 2
The output z is set equal to 1 for all those cases where the binary number is greater than 0110.
For all other cases, z is set equal to 0. This truth table gives us the following sum-of-products
expression:
z  ABCD  ABCD  ABCD  ABCD  ABCD  ABCD  ABCD  ABCD  ABCD
Simplification of this expression will be a formidable task, but with a little care it can be
accomplished. The step-by-step process involves factoring and eliminating terms of the form
A A:

z  ABCD  ABC ( D  D)  ABC ( D  D )  ABC ( D  D )  ABC ( D  D )

z  ABCD  ABC  ABC  ABC  ABC
z  ABCD  AB(C  C )  AB(C  C )
z  ABCD  AB  AB
z  ABCD  A( B  B)
z  ABCD  A
 Example
This can be reduced further, which says that x  xy  x  y. In this case x = A and y = BCD.
Thus,
z  ABCD  A
z  BCD  A

This final expression is implemented in Figure 7 (c).

 Example 3
The figure below shows a diagram for an automobile alarm
circuit used to detect certain undesirable conditions. The three
switches are used to indicate the status of the door by the
driver’s seat, the ignition, and the headlights, respectively.
Design the logic circuit with these three switches as inputs so
that the alarm will be activated whenever either of the following
conditions exists:
• The headlights are on while the ignition is off.
• The door is open while the ignition is on.
Example 3
 Example 3
Solution:
 Karnaugh Map Method

• The Karnaugh map (K map) is a graphical tool used to simplify

a logic equation or to convert a truth table to its
corresponding logic circuit in a simple, orderly process.
• Although a K map can be used for problems involving any
number of input variables, its practical usefulness is limited to
five or six variables.
• The following discussion will be limited to problems with up
to four inputs because even five- and six-input problems are
too involved and are best done by a computer program.
 Karnaugh Map Format

• The K map, like a truth table, is a means for showing the

relationship between logic inputs and the desired output.
• The figure below show three examples of K maps for two,
three, and four variables, together with the corresponding
truth tables.
• These examples illustrate the following important points:
– The truth table gives the value of output X for each
combination of input values.
– The K-map squares are labelled so that horizontally and
vertically adjacent squares differ only in one variable.
Likewise, each square in the top row is considered to be
adjacent to a corresponding square in the bottom row.
 Karnaugh Map Format

– In order for vertically and horizontally adjacent squares to

differ in only one variable, the top-to-bottom labelling
must be done in the order shown: AB, AB, AB, AB. The
same is true of the left-to-right labeling: C D, CD, CD, C D.
– Once a K map has been filled with 0s and 1s, the sum-of-
products expression for the output X can be obtained by
ORing together those squares that contain a 1.
Karnaugh Map Format
Karnaugh Map Format
 Looping
• The expression for output X can be simplified by properly
combining those squares in the K map that contain 1s.
• The process for combining these 1s is called looping.
 Looping Groups of Two (Pairs)

• Consider the following figures:

Looping Groups of Two (Pairs)
 Looping Groups of Two (Pairs)

• Looping a pair of adjacent 1s in a K map eliminates the

variable that appears in complemented and
uncomplemented form.
Looping Groups of Four (Quads)
Looping Groups of Four (Quads)
Looping Groups of Four (Quads)
 Looping Groups of Four (Quads)
• Looping a quad of adjacent 1s eliminates the two variables
that appear in both complemented and uncomplemented
form.
 Looping Groups of Eight (Octets)
• Consider the following figures:
Looping Groups of Eight (Octets)
 Looping Groups of Eight (Octets)
• Looping an octet of adjacent 1s eliminates the three
variables that appear in both complemented and
uncomplemented form.
 Complete Simplification Process
• We have seen how looping of pairs, quads, and octets on a K
map can be used to obtain a simplified expression.
• We can summarize the rule for loops of any size:
• When a variable appears in both complemented and
uncomplemented form within a loop, that variable is
eliminated from the expression.
• Variables that are the same for all squares of the loop must
appear in the final expression.
• It should be clear that a larger loop of 1s eliminates more
variables.
• To be exact, a loop of two eliminates one variable, a loop of
four eliminates two variables, and a loop of eight eliminates
three.
 Complete Simplification Process
• The steps below are followed in using the K-map method for
simplifying a Boolean expression:
– Step 1: Construct the K map and place 1s in those squares
corresponding to the 1s in the truth table. Place 0s in the
other squares.
– Step 2: Examine the map for adjacent 1s and loop those 1s
that are not adjacent to any other 1s. These are called
isolated 1s.
– Step 3: Next, look for those 1s that are adjacent to only
one other 1. Loop any pair containing such a 1.
– Step 4: Loop any octet even if it contains some 1s that
have already been looped.
Complete Simplification Process
– Step 5 Loop any quad that contains one or more 1s that
have not already been looped, making sure to use the
minimum number of loops.
– Step 6 Loop any pairs necessary to include any 1s that
have not yet been looped, making sure to use the
minimum number of loops.
– Step 7 Form the OR sum of all the terms generated by
each loop.
 Example 1
• The figure (a) below shows the K map for a four-variable
problem.

• We will assume that the map was obtained from the problem
truth table (step 1). The squares are numbered for
convenience in identifying each loop.
 Example 1
• Step 2 Square 4 is the only square containing a 1 that is not
adjacent to any other 1. It is looped and is referred to as loop 4.
• Step 3 Square 15 is adjacent only to square 11. This pair is
looped and referred to as loop 11, 15.
• Step 4 There are no octets.
• Step 5 Squares 6, 7, 10, and 11 form a quad. This quad is looped
(loop 6, 7, 10, 11). Note that square 11 is used again, even
though it was part of loop 11, 15.
• Step 6 All 1s have already been looped.
• Step 7 Each loop generates a term in the expression for X. Loop
4 is simply . Loop 11, 15 is ACD (the B variable is
eliminated). Loop 6, 7, 10, 11 is BD (A and C are eliminated).
 Example 2
• Consider the K map in Figure (b). Once again, we can assume
that step 1 has already been performed.
 Example 2
• Step 2 There are no isolated 1s.
• Step 3 The 1 in square 3 is adjacent only to the 1 in square 7.
Looping this pair (loop 3, 7) produces the term
• Step 4 There are no octets.
• Step 5 There are two quads. Squares 5, 6, 7, and 8 form one
quad. Looping this quad produces the term The second
quad is made up of squares 5, 6, 9, and 10. This quad is
looped because it contains two squares that have not been
looped previously. Looping this quad produces
• Step 6 All 1s have already been looped.
• Step 7 The terms generated by the three loops are ORed
together to obtain the expression for X.
 Example 3
• Consider the K map in Figure (c).
 Example 3
• Step 2 There are no isolated 1s.
• Step 3 The 1 in square 2 is adjacent only to the 1 in square 6.
This pair is looped to produce Similarly, square 9 is
adjacent only to square 10. Looping this pair produces
Likewise, loop 7, 8 and loop 11, 15 produce the terms
and ACD, respectively.
• Step 4 There are no octets.
• Step 5 There is one quad formed by squares 6, 7, 10, and 11.
This quad, however, is not looped because all the 1s in the
quad have been included in other loops.
• Step 6 All 1s have already been looped.
• Step 7 The expression for X is shown in the Figure 13 (c).
 Example 3
• Consider the following K-maps:
 Example 3
• Step 2 There are no isolated 1s.
• Step 3 There are no 1s that are adjacent to only one other 1.
• Step 4 There are no octets.
• Step 5 There are no quads.
• Steps 6 and 7 There are many possible pairs. The looping
must use the minimum number of loops to account for all the
1s. For this map, there are two possible loopings, which
require only four looped pairs. Figure (a) shows one solution
and its resultant expression. Figure (b) shows the other.
Note that both expressions are of the same complexity, and so
neither is better than the other.
 Don’t-Care Conditions
• Some logic circuits can be designed so that there are certain
input conditions for which there are no specified output
levels, usually because these input conditions will never occur.
• In other words, there will be certain combinations of input
levels where we “don’t care” whether the output is HIGH or
LOW.
• This is illustrated in the truth table below.
Don’t-Care Conditions
 Don’t-Care Conditions
• Example: Design a logic circuit that controls an elevator door
in a three-story building. The circuit in Figure (a) has four
inputs. M is a logic signal that indicates when the elevator is
moving (M = 1) or stopped (M = 0). F1, F2, and F3 are floor
indicator signals that are normally LOW, and they go HIGH
only when the elevator is positioned at the level of that
particular floor. For example, when the elevator is lined up
level with the second floor, F2 = 1 and F1 = F3 = 0. The circuit
output is the OPEN signal, which is normally LOW and will go
HIGH when the elevator door is to be opened.
Don’t-Care Conditions
 Don’t-Care Conditions
• We can fill in the truth table for the OPEN output [Figure (b)]
as follows:
– Because the elevator cannot be lined up with more than
one floor at a time, only one of the floor inputs can be
HIGH at any given time. This means that all those cases in
the truth table where more than one floor input is a 1 are
don’t-care conditions. We can place an x in the OPEN
output column for those eight cases where more than one
F input is 1.
 Don’t-Care Conditions
– Looking at the other eight cases, when M = 1 the elevator
is moving, so OPEN must be a 0 because we do not want
the elevator door to open. When M = 0 (elevator stopped)
we want OPEN 1 provided that one of the floor inputs is 1.
When M = 0 and all floor inputs are 0, the elevator is
stopped but is not properly lined up with any floor, so we
want OPEN 0 to keep the door closed.
• The truth table is now complete and we can transfer its
information to the K map in Figure (c). The map has only three
1s, but it has eight don’t cares. By changing four of these
don’t-care squares to 1s, we can produce quad loopings that
contain the original 1s [Figure (d)]. This is the best we can do
as far as minimizing the output expression. Verify that the
loopings produce the OPEN output expression shown.
Don’t-Care Conditions
 Flip-Flops
• The logic circuits considered thus far have been combinational
circuits whose output levels at any instant of time are
dependent on the levels present at the inputs at that time.
• Any prior input-level conditions have no effect on the present
outputs because combinational logic circuits have no memory.
• Most digital systems consist of both combinational circuits
and memory elements.
• The figure below shows a block diagram of a general digital
system that combines combinational logic gates with memory
• devices.
 Flip-Flops
• The combinational portion accepts logic signals from external
inputs and from the outputs of the memory elements.
• The combinational circuit operates on these inputs to produce
various outputs, some of which are used to determine the
binary values to be stored in the memory elements.
• The outputs of some of the memory elements, in turn, go to
the inputs of logic gates in the combinational circuits.
• This process indicates that the external outputs of a digital
system are functions of both its external inputs and the
information stored in its memory elements.
Flip-Flops
 Flip-Flops
• The most important memory element is the flip-flop, which is
made up of an assembly of logic gates.
• Even though a logic gate, by itself, has no storage capability,
several can be connected together in ways that permit
information to be stored.
• Several different gate arrangements are used to produce
these flip-flops (abbreviated FF).
 Flip-Flops
The figure (a) is the general symbol used for a flip-flop. It shows two outputs, labeled Q and
Q that are the inverse of each other. Q/ Q are the most common designations used for a FF’s

outputs. From time to time, we will use other designations such as X/ X and A/ A for
convenience in identifying different FFs in a logic circuit.
 Flip-Flops
The Q output is called the normal FF output, and Q is the inverted FF output. Whenever we
refer to the state of a FF, we are referring to the state of its normal (Q) output; it is understood
that its inverted output ( Q ) is in the opposite state. For example, if we say that a FF is in the
HIGH (1) state, we mean that Q = 1; if we say that a FF is in the LOW (0) state, we mean that
Q = 0. Of course, the state will always be the inverse of Q.
The two possible operating states for a FF are summarized in Figure (b). Note that the HIGH
or 1 state (Q =1/ Q = 0) is also referred to as the SET state. Whenever the inputs to a FF
cause it to go to the state, we call this setting the FF; the FF has been set. In a similar way, the
LOW or 0 state (Q = 0/ Q = 1) is also referred to as the CLEAR or RESET state. Whenever
the inputs to a FF cause it to go to the Q = 0 state, we call this clearing or resetting the FF;
the FF has been cleared (reset). As we shall see, many FFs will have a SET input and/or a
CLEAR (RESET) input that is used to drive the FF into a specific output state.
Flip-Flops
 Flip-Flops
• As the symbol in Figure (a) implies, a FF can have one or more
inputs.
• These inputs are used to cause the FF to switch back and forth
(“flip-flop”) between its possible output states.
• We will find out that most FF inputs need only to be
momentarily activated (pulsed) in order to cause a change in
the FF output state, and the output will remain in that new
state even after the input pulse is over.
• This is the FF’s memory characteristic.
 Flip-Flops
• The flip-flop is known by other names, including latch and
bistable multivibrator.
• The term latch is used for certain types of flip-flops that we
will describe.
• The term bistable multivibrator is the more technical name for
a flip-flop, but it is too much of a mouthful to be used
regularly.
 NAND gate Latch
The most basic FF circuit can be constructed from either two NAND gates or two NOR gates.
The NAND gate version, called a NAND gate latch or simply a latch, is shown in Figure (a).
The two NAND gates are cross-coupled so that the output of NAND-1 is connected to one of
the inputs of NAND-2, and vice versa. The gate outputs labelled Q and Q respectively, are
the latch outputs. Under normal conditions, these outputs will always be the inverse of each
other. There are two latch inputs: the SET input is the input that sets Q to the 1 state; the
RESET input is the input that resets Q to the 0 state.
 NAND gate Latch

The SET and RESET inputs are both normally resting in the HIGH state, and one of them
will be pulsed LOW whenever we want to change the latch outputs. We begin our analysis by
showing that there are two equally likely output states when SET = RESET = 1. One
possibility is shown in Figure (a), where we have Q = 0 and Q = 1. With Q = 0, the inputs to

NAND-2 are 0 and 1, which produce Q = 1. The 1 from Q causes NAND-1 to have a 1 at
both inputs to produce a 0 output at Q. In effect, what we have is the LOW at the NAND-1
output producing a HIGH at the NAND-2 output, which, in turn, keeps the NAND-1 output
LOW.
NAND gate Latch
 NAND gate Latch
The second possibility is shown in Figure (b), where Q =1 and Q = 0. The HIGH from
NAND-1 produces a LOW at the NAND-2 output, which, in turn, keeps the NAND-1 output
HIGH. Thus, there are two possible output states when SET = RESET = 1; as we shall soon
see, the one that actually exists will depend on what has occurred previously at the inputs.
 Setting the Latch (FF)
Now let’s investigate what happens when the SET input is momentarily pulsed LOW while
RESET is kept HIGH. Figure (a) shows what happens when Q = 0 prior to the occurrence of
the pulse. As SET is pulsed LOW at time t0, Q will go HIGH, and this HIGH will force Q to
go LOW so that NAND-1 now has two LOW inputs. Thus, when SET returns to the 1 state at
t1, the NAND-1 output remains HIGH, which, in turn, keeps the NAND-2 output LOW.
 Setting the Latch (FF)

 Figure (b) shows what happens when Q = 1and Q = 0 prior to the application of the
SET pulse. Since Q = 0 is already keeping the NAND-1 output HIGH, the LOW
pulse at SET will not change anything. Thus, when SET returns HIGH, the latch
outputs are still in the Q = 1, Q = 0 state.
 We can summarize both Figure (a) and (b) by stating that a LOW pulse on the SET
input will always cause the latch to end up in the Q = 1 state. This operation is called
setting the latch or FF.
 Resetting the Latch (FF)
 Now let’s consider what occurs when the RESET input is pulsed LOW while SET is
kept HIGH. Figure (a) shows what happens when Q 0 and Q = 1 prior to the
application of the pulse. Since Q = 0 is already keeping the NAND-2 output HIGH,
the LOW pulse at RESET will not have any effect. When RESET returns HIGH, the
latch outputs are still Q = 0 and Q = 1.
 Resetting the Latch (FF)
 Figure (b) shows the situation where Q = 1 prior to the occurrence of the RESET
pulse. As RESET is pulsed LOW at t0, Q will go HIGH, and this HIGH forces Q to
go LOW so that NAND-2 now has two LOW inputs. Thus, when RESET returns
HIGH at t1, the NAND-2 output remains HIGH, which, in turn, keeps the NAND-1
output LOW.

 The figures above can be summarized by stating that a LOW pulse on the RESET
input will always cause the latch to end up in the Q = 0 state. This operation is called
clearing or resetting the latch.
 Simultaneous Setting and Resetting
• The last case to consider is the case where the SET and RESET
inputs are simultaneously pulsed LOW. This will produce HIGH
levels at both NAND outputs so that Q = = 1.
• Clearly, this is an undesired condition because the two
outputs are supposed to be inverses of each other.
• Furthermore, when the SET and RESET inputs return HIGH,
the resulting output state will depend on which input returns
HIGH first.
• Simultaneous transitions back to the 1 state will produce
unpredictable results.
• For these reasons the SET = RESET = 0 condition is normally
not used for the NAND latch.
 Summary of NAND Latch
• The operation described above can be conveniently placed in
a function table and is summarized as follows:
– SET = RESET = 1: This condition is the normal resting state,
and it has no effect on the output state. The Q and
outputs will remain in whatever state they were in prior to
this input condition.
– SET = 0, RESET = 1: This will always cause the output to go
to the Q = 1 state, where it will remain even after SET
returns HIGH. This is called setting the latch.
– SET = 1, RESET = 0: This will always produce the Q = 0 state,
where the output will remain even after RESET returns
HIGH. This is called clearing or resetting the latch.
 Summary of NAND Latch
– SET = RESET = 0: This condition tries to set and clear the
latch at the same time, and it produces Q = = 1. If the
inputs are returned to 1 simultaneously, the resulting state
is unpredictable. This input condition should not be used.
 NOR gate Latch
• Two cross-coupled NOR gates can be used as a NOR gate
latch.
• The arrangement, shown in Figure (a), is similar to the NAND
latch except that the Q and outputs have reversed
positions.
NOR gate Latch
 NOR gate Latch
• The analysis of the operation of the NOR latch can be
performed in exactly the same manner as for the NAND latch.
• The results are given in the function table in Figure (b) and are
summarized as follows:
– SET = RESET = 0: This is the normal resting state for the
NOR latch, and it has no effect on the output state. Q and
will remain in whatever state they were in prior to the
occurrence of this input condition.
 NOR gate Latch
– SET = 1, RESET = 0: This will always set Q = 1, where it will
remain even after SET returns to 0.
– SET = 0, RESET = 1: This will always clear Q = 0, where it will
remain even after RESET returns to 0.
– SET = 1, RESET = 1: This condition tries to set and reset the
latch at the same time, and it produces Q = = 0. If the
inputs are returned to 0 simultaneously, the resulting
output state is unpredictable. This input condition should
not be used.
 Digital pulses
• As you can see from our discussion of SR latches, there are
situations in digital systems when a signal switches from a
normal inactive state to the opposite (active) state, thus
causing something to happen in the circuit.
• Then the signal returns to its inactive state while the effect of
the recently activated signal remains in the system.
• These signals are called pulses, and it is very important to
understand the terminology associated with pulses and pulse
waveforms.
• A pulse that performs its intended function when it goes HIGH
is called a positive pulse, and a pulse that performs its
intended function when it goes LOW is called a negative
pulse.
 Digital pulses
• In actual circuits it takes time for a pulse waveform to change
from one level to the other.
• These transition times are called the rise time and the fall
time and are defined as the time it takes the voltage to
change between 10% and 90% of the HIGH level voltage as
shown on the positive pulse in Figure (a).
• The transition at the beginning of the pulse is called the
leading edge and the transition at the end of the pulse is the
trailing edge.
• The duration (width) of the pulse is defined as the time
between the points when the leading and trailing edges are at
50% of the HIGH level voltage. Figure (b) shows an active-LOW
or negative pulse.
Digital pulses
 Clock Signals and Clocked Flip-Flops
• Digital systems can operate either asynchronously or
synchronously.
• In asynchronous systems, the outputs of logic circuits can
change state any time one or more of the inputs change.
• An asynchronous system is generally more difficult to design
and troubleshoot than a synchronous system.
• In synchronous systems, the exact times at which any output
can change states are determined by a signal commonly called
the clock.
• This clock signal is generally a rectangular pulse train or a
square wave, as shown in the figure below.
 Clock Signals and Clocked Flip-Flops
• The clock signal is distributed to all parts of the system, and
most (if not all) of the system outputs can change state only
when the clock makes a transition.
• The transitions (also called edges) are pointed out in the
figure.
• When the clock changes from a 0 to a 1, this is called the
positive-going transition (PGT); when the clock goes from 1
to 0, this is the negative-going transition (NGT).
• We will use the abbreviations PGT and NGT because these
terms appear so often throughout the text.
 Clock Signals and Clocked Flip-Flops
• Most digital systems are principally synchronous (although
there are always some asynchronous parts) because
synchronous circuits are easier to design and troubleshoot.
• They are easier to troubleshoot because the circuit outputs
can change only at specific instants of time.
• In other words, almost everything is synchronized to the
clock-signal transitions.
• The synchronizing action of the clock signals is accomplished
through the use of clocked flip-flops that are designed to
change states on one or the other of the clock’s transitions.
Clock Signals and Clocked Flip-Flops
 Clocked Flip-Flops
• Several types of clocked FFs are used in a wide range of
applications. Before we begin our study of the different
clocked FFs, we will describe the principal ideas that are
common to all of them.
– Clocked FFs have a clock input that is typically labelled CLK,
CK, or CP. We will normally use CLK, as shown in the figure
below.
– In most clocked FFs, the CLK input is edge-triggered, which
means that it is activated by a signal transition; this is
indicated by the presence of a small triangle on the CLK
input. This contrasts with the latches, which are level-
triggered.
 Clocked Flip-Flops
– Figure (a) is a FF with a small triangle on its CLK input to
indicate that this input is activated only when a positive-
going transition (PGT) occurs; no other part of the input
pulse will have an effect on the CLK input.
– In Figure (b), the FF symbol has a bubble as well as a
triangle on its CLK input.
– This signifies that the CLK input is activated only when a
negative-going transition occurs; no other part of the input
pulse will have an effect on the CLK input.
 Clocked Flip-Flops
• Clocked FFs also have one or more control inputs that can
have various names, depending on their operation.
• The control inputs will have no effect on Q until the active
clock transition occurs.
• In other words, their effect is synchronized with the signal
applied to CLK.
• For this reason they are called synchronous control inputs.
• For example, the control inputs of the FF in Figure (a) will have
no effect on Q until the PGT of the clock signal occurs.
• Likewise, the control inputs in Figure (b) will have no effect
until the NGT of the clock signal occurs.
 Clocked Flip-Flops
• In summary, we can say that the control inputs get the FF
outputs ready to change, while the active transition at the CLK
input actually triggers the change.
• The control inputs control the WHAT (i.e., what state the
output will go to); the CLK input determines the WHEN.
 Clocked S-R Flip-Flop
• Figure (a) below shows the logic symbol for a clocked S-R flip-
flop that is triggered by the positive-going edge of the clock
signal.
• This means that the FF can change states only when a signal
applied to its clock input makes a transition from 0 to 1.
• The S and R inputs control the state of the FF in the same
manner as described earlier for the NOR gate latch, but the FF
does not respond to these inputs until the occurrence of the
PGT of the clock signal.
 Clocked S-R Flip-Flop
• The function table in Figure (b) below shows how the FF
output will respond to the PGT at the CLK input for the various
combinations of S and R inputs. This function table uses some
new nomenclature.
• The up arrow indicates that a PGT is required at CLK; the
label indicates the level at Q prior to the PGT. This
nomenclature is often used by IC manufacturers in their IC
data manuals.
• The waveforms in Figure (c) below illustrate the operation of
the clocked S-R flip-flop.
• If we assume that the setup and hold time requirements are
being met in all cases, we can analyze these waveforms as
follows:
Clocked S-R Flip-Flop
Clocked S-R Flip-Flop
 Clocked S-R Flip-Flop
• Initially all inputs are 0 and the Q output is assumed to be 0;
that is,
• When the PGT of the first clock pulse occurs (point a), the S
and R inputs are both 0, so the FF is not affected and remains
in the Q = 0 state (i.e. Q = ).
• At the occurrence of the PGT of the second clock pulse (point
c), the S input is now high, with R still low. Thus, the FF sets to
the 1 state at the rising edge of this clock pulse.
• When the third clock pulse makes its positive transition (point
e), it finds that S = 0 and R = 1, which causes the FF to clear to
the 0 state.
 Clocked S-R Flip-Flop
• The fourth pulse sets the FF once again to the Q = 1 state
(point g) because S = 1 and R = 0, when the positive edge
occurs.
• The fifth pulse also finds that S = 1 and R = 0 when it makes its
positive going transition. However, Q is already high, so it
remains in that state.
• The S = R = 1 condition should not be used because it results
in an ambiguous condition.
 Clocked S-R Flip-Flop
• It should be noted from these waveforms that the FF is not
affected by the negative-going transitions of the clock pulses.
• Also, note that the S and R levels have no effect on the FF,
except upon the occurrence of a positive-going transition of
the clock signal.
• The S and R inputs are synchronous control inputs; they
control which state the FF will go to when the clock pulse
occurs.
• The CLK input is the trigger input that causes the FF to
change states according to what the S and R inputs are when
the active clock transition occurs.
 Clocked S-R Flip-Flop
• The figure below shows the symbol and the function table for
a clocked S-R flip-flop that triggers on the negative-going
transition at its CLK input.
• The small circle and triangle on the CLK input indicates that
this FF will trigger only when the CLK input goes from 1 to 0.
• This FF operates in the same manner as the positive-edge FF
except that the output can change states only on the falling
edge of the clock pulses (points b, d, f, h, and j).
• Both positive-edge and negative-edge triggering FFs are used
in digital systems.
Clocked S-R Flip-Flop
 Clocked J-K Flip-Flop
• Figure (a) below shows a clocked J-K flip-flop that is triggered
by the positive going edge of the clock signal.
• The J and K inputs control the state of the FF in the same ways
as the S and R inputs do for the clocked S-R flip-flop except for
one major difference: the J = K = 1 condition does not result in
an ambiguous output.
• For this 1, 1 condition, the FF will always go to its opposite
state upon the positive transition of the clock signal.
• This is called the toggle mode of operation.
• In this mode, if both J and K are left HIGH, the FF will change
states (toggle) for each PGT of the clock.
 Clocked J-K Flip-Flop
• The function table in Figure (a) summarizes how the J-K flip-
flop responds to the PGT for each combination of J and K.
• Notice that the function table is the same as for the clocked S-
R flip-flop (Figure 5-19) except for the J = K = 1 condition.
• This condition results in which means that the new
value of Q will be the inverse of the value it had prior to the
PGT; this is the toggle operation.
Clocked J-K Flip-Flop
Clocked J-K Flip-Flop
 Clocked J-K Flip-Flop
• The operation of this FF is illustrated by the waveforms in
Figure (b). Once again, we assume that the setup and hold
time requirements are being met.
– Initially all inputs are 0, and the Q output is assumed to be
1; that is,
– When the positive-going edge of the first clock pulse
occurs (point a), the J = 0, K = 1 condition exists. Thus, the
FF will be reset to the Q = 0 state.
– The second clock pulse finds J = K = 1 when it makes its
positive transition (point c). This causes the FF to toggle to
its opposite state, Q = 1.
 Clocked J-K Flip-Flop
– At point e on the clock waveform, J and K are both 0, so
that the FF does not change states on this transition.
– At point g, J = 1 and K = 0. This is the condition that sets Q
to the 1 state. However, it is already 1, and so it will remain
there.
– At point i, J = K = 1 and so the FF toggles to its opposite
state. The same thing occurs at point k.
 Clocked J-K Flip-Flop
• Note from these waveforms that the FF is not affected by the
negative going edge of the clock pulses.
• Also, the J and K input levels have no effect except upon the
occurrence of the PGT of the clock signal.
• The J and K inputs by themselves cannot cause the FF to
change states.
• The figure below shows the symbol for a clocked J-K flip-flop
that triggers on the negative-going clock-signal transitions.
• The small circle on the CLK input indicates that this FF will
trigger when the CLK input goes from 1 to 0.
 Clocked J-K Flip-Flop
• This FF operates in the same manner as the positive-edge FF
of the previous figure except that the output can change
states only on negative-going clock-signal transitions (points
b, d, f, h, and j).
• Both polarities of edge-triggered J-K flip-flops are in common
usage.
• The J-K flip-flop is much more versatile than the S-R flip-flop
because it has no ambiguous states.
• The J = K = 1 condition, which produces the toggling
operation, finds extensive use in all types of binary counters.
• In essence, the J-K flip-flop can do anything the S-R flip-flop
can do plus operate in the toggle mode.
Clocked J-K Flip-Flop
 Clocked D Flip-Flop
• Figure (a) below shows the symbol and the function table for
a clocked D flipflop that triggers on a PGT.
• Unlike the S-R and J-K flip-flops, this flip-flop has only one
synchronous control input, D, which stands for data.
• The operation of the D flip-flop is very simple: Q will go to the
same state that is present on the D input when a PGT occurs
at CLK.
• In other words, the level present at D will be stored in the flip-
flop at the instant the PGT occurs.
• The waveforms in Figure (b) below illustrate this operation.
Clocked D Flip-Flop
Clocked D Flip-Flop
 Clocked D Flip-Flop
• Assume that Q is initially HIGH. When the first PGT occurs at
point a, the D input is LOW; thus, Q will go to the 0 state. Even
though the D input level changes between points a and b, it
has no effect on Q; Q is storing the LOW that was on D at
point a.
• When the PGT at b occurs, Q goes HIGH because D is HIGH at
that time. Q stores this HIGH until the PGT at point c causes Q
to go LOW because D is LOW at that time.
• In a similar manner, the Q output takes on the levels present
at D when the PGTs occur at points d, e, f, and g.
• Note that Q stays HIGH at point e because D is still HIGH.
 Clocked D Flip-Flop
• Again, it is important to remember that Q can change only
when a PGT occurs.
• The D input has no effect between PGTs.
• A negative-edge-triggered D flip-flop operates in the same
way just described Except that Q will take on the value of D
when a NGT occurs at CLK.
• The symbol for the D flip-flop that triggers on NGTs will have a
bubble on the CLK input.