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Sarath Kumar Jha

Sarath Kumar Jha has over 15 years of experience in semiconductor design and verification. He is currently the SoC Design Engineering Manager at Intel Corporation, where he manages verification teams and drives adoption of new verification methodologies. Previously, he held senior verification roles at Cadence Design Systems, Qualcomm, and other companies, where he led teams, defined verification strategies, and delivered several industry-leading verification IP products. He has three granted US patents related to forward error correction coding.

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212 views2 pages

Sarath Kumar Jha

Sarath Kumar Jha has over 15 years of experience in semiconductor design and verification. He is currently the SoC Design Engineering Manager at Intel Corporation, where he manages verification teams and drives adoption of new verification methodologies. Previously, he held senior verification roles at Cadence Design Systems, Qualcomm, and other companies, where he led teams, defined verification strategies, and delivered several industry-leading verification IP products. He has three granted US patents related to forward error correction coding.

Uploaded by

bhatia1990rahul
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We take content rights seriously. If you suspect this is your content, claim it here.
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Sarath Kumar Jha

P 1307 Stellar Jeevan


Sector 1, Greater Noida,
Uttar Pradesh (India)-203207

Education
2000 to 2005 Dual Degree (Master of Technology, Bachelor of Technology), Electrical Engineering
Indian Institute of Technology Bombay,
Powai, Mumabi, India – 400076

Experience
Intel Corporation, September 2020 to Present
Bangalore, India

SoC Design Engineering Manager


Manage the Coherent Interconnect Verification Team for next generation of Intel Datacentre products. Responsible
for hiring, training and tracking execution status of the team. Work with stakeholders and customers on schedules,
issues and roadmaps.
Manage the Validation Infrastructure and Architecture team to supply validation infrastructure to the Datacentre
Organization. Responsible for defining the validation strategy, roadmap and execution tracking for the team.
Drive the adoption of verification tools and methodologies such as UVM migration, Portable stimulus, formal
verification across the organization.

Cadence Design Systems, December 2018 to August 2020


Noida, India

Senior Principal Design Engineer


Manage the IPG Verification Team at the site (Cadence Noida) working on a wide class of peripherals such as PCIe,
USB, MIPI, CXL. Handled development as well as customer support for these IPs. Responsible for defining the
verification strategy, planning, resource allocation and tracking. Responsible for hiring, training and reward decisions
for the team.
Collaboration with sites in UK, USA, Poland and Bangalore on execution and planning.
Led the team to successful USB xHCI certification with the development of an indigenous Verification IP to handle
scenarios not covered with industry standard Verification IPs.

Qualcomm , October 2016 to December 2018


Noida, India

Staff Engineer
Lead for top level Custom PHY transmitter and receiver behavioral and mixed signal verification. Responsible for
verification planning and execution on critical blocks. Worked with the design team, test engineering team to finalize
requirements, resolve issues to reach the goal of zero bugs. The team reached the goal of a 7nm PHY working in the
silicon on the 1st pass.
Submitted innovation disclosure related to Synthesis Algorithms and Fault safety.

Cadence Design Systsems, December 2013 to October 2016


Noida, India

Principal Engineer
Verification Architect and Lead for industry leading Ethernet IEEE 802.3 400G Verification IP.
Key contributor and developer with multiple patents on the FEC (forward error correction code) layer which
differentiate the product and make it an industry leader.
Responsible for handling customer issues during initial deployment.
Responsible for training of Application Engineers across sites on the product.
Truechip Solutions, December 2010 to December 2011
Delhi, India

Lead Engineer
Responsible for hiring and training a team of 50+ engineers at the start up.
Verification Architect and Lead for Verification IPs at Truechip.
Responsibilities include product definition, planning, execution and customer support.

Smartplay Technologies, July 2010 to December 2010


Hyderabad, India

Senior Engineer
System level verification of northbridge-southbridge susbsystem for next generation of Fusion SoCs at AMD.
Verification of resets, clocking and interrupts.
Led the effort for migration of the verification environment to latest methodology.

Freescale Semiconductors July 2010 to December 2010


Noida, India

Senior Design Engineer


Verification lead and key individual contributor for verification of an Automotive Powertrain SoC.
Led the team through milestones of logic freeze, tape outs and support for silicon bring up.

Mirafra technologies June 2007 to May 2008


Bangalore, India

Verification Engineer
Verification of USB OHCI host controller for a mobile SoC.
Developed a reference model for OHCI in system verilog.
Collaborated with firmware team to test the firmware code in verification environment.

Ittiam Systems August 2005 to June 2007


Bangalore, India

Verification Engineer
Verification of WLAN 802.11 IP.
Implemented constrained random verification using perl and verilog.

Publications and Professional Memberships

US Patent 10355818 - Method and apparatus for codeword boundary detection for a scrambled Reed Solomon code
bitstream
US Patent 10020824 - Method and system for efficient block synchronization on a scrambled cyclic code bitstream
US Patent 9882585 - Systems and methods for partitioned root search for error locator polynomial functions in Reed
Solomon forward error correction decoding

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