ST93C67 - ST
ST93C67 - ST
ST93C67 - ST
ST93C67
DESCRIPTION
This specification covers a range of 4K bit serial
EEPROM products, the ST93C66 specified at 5V
± 10% and the ST93C67 specified at 3V to 5.5V. In
the text, products are referred to as ST93C66.
The ST93C66 is a 4K bit Electrically Erasable VCC
Programmable Memory (EEPROM) fabricated with
SGS-THOMSON’s High EnduranceSingle Polysili-
con CMOS technology. The memory is accessed
through a serial input (D) and output (Q). The 4K D Q
bit memory is divided into either 512 x 8 bit bytes
or 256 x 16 bit words. The organization may be C ST93C66
selected by a signal applied on the ORG input. ST93C67
S
Table 1. Signal Names
ORG
S Chip Select Input
C Serial Clock
VSS Ground
ST93C66 ST93C66
ST93C67 ST93C67
S 1 8 VCC S 1 8 VCC
C 2 7 DU C 2 7 DU
D 3 6 ORG D 3 6 ORG
Q 4 5 VSS Q 4 5 VSS
AI01253B AI01254C
DESCRIPTION (cont’d) nected or left running after the start of a Write cycle)
and does not require an erase cycle prior to the
The memory is accessed by a set of instructions Write instruction. The Write instruction writes 8 or
which includes Read a byte/word, Write a 16 bits at one time into one of the 512 bytes or 256
byte/word, Erase a byte/word, Erase All and Write words. After the start of the programming cycle, a
All. A Read instruction loads the address of the first Busy/Ready signal is available on the Data output
byte/word to be read into an internal address (Q) when Chip Select (S) is driven High.
pointer. The data contained at this address is then
clocked out serially. The address pointer is auto- The design of the ST93C66 and the High Endur-
matically incremented after the data is output and, ance CMOS technologyused for its fabrication give
if the Chip Select input (S) is held High, the an Erase/Write cycle Endurance of 1,000,000 cy-
ST93C66 can output a sequential stream of data cles and a data retention of 40 years.
bytes/words. In this way, the memory can be read The DU (Don’t Use) pin does not affect the function
as a data stream from 8 to 4096 bits long, or of the memory and it is reserved for use by SGS-
continuously as the address counter automatically THOMSON during test sequences.The pin may be
rolls over to ’00’ when the highest address is left unconnected or may be connected to VCC or
reached. Programming is internally self-timed (the VSS. Direct connection of DU to VSS is recom-
external clock signal on C input may be discon- mended for the lowest standby power consump-
tion.
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ST93C66, ST93C67
Table 4. DC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V or 3V to 5.5V)
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±2.5 µA
0V ≤ VOUT ≤ VCC,
ILO Output Leakage Current ±2.5 µA
Q in Hi-Z
Supply Current (TTL Inputs) S = VIH, f = 1 MHz 3 mA
ICC
Supply Current (CMOS Inputs) S = VIH, f = 1 MHz 2 mA
S = VSS, C = VSS,
ICC1 Supply Current (Standby) 50 µA
ORG = VSS or VCC
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ST93C66, ST93C67
Table 5. AC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V or 3V to 5.5V)
Symbol Alt Parameter Test Condition Min Max Unit
tSHCH tCSS Chip Select High to Clock High 50 ns
tCLSH tSKS Clock Low to Chip Select High 100 ns
tDVCH tDIS Input Valid to Clock High 100 ns
tCLSH tCHCL
tSHCH tCLCH
tDVCH tCHDX
AI01428
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ST93C66, ST93C67
tCLSL
D An A0
tCHQL tSLQZ
Hi-Z
Q Q15/Q7 Q0
AI00820C
tSLCH
tCLSL
D An A0/D0
tSHQV tSLQZ
Hi-Z
Q BUSY READY
tW
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ST93C66, ST93C67
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ST93C66, ST93C67
READ S
D 1 1 0 An A0
Q Qn Q0
WRITE S
CHECK
STATUS
D 1 0 1 An A0 Dn D0
ERASE S ERASE S
WRITE WRITE
ENABLE DISABLE
D 1 0 0 1 1 Xn X0 D 1 0 0 0 0 Xn X0
OP OP
CODE CODE
AI00878C
When the write cycle is completed, the Ready running after the start of a programming cycle) and
signal (Q = 1) will indicate (if S is driven high) that does not require an Erase instruction prior to the
the ST93C66 is ready to receive a new instruction. Write instruction (The Write instruction includes an
Programming is internally self-timed (the external automatic erase cycle before programing data).
clock signal on C input may be disconnected or left
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ST93C66, ST93C67
ERASE S
CHECK
STATUS
D 1 1 1 An A0
ERASE S
ALL
CHECK
STATUS
D 1 0 0 1 0 Xn X0
WRITE S
ALL
CHECK
STATUS
D 1 0 0 0 1 Xn X0 Dn D0
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ST93C66, ST93C67
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ST93C66, ST93C67
An An-1 An-2
Example: ST93C66 CM 3 TR
Devices are shipped from the factory with the memory content set at all ”1’s” (FFFFh for x16, FFh for x8).
For a list of available options (Operating Voltage, Package, etc...) or for further information on any aspect
of this device, please contact the SGS-THOMSON Sales Office nearest to you.
10/13
ST93C66, ST93C67
mm inches
Symb
Typ Min Max Typ Min Max
A 4.80 0.189
A1 0.70 – 0.028 –
A2 3.10 3.60 0.122 0.142
B 0.38 0.58 0.015 0.023
B1 1.15 1.65 0.045 0.065
C 0.38 0.52 0.015 0.020
D 9.20 9.90 0.362 0.390
E 7.62 – – 0.300 – –
E1 6.30 7.10 0.248 0.280
e1 2.54 – – 0.100 – –
eA 8.40 – 0.331 –
eB 9.20 0.362
L 3.00 3.80 0.118 0.150
N 8 8
CP 0.10 0.004
PSDIP8
A2 A
A1 L
B e1 C
B1 eA
D eB
E1 E
1
PSDIP-a
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ST93C66, ST93C67
mm inches
Symb
Typ Min Max Typ Min Max
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
E 3.80 4.00 0.150 0.157
e 1.27 – – 0.050 – –
N 8 8
CP 0.10 0.004
SO8
h x 45°
A
C
B
e CP
E H
1
A1 α L
SO-a
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ST93C66, ST93C67
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
13/13