QUESTION BANK WITH ANSWER

Digital Design and Computer Organization

1. Write the HDL code for Two-to-Four-Line Decoder using gate-level and data flow
modelling method.

2. Write the code using behavioral Model for Two-to-one and Four-to-One Line Multiplexer.

3. Write an 8:3 priority encoder giving highest priority for I 7 and generate the code using
behavioral model and dataflow model.
 module priorityencoder(en,i,y);
input en;
input [7:0]i;
output reg [2:0]y;
always @(en,i)
begin
if(en==1)
begin
if(i[7]==1) y=3'b111;
else if(i[6]==1) y=3'b110;
else if(i[5]==1) y=3'b101;
else if(i[4]==1) y=3'b100;
else if(i[3]==1) y=3'b011;
else if(i[2]==1) y=3'b010;
else if(i[1]==1) y=3'b001;
else
y=3'b000;
end
endmodule
4. Write the Ripple-Carry Adder code using gate level model.
5. Design a combinational circuit with three inputs, x , y , and z , and three outputs, A, B , and
C.When the binary input is 0, 1, 2, or 3, the binary output is one greater than the input.
When the binary input is 4, 5, 6, or 7, the binary output is two less than the input. Write a
Verilog code using data-flow model and gate level model of the circuit.
module ckt (x,y,z,a,b,c);
output a,b,c:
input x,y,z;
assign a= (x & y)| (x & y & z);
assign b= (!y &z)|(x & !y)|( !x & y & !z);
assign c= (c & z)|(!x & !z);
endmodule

6. Difference between sequential and combinational circuits

7. Differentiate between synchronous sequential circuit and asynchronous sequential circuit.
8. Differentiate between latch and flip flop.

9. Explain the fundamental storage mechanism utilized in SR latches using NOR Gates and
NAND gates.

Storage elements that operate with signal levels (rather than signal transitions) are
referred to as latches. Latches are said to be level sensitive devices.

The SR latch is a circuit with two cross-coupled NOR gates or two cross-coupled NAND gates,
and two inputs labelled S for set and R for reset. When output Q = 1 and Q’= 0, the latch is said
to be in the set state . When Q = 0 and Q’= 1, it is in the reset state . Outputs Q and Q_ are
normally the complement of each other. However, when both inputs are equal to 1 at the same
time, a condition in which both outputs are equal to 0 (rather than be mutually complementary)
occurs. If both inputs are then switched to 0 simultaneously, the device will enter an
unpredictable.

From the diagram it is evident that the latches have mainly four states. They are

Case 1:

S=1, R=0—Q=1, Q’=0 This state is also called the SET state.

Case 2:

S=0, R=1—Q=0, Q’=1 This state is known as the RESET state.

In both the states the outputs are just compliments of each other and that the value of Q follows
the value of S.

Case 3:

S=0, R=0—Q & Q’ = Remember If both the values of S and R are switched to 0, then the circuit
remembers the value of S and R in their previous state.

Case 4:

S=1, R=1—Q=0, Q’=0 [Invalid] This is an invalid state because the values of both Q and Q’ are
0. They are supposed to be compliments of each other. Normally, this state must be avoided.

The SR latch with two cross-coupled NAND gates operates with both inputs normally at 1,
unless the state of the latch has to be changed. The application of 0 to the S input causes output
Q to go to 1, putting the latch in the set state. When the S input goes back to 1, the circuit
remains in the set state. After both inputs go back to 1, we are allowed to change the state of the
latch by placing a 0 in the R input. This action causes the circuit to go to the reset state and stay
there even after both inputs return to 1. The condition that is forbidden for the NAND latch is
both inputs being equal to 0 at the same time, an input combination that should be avoided.

Case 1:
S=1, R=0—Q=0, Q’=1
This state is also called the SET state.
Case 2:
S=0, R=1—Q=1, Q’=0 This state is known as the RESET state.
In both the states the outputs are just compliments of each other and that the value of Q follows
the compliment value of S.
Case 3:
S=0, R=0—Q=1, & Q’ =1 [Invalid] If both the values of S and R are switched to 0 it is an
invalid state because the values of both Q and Q’ are 1. They are supposed to be compliments of
each other. Normally, this state must be avoided.
Case 4:
S=1, R=1—Q & Q’= Remember If both the values of S and R are switched to 1, then the circuit
remembers the value of S and R in their previous state.
In comparing the NAND with the NOR latch, note that the input signals for the NAND require
the complement of those values used for the NOR latch. Because the NAND latch requires a 0
signal to change its state, it is sometimes referred to as an S’R’ latch.

10. Explain the construction of a JK flip-flop using a D flip-flop and gates. write the
characteristic table of a JK flip-flop and D flip-flop.

There are three operations that can be performed with a flip-flop: Set it to 1, reset it to 0, or
complement its output. With only a single input, the D flip-flop can set or reset the output,
depending on the value of the D input immediately before the clock transition.
Synchronized by a clock signal, the JK flip-flop has two inputs and performs all three operations.
The circuit diagram of a JK flip-flop constructed with a D flip-flop and gates is shown in Fig.
The J input sets the flip-flop to 1, the K input resets it to 0, and when both inputs are enabled, the
output is complemented. This can be verified by investigating the circuit applied to the D input:

D = JQ’ + K’Q
When J = 1 and K = 0, D = Q’+ Q = 1, so the next clock edge sets the output to 1.
When J = 0 and K = 1, D = 0, so the next clock edge resets the output to 0.
When both J = K = 1 and D = Q’, the next clock edge complements the output.
When both J = K = 0 and D = Q, the clock edge leaves the output unchanged.

A characteristic table defines the logical properties of a flip-flop by describing its operation in
tabular form.
They define the next state as a function of the inputs and the present state. Q ( t ) refers to the
present state Q(t + 1) is the next state.
The characteristic table for the JK flip-flop shows that the next state is equal to the present state
when inputs J and K are both equal to 0. This condition can be expressed as Q(t + 1) = Q(t),
indicating that the clock produces no change of state. When K = 1 and J = 0, the clock resets the
flip-flop and Q(t + 1) = 0. With J = 1 and K = 0, the flip-flop sets and Q(t + 1) = 1. When both J
and K are equal to 1, the next state changes to the complement of the present state, a transition
that can be expressed as Q(t + 1) = Q’ (t).
The next state of a D flip-flop is dependent only on the D input and is independent of the present
state. This can be expressed as Q(t + 1) = D. It means that the next-state value is equal to the
value of D. Note that the D flip-flop does not have a “no-change” condition.

11. Explain Master Slave D Flip-Flop.

The construction of a D flip-flop with two D latches and an inverter. The first latch is called the
master and the second the slave. The circuit samples the D input and changes its output Q only at
the negative edge of the synchronizing or controlling clock (designated as Clk ). When the clock
is 0, the output of the inverter is 1. The slave latch is enabled, and its output Q is equal to the
master output Y. The master latch is disabled because Clk = 0. When the input pulse changes to
the logic-1 level, the data from the external D input are transferred to the master. The slave,
however, is disabled as long as the clock remains at the 1 level, because it enables input is equal
to 0. Any change in the input changes the master output at Y, but cannot affect the slave output.
When the clock pulse returns to 0, the master is disabled and is isolated from the D input. At the
same time, the slave is enabled and the value of Y is transferred to the output of the flip-flop at
Q. Thus, a change in the output of the flip-flop can be triggered only by and during the transition
of the clock from 1 to 0.

The behavior of the master–slave flip-flop just described dictates that (1) the output may change
only once, (2) a change in the output is triggered by the negative edge of the clock, and (3) the
change may occur only during the clock’s negative level. The value that is produced at the output
of the flip-flop is the value that was stored in the master stage immediately before the negative
edge occurred . It is also possible to design the circuit so that the flip-flop output changes on the
positive edge of the clock. This happens in a flip-flop that has an additional inverter between the
Clk terminal and the junction between the other inverter and input En of the master latch. Such a
flip-flop is triggered with a negative pulse, so that the negative edge of the clock affects the
master
and the positive edge affects the slave and the output terminal.

12. Define performance measurement. Discuss the basic performance equation.

The performance measure is the time taken by the computer to execute a given bench mark.
A non-profit organization called SPEC- system performance evaluation corporation selects and
publishes bench marks.
The ‘SPEC’ rating is computed as follows

If the SPEC rating = 50

Means that the computer under test is 50 times as fast as the ultra sparc 10. This is repeated for
all the programs in the SPEC suit, and the geometric mean of the result is computed.
Let SPECi be the rating for program ‘i’ in the suite. The overall SPEC rating for the computer is
given by
Since actual execution time is measured the SPEC rating is a measure of the combined effect of
all factors affecting performance, including the compiler, the OS, the processor, the memory of
comp being tested.
Performance equation
Let
T=processor time required to execute a program
N=actual number of instruction executions
S=average number of basic steps needed to execute one machine instruction
R=clock rate in cycles per second
• The program execution time is given by

-----(1)
• Equ1 is referred to as the basic performance equation.
• To achieve high performance, the computer designer must reduce the value of T, which means
reducing N and S, and increasing R.
→ The value of N is reduced if source program is compiled into fewer machine instructions.
→ The value of S is reduced if instructions have a smaller number of basic steps to perform.
→ The value of R can be increased by using a higher frequency clock.

13. Define Bus. Show the structure with diagram

The simplest and most common way of interconnecting various parts of the computer. To achieve
a reasonable speed of operation, a computer must be organized so that all its units can handle one
full word of data at a given time. A group of lines that serve as a connecting port for several
devices is called a bus. In addition to the lines that carry the data, the bus must have lines for
address and control purpose. Simplest way to interconnect is to use the single bus as shown
Since the bus can be used for only one transfer at a time, only two units can actively use the bus at
any given time. Bus control lines are used to arbitrate multiple requests for use of one bus.
Single bus structure is
 Low cost
 Very flexible for attaching peripheral devices
Multiple bus structure certainly increases, the performance but also increases the cost significantly.
All the interconnected devices are not of same speed & time, leads to a bit of a problem. This is
solved by using cache registers (ie buffer registers). These buffers are electronic registers of small
capacity when compared to the main memory but of comparable speed.
The instructions from the processor at once are loaded into these buffers and then the complete
transfer of data at a fast rate will take place.

14. Demonstrate instruction execution and straight-line sequencing for C [A] + [B]

• C=A+B; This statement is a command to the computer to add the current values of the two
variables A and B, and to assign the sum to a third variable C.
• When the program is compiled, each variable is assigned a distinct address in memory.
• The contents of these locations represent the values of the three variables
• The statement C<-[A]+[B] indicates that the contents of memory locations A and B are fetched
from memory, transferred to the processor, sum is computed and then result is stored in memory
location C.
Three-Address Instruction
• The instruction has general format
Operation Source1, Source2, Destination
• For example, Add A, B, C; operands A and B are called the source operands, C is called the
destination operand, and Add is the operation to be performed.
Two-Address Instruction
• The instruction has general format
Operation Source, Destination
• For example, Add A, B; performs the operation B<-[A]+[B].
• When the sum is calculated, the result is sent to the memory and stored in location B, replacing
the original contents of this location. This means that operand B is both a source and a destination.
• The operation C<-[A]+[B] can be performed by the two-instruction sequence
Move B, C
Add A, C
One-Address Instruction
• The instruction has general format
Operation Source/Destination
• For example, Add A ; Add the contents of memory location A to the contents of the
accumulator register and place the sum back into the accumulator.
• Load A; This instruction copies the contents of memory location A into the accumulator and
Store A; This instruction copies the contents of the accumulator into memory location A.
The operation C<-[A]+[B] can be performed by executing the sequence of instructions
Load A
Add B
Store C
• The operand may be a source or a destination depending on the instruction. In the Load
instruction, address A specifies the source operand, and the destination location, the accumulator,
is implied. On the other hand, C denotes the destination location in the Store instruction, whereas
the source, the accumulator, is implied.
15. With a memory layout starting at address ‘i’ represent how ‘ABCD’ data is stored in Big -
Endian and Little-Endian assignment scheme in a system of word length 32 bits.

There are two ways that byte addresses can be assigned across words, as shown in fig b. The name big-
endian is used when lower byte addresses are used for the more significant bytes (the leftmost bytes) of
the word. The name little-endian is used for the opposite ordering, where the lower byte addresses are
used for the less significant bytes (the rightmost bytes) of the word. In addition to specifying the address
ordering of bytes within a word, it is also necessary to specify the labeling of bits within a byte or a word.
The same ordering is also used for labeling bits within a byte, that is, b7, b6, …., b0, from left to right.

16. Define an addressing mode and conditional codes. List and explain them in detail.

Programs are normally written in a high-level language, which enables the programmer to use
constants, local and global variables, pointers, and arrays. The different ways in which the location
of an operand is specified in an instruction are referred to as addressing modes.
Register mode - The operand is the contents of a processor register; the name (address) of the
register is given in the instruction.
Absolute mode – The operand is in a memory location; the address of this location is given
explicitly in the instruction.
The instruction
Move LOC, R2
Processor registers are used as temporary storage locations where the data is a register are accessed
using the Register mode. The Absolute mode can represent global variables in a program. A
declaration such as
Integer A, B;
Immediate mode – The operand is given explicitly in the instruction.
A common convention is to use the sharp sign (#) in front of the value to indicate that this value is
to be used as an immediate operand. Hence, we write the instruction above in the form
Move #200, R0
Indirect mode – The effective address of the operand is the contents of a register or memory
location whose address appears in the instruction.
Index mode – the effective address of the operand is generated by adding a constant value to the
contents of a register.
The register use may be either a special register provided for this purpose, or, more commonly, it
may be any one of a set of general-purpose registers in the processor. In either case, it is referred to
as index register. We indicate the Index mode symbolically as
X (Ri)
Where X denotes the constant value contained in the instruction and Ri is the name of the register
involved. The effective address of the operand is given by
EA = X + [Rj]
Relative mode – The effective address is determined by the Index mode using the program counter
in place of the general-purpose register Ri.
This mode can be used to access data operands. But, its most common use is to specify the target
address in branch instructions. An instruction such as
Branch > 0 LOOP
Causes program execution to go to the branch target location identified by the name LOOP if the
branch condition is satisfied. This location can be computed by specifying it as an offset from the
current value of the program counter. Since the branch target may be either before or after the
branch instruction, the offset is given as a signed number.
Autoincrement mode – the effective address of the operand is the contents of a register specified in
the instruction. After accessing the operand, the contents of this register are automatically to point
to the next item in a list.
(Ri)+
Autodecrement mode – the contents of a register specified in the instruction are first automatically
decremented and are then used as the effective address of the operand.
-(Ri)
conditional codes
The processor keeps track of information about the results of various operations for use by
subsequent conditional branch instructions. This is accomplished by recording the required
information in individual bits, often called condition code flags. These flags are usually grouped
together in a special processor register called the condition code register or status register.
Individual condition code flags are set to 1 or cleared to 0, depending on the outcome of the
operation performed.
Four commonly used flags are
N(negative) Set to 1 if the result is negative; otherwise, cleared to 0
Z(zero) Set to 1 if the result is 0; otherwise, cleared to 0
V(overflow) Set ot1 if arithmetic overflow occurs; otherwise, cleared to 0
C(carry) Set to 1 if a carry-out results from the operation; otherwise, cleared to 0
The instruction Branch > 0, discussed in the previous section, is an example of a branch instruction
that tests one or more of the condition flags. It causes a branch if the value tested is neither
negative nor equal to zero. That is, the branch is taken if neither N nor Z is 1. The conditions are
given as logic expressions involving the condition code flags.

17. Explain the concept of communication between memory and processor with the respective
registers.
• The processor contains ALU, control-circuitry and many registers.
• The instruction-register(IR) holds the instruction that is currently being executed.
• The instruction is then passed to the control-unit, which generates the timing-signals that determine
when a given action is to take place
• The PC(Program Counter) contains the memory-address of the next-instruction to be fetched &
executed.
• During the execution of an instruction, the contents of PC are updated to point to next instruction. • The
processor also contains „n‟ general-purpose registers R0 through Rn-1.
• The MAR (Memory Address Register) holds the address of the memory-location to be accessed.
• The MDR (Memory Data Register) contains the data to be written into or read out of the addressed
location. Following are the steps that take place to execute an instruction
• The address of first instruction(to be executed) gets loaded into PC.
• The contents of PC(i.e. address) are transferred to the MAR & control-unit issues Read signal to
memory. • After certain amount of elapsed time, the first instruction is read out of memory and placed
into MDR. • Next, the contents of MDR are transferred to IR. At this point, the instruction can be decoded
& executed.
• To fetch an operand, it's address is placed into MAR & control-unit issues Read signal. As a result, the
operand is transferred from memory into MDR, and then it is transferred from MDR to ALU.
• Likewise required number of operands is fetched into processor.
• Finally, ALU performs the desired operation.
• If the result of this operation is to be stored in the memory, then the result is sent to the MDR.
• The address of the location where the result is to be stored is sent to the MAR and a Write cycle is
initiated.
• At some point during execution, contents of PC are incremented to point to next instruction in the
program. [The instruction is a combination of opcode and operand].