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U8 Emif02 Usb03f2

The EMIF02-USB03F2 is a highly integrated 2-line EMI filter and ESD protection device for USB ports. It provides high efficiency EMI filtering and ESD suppression up to 15kV, while occupying very low PCB space of less than 2.80mm2. Key features include integrated low-pass filtering, ESD protection up to IEC 61000-4-2 level 4, and reliability through monolithic integration in a thin flip-chip package.

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0% found this document useful (0 votes)
34 views8 pages

U8 Emif02 Usb03f2

The EMIF02-USB03F2 is a highly integrated 2-line EMI filter and ESD protection device for USB ports. It provides high efficiency EMI filtering and ESD suppression up to 15kV, while occupying very low PCB space of less than 2.80mm2. Key features include integrated low-pass filtering, ESD protection up to IEC 61000-4-2 level 4, and reliability through monolithic integration in a thin flip-chip package.

Uploaded by

haystackmuddy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 8

EMIF02-USB03F2

2-line IPAD™, EMI filter including ESD protection

Features
■ 2-line, low-pass filter + 2-line ESD protection
■ High efficiency in EMI filtering
■ Lead-free package
■ Very low PCB space occupation: < 2.80 mm2
Flip Chip
■ Very thin package: 0.65 mm (11 bumps)
■ High efficiency in ESD suppression
(IEC 61000-4-2 level 4)
■ High reliability offered by monolithic integration Figure 1. Pin layout (bump side)
■ High reduction of parasitic elements through 3 2 1
integration and wafer level packaging
ID Dz A
Complies with the following standards
■ IEC 61000-4-2 level 4 on external pins:
Vbus Pup Pd1 B
– 15 kV (air discharge) D+ D+
out Pd2 in C
– 8 kV (contact discharge)
■ IEC 61000-4-2 level 1 on internal pins: D-
out GND D-
in D
– 2 kV (air discharge)
– 2 kV (contact discharge)
Figure 2. Schematic
Application Pup Dz ID Vbus

EMIF02-USB03F2
R3=1.3kΩ
ESD protection and EMI filtering for: D+OUT R2=33Ω D+IN

■ USB OTG port D-OUT R1=33Ω D-IN

R5=15kΩ R4=17kΩ

Description Pd2

Pd1
The EMIF02-USB03F2 is a highly integrated array
CLINE = 20 pF max.
designed to suppress EMI / RFI noise for USB
OTG (on-the-go) ports.
The EMIF02-USB03F2 Flip-Chip packaging
means the package size is equal to the die size.
Additionally, this filter includes ESD protection
circuitry which prevents damage to the protected
device when subjected to ESD surges up to 15 kV
on external contacts.

TM: IPAD is a trademark of STMicroelectronics.

February 2010 Doc ID 10740 Rev 5 1/8


www.st.com 8
Characteristics EMIF02-USB03F2

1 Characteristics

Table 1. Absolute ratings (Tamb = 25 °C)


Symbol Parameter and test conditions Value Unit

Internal pins (D3, C3, C2, B2, B1):


ESD discharge IEC61000-4-2, air discharge 2
ESD discharge IEC61000-4-2, contact discharge 2
VPP kV
External pins (D1, C1, A2, A3, B3):
ESD discharge IEC61000-4-2, air discharge 15
ESD discharge IEC61000-4-2, contact discharge 8

Tj Maximum junction temperature 125 °C

Top Operating temperature range -40 to +85 °C

Tstg Storage temperature range -55 to 150 °C

Table 2. Electrical characteristics (Tamb = 25 °C)


Symbol Parameters

VBR Breakdown voltage


IRM Leakage current @ VRM
VRM Stand-off voltage
VCL Clamping voltage
Rd Dynamic impedance
IPP Peak pulse current

CLINE Input capacitance per line

Symbol Test conditions Min Typ Max Unit

VBR IR = 1 mA 14 V

IRM VRM = 3 V 0.2 µA

VLINE = 0 V, VOSC = 30 mV, F = 1 MHz,


CLINE 20 pF
measured in zero light condition

R1, R2 Tolerance ± 5 % 33 Ω

R3 Tolerance ± 5 % 1.30 kΩ

R4 Tolerance ± 5 % 17 kΩ

R5 Tolerance ± 5 % 15 kΩ

2/8 Doc ID 10740 Rev 5


EMIF02-USB03F2 Characteristics

Figure 3. Filtering measurement Figure 4. Analog crosstalk measurement


0 dB 0 dB
-10
-20
-10 -30
-40
-50
-60
-20 -70
-80
-90
-30 -100
-110
F (Hz) -120 F (Hz)
-40 -130
100k 1M 10M 100M 1G 100k 1M 10M 100M 1G
D+In D+Out D-In D-Out D-In D+Out DZ ID

Figure 5. ESD response to IEC 61000-4-2 Figure 6. ESD response to IEC 61000-4-2
(+15 kV air discharge) on one input (-15 kV air discharge) on one input
Vin and on one output Vout Vin and on one output Vout

10.0 V / Div.
20.0 V / Div. IN
VCL = 74 V

IN VCL = -47 V
100 ns / Div. 100 ns / Div.
10.0 V / Div. 10.0 V / Div.
OUT
VCL = 27 V
OUT
VCL = -23 V
100 ns / Div. 100 ns / Div.

Figure 7. Junction capacitance versus reverse voltage applied (typical values)


C(pF)
20
18
16
14
12
10
8
6
4
2 VLINE (V)
0
0 1 2 3 4 5 6 7 8 9 10 11 12

Doc ID 10740 Rev 5 3/8


Application information EMIF02-USB03F2

2 Application information

Figure 8. Application schematic


Vbus Vbus
3.3V ID

USB OTG connector


ID

Pup Dz ID Vbus

EMIF02-USB03F2

USB OTG Xceiver


R3=1.3kΩ

D+OUT R2=33Ω D+IN


D+ D+
D-OUT R1=33Ω D-IN
D- D-

R5=15kΩ R4=17kΩ

GND GND
Pd2

Pd1

R1 = R2 = 33 Ω
Cline = 20 pF max.

Figure 9. Aplac model


C3 C1
Ls Rs Lbump Rbump Rbump Lbump Rs Ls
Port1 Port2
50 50

A3 A2 B3 B2 B1 C2 D2

MODEL = D02_usb03_gnd
MODEL = D02_usb03

bulk bulk bulk bulk bulk bulk bulk


B2 B1 C2 D2

R_1k3 R_17k
R_15k
Lbump
C3 R_33R C1 D3 R_33R D1

Rbump

MODEL = D02_usb03 MODEL = D02_usb03


Cgnd
Lgnd
bulk bulk bulk bulk

Cbump Rsubump Cbump Rsubump Rgnd

A2 bulk B1 bulk

Cbump Rsubump Cbump Rsubump


B2 bulk C1 bulk

Cbump Rsubump Cbump Rsubump


C2 bulk D3 bulk

Cbump Rsubump Cbump Rsubump


C3 bulk D1 bulk

Cbump Rsubump Cbump Rsubump


B3 bulk A3 bulk

Figure 10. Aplac parameters


Ls 950pH Rs_usb03_gnd 0.9
Rs 150m Lgnd 50pH
R_33R 33 Rgnd 100m
R_1k3 1.3k Cgnd 0.15pF
R_15k 15k Lbump 50pH
R_17k 17k Rbump 20m
Cz_usb03 11pF Cbump 2.4pF
Rs_usb03 1 Rsubump 100m
Cz_usb03_gnd 220pF

4/8 Doc ID 10740 Rev 5


EMIF02-USB03F2 Ordering information scheme

3 Ordering information scheme

Figure 11. Ordering information scheme


EMIF yy - xxx zz Fx

EMI Filter

Number of lines

Information
x = resistance value (ohm)
z = capacitance value / 10 (pF)
or
3 letters = application
2 digits = version

Package
F = Flip Chip
x = 2: lead-free, pitch = 500 µm, bump = 315 µm

4 Package information

In order to meet environmental requirements, ST offers these devices in different grades of


ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

Figure 12. Package dimensions


315 µm ± 50 650 µm ± 65
500 µm
1.94 mm ± 30 µm
500 µm

220 µm
220 µm

1.44 mm ± 30 µm

Doc ID 10740 Rev 5 5/8


Ordering information EMIF02-USB03F2

Figure 13. Footprint Figure 14. Marking


Dot, ST logo
ECOPACK status
Copper pad Diameter: xx = marking
250 µm recommended, 300 µm max. z = manufacturing location
yww = datecode
(y = year
Solder stencil opening: ww = week)
330 µm recommended
x x z
Solder mask opening recommendation: y ww
340 µm min. for 300 µm copper pad diameter

Figure 15. Flip Chip tape and reel specification


Dot identifying Pin A1 location
Ø 1.5 ± 0.1
4 ± 0.1

1.75 ± 0.1
3.5 ± 0.1
2.04
8 ± 0.3

1.58
ST E

ST E

ST E
yww

yww

yww
xxz

xxz

xxz
0.73 ± 0.05 4 ± 0.1

User direction of unreeling


All dimensions in mm

Note: More information is available in the application notes:


AN1235:"Flip Chip: Package description and recommendations for use"
AN1751: “EMI filters: Recommendations and measurements”

5 Ordering information

Table 3. Ordering information


Order code Marking Package Weight Base qty Delivery mode

EMIF02-USB03F2 FU Flip Chip 4 mg 5000 Tape and reel 7”

6/8 Doc ID 10740 Rev 5


EMIF02-USB03F2 Revision history

6 Revision history

Table 4. Document revision history


Date Revision Changes

14-Oct-2004 1 Initial release.


25-Oct-2004 2 Figure 14.: Flip Chip marking dimensions updated.
27-Oct-2004 3 Minor layout update. No content change.
Updated ECOPACK statement. Updated Figure 11, Figure 12, Figure 13,
28-Apr-2008 4
Figure 14 and Figure 15. Reformatted to current standards.
Updated the maximum value of IRM in Table 2. Updated Figure 12 and
08-Feb-2010 5
Figure 15 for die dimension reductions.

Doc ID 10740 Rev 5 7/8


EMIF02-USB03F2

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right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
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Information in this document supersedes and replaces all information previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

© 2010 STMicroelectronics - All rights reserved

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www.st.com

8/8 Doc ID 10740 Rev 5

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