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Charge pump with perfect current matching characteristics in phase-locked

loops

Article in Electronics Letters · December 2000

DOI: 10.1049/el:20001358 · Source: IEEE Xplore

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Charge pump with perfect current matching ence between the drain-source voltage of the PMOS and NMOS
characteristics in phase-locked loops FETs. The current mismatch of the charge pump in the PLLs gen-
erates a phase offset which increases spurs in the RLL output sig-
nals. Also, the phase offset reduces the locking range in the wide
Jae-Shin Lee, Min-Sun Keel, Shin-I1 Lim a n d Suki Kim range PLL with the dual loop scheme frequency locking loop and
Conventional CMOS charge pump circuits have some current phase locking loop, especially. When the current rnismatch occurs
mismatching characteristics. The current mismatch of the charge in the charge pump, the amount of the phase offset is given by
pump in the PLLs generates a phase offset, which increases spurs
in the PLL output signals. In particular, it reduces the locking
range in wide range PLLs with a dual loop scheme. A new charge
pump circuit with perfect current matching characteristics is where @E, Aton, Tre3repand A; are the phase offset, the turn-on
proposed. By using an error amplifier and reference current time of the PED, the reference clock period, the charge pump cur-
sources, one can acheve a charge pump with good current rent and the current mismatch of the charge pump, respectively.
matching characteristics.It shows nearly perfect current matching
characteristics over the whole VCO input range, and the amount The amount of reference spur, P,,in the third order PLL is given
of the reference spur is < -75dBc in the PLL output signal. The approximately by
charge pump circuit is implemented in a 0 . 2 5 CMOS
~ process.

Introduction: A charge pump is widely used in modem phase-

locked loops (PLL) for a low cost IC solution. Having a neutral
state, an ideal charge pump combined with a phase/frequency where R is the resistor value in the loop filter, Kvco is the VCO
detector (PIFD) provides an infinite DC gain with passive filters, gain, fief is the reference frequency for the P E D and fpl is the fre-
which results in the unbounded pull-in range for second and quency of the pole in the loop filter [l]. As shown in eqn. 1, to
higher order PLLs if not limited by the voltage controlled oscilla- minimise the phase offset, one should reduce the tum-on time of
tor (VCO) input range [l]. As long as the P E D and the charge the P E D and the current mismatch. The turn-on time of the P/
pump are ideal, zero static phase error can be obtained. The FD, however, is needed a little to eliminate the dead-zone. So, we
charge pump, in general, shows nonideal characteristics when have to reduce the current mismatch as small as possible. In this
implemented in a circuit and its practical issues need to be consid- Letter we propose a new charge pump circuit with nearly perfect
ered in the design of the PLLs. One of the issues in the charge current matching characteristics as shown in Fig. 1. For the con-
pump design is the current mismatch. In this Letter we consider ventional charge pumps, by enlarging the output impedance of the
the effects of the phase offset caused by the current mismatch and current source, the sourcingkinking current matching is improved.
propose a new charge pump circuit with nearly perfect current This method, however, cannot produce perfect current matching
matching characteristics. characteristics because of the sizable output impedance of the
VDD practical devices used in the circuit. In the proposed charge pump,
by using an error amplifer, the voltage V,, at the node REF of
up- ri
MI
-
the current mirror (M5 Ms) follows the voltage VcpouTat the
node CPOUT of the charge pump (M1 M4). As a result, the
M2 voltage V,, is equal to the voltage VcpouTas long as the ampli-
l l e fier maintains a high enough gain. For M5 = M1, M6 = M2, M7
c
= M3 and M8 = M4, if the DOWN and the UP signal are high,
1I’ 1 12 then I4 = I3 = I2, and if the DOWN and the UI’ signal are low,
‘I
REF then Z3 = I2 = 11. So we can make the sinking current 14 equal the
0 sourcing current Zl. In this way, one can achieve nearly perfect
VDD CPOUT sourcdsinking current matching characteristics regardless of the
charge pump output voltages.

p
J
Fig. 1 Proposed charge pump circuit

1.2, r
proposed
charge pump
-751 f , , , , , ,

-80
0 2 4 6 8 10 12 14 16 18 20
current mismatch, %
1010/31
Fig. 3 Reference spur against current mismatch
charge pump output voltage, V charge pump output voltage, V
a b Conditions: I, = l O O p A , f , - SMHz, Aton = 50ns, K ~ C =
O 200MHd
1010/21 V,&, = 16.5kfIz, R = 1.5k6-
Fig. 2 Charge pump current matching characteristic
sinking Fig. 2 shows the current variations against the output voltage
_ - - sourcing variations of the charge pump circuit. For the conventional charge
a Conventional charge pump pump, perfect current matching occurs only when the output volt-
b Proposed charge pump
age of the charge pump, that is the input voltage of the VCO, is
near the centre of the supply voltage. If the output voltage is near
Charge pwnp design: CMOS charge pumps usually have UP and the supply voltage or the ground, the sourcinghking current dif-
DOWN switches implemented with a PMOS FET and an NMOS ference is relatively large. For the proposed charge pump, the
FET, respectively. The conventional CMOS charge pump circuits sourcingkinking current matching is nearly perfect. For the same
have some current mismatching characteristics due to the differ- size of the transistors used in the circuit, the maThum difference
ELECTRONICS LETTERS 9th November 2000 Vol. 36 No. 23 1907
 of the sourcing/sinkingcurrent in the conventional charge pump is ing PWM is shown in Fig. 1. Because of the s;nilarity of the
> 13%, but the proposed charge pump has < 1% of that. Fig. 3 modulator waveforms between peak and average current mode
shows the amount of the reference spur against the variations of controls, the approach presented in 131 can be applied in discrete
the current mismatch. While the conventional charge pump has a time small signal modelling of average current mode control. The
maximum reference spur of -52dBc, the proposed charge pump has effect of a compensation network, however, should be considered.
a reference spur < -75dBc. Using the practical sampler model approach, the small signal
model structure of an average current mode control can be drawn
Conclusion: In this Letter we present a new charge pump with as in Fig. 2a. The different sampling instant of the two ideal sam-
nearly perfect current matching characteristics in phase-locked pler presented in this Figure can be unified with some manipula-
loops. The current mismatch in the charge pump generates the tions including modification of compensation network. Fig. 2b
phase offset which increases the spur in the PLL output signal and shows the resultant small signal model structure.
reduces the locking range in the wide range PLL. By using an
error amplifier and a reference current source, we can achieve a
charge pump which has nearly perfect current matching character-
istics and the reference spur < -75dBc. It is implemented in a
0 . 2 5 ~CMOS process and occupies an active area of 200 x
I I =
200pn.

0 IEE 2000 29 August 2000

Electronics Letters Online No: 20001358
DOI: 10.1049/el:200013.58 ......
_ ;...i
compensation
Jae-Shin Lee, Min-Sun Keel and Suki Kim (Department Electronics
of
Engineering, Korea University, Anam-Dong, Sungbuk-Gu, Seoul, Korea,
I network

136-701)
E-mail: jaeri@ulsil .korea.ac.kr lul
1245/11
Ts
Shin-I1 Lim (Department of Computer Engineering, Seokyeong
University, Jungleung-Dong, Sungbuk-Gu, Seoul, Korea, 136-704) Fig. 1 Circuit diagram of buck converter employing average current
mode control

References
1R H E E , ~ . :‘Design of high performance CMOS charge pumps in
phase locked loop’. Proc. IEEE Int. Symp. Circuits and Systems,
1999, Vol. 1, pp. 545-548
2 LEE, WON-HYO, CHO, JUN-DONG, and LEE, SUNG-DAE: ‘A high speed
and low power phase-frequency detector and charge pump. ,Proc. a
ASP-DAC ’99 Asia and South Pacific Design Automation Conf.,
1999, Vol. 1, pp. 269-212
3 VAN PAEMEL, M.: ‘Analysis of a charge pump PLL: New model’,
IEEE Trans. Commun., 1994, 427, pp. 2490-2498
4 HOWARD, P.A., and JONES, A.E.: ‘Improved charge pump phase
detector for digital phase-locked loop’. IEEE Colloquium
Analogue Signal Processing, 1994, pp. 2/1-2/8
I ’ I I.

Fig. 2 Model structure of average current mode control

a Two samplers operate at different sampling instants
Discrete time small signal modelling of b Two samplers operate at same sampling instant
average current mode control
The sampling instant of an ideal sampler placed on a duty cycle
Young-Seok Jung a n d Myung-Joong Y o u n generator is changed to that of the perturbed inductor current,
and the modification of a compensator gain should be considered.
A discrete time small signal modelling of an average current mode For the model structure shown in Fig. 2a, the output value qf a
control is derived using the practical sampler model approach. By compensator is varied during the time interval of t = (n + d)T,
the practical sampler model approach, the small signal model
structure can be simply defined. This model structure includes the and t = (n + 1)q. For a PI type compensation network, the varia-
two ideal samplers, which make it easy to obtain the discrete time tion can be expressed as
model. To verify the usefulness of the proposed model,
simulations and experiments are carried out.
where e^ denotes the error signal between the perturbed reference
Introduction: The average current mode control has been reported, and perturbed inductor currents. By assuming that the perturbed
and the superior characteristics over a peak current mode control quantities are small, the second term on the right-hand side of
such as good tracking performance of an average current, no slope eqn. 1 can be reduced to zero. To guarantee the equivalent condi-
compensation and noise immunity have been discussed [l]. In this tion of the perturbed inductor current at t = (n + 1)T, for the
control, the compensation network is presented in a current con- model structure shown in Fig. 2b, the compensation network
trol loop to use the average current as a controlled quantity. should be modified from eqn. 1 as follows:
Although the design insights cannot be provided, the discrete
time model is useful for understanding the behaviour of the power
converter. Because of the presence of a compensation network,
however, it is difficult to derive a discrete time small signal model where ki = kp + kiT,. Note that, by the unification of two sam-
of an average current mode using the conventional approach [2]. pling instants of a practical sampler model, the modification of a
Thus, it is shown, in this Letter, that the derivation of a discrete compensation network should be carried out according to the
time model of a current loop transfer function can be easily equivalent condition of the perturbed inductor current at t = (n +
achieved using the practical sampler model approach. 1)T’ for the model structure shown in Fig. 2b.

Basic structure of proposed model: The circuit diagram of an aver- Discrete time small signal model: From the small signal model
age current mode controlled buck converter which is composed of structure shown in Fig. 2b, the discrete time model can be
a power stage, a compensation network and a modulator employ- obtained. As an example, the buck converter is considered as a
1908 ELECTRONICS LETTERS 9th November 2000 Vol. 36 No. 23

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