DIGITAL CIRCUIT DESIGN

18B11EC215
Lecture 17
Reducing Decoders and Encoder

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 Outlines
▪ Reducing Decoders

▪ Examples

▪ Encoders

▪ Examples

▪ References

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 Reducing Decoders [1-3]
▪ Example:
F(a,b,c) = ∑ m(4,6,7)
▪ Using a 3×8 decoder (assuming 1-enable and active-high
outputs).
3x8 0
Dec 1
2
a S2 3
4
b S1
5 F
c S0 6
7
EN

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 Reducing Decoders [1-3]
▪ We have seen that a decoder may be constructed from smaller
decoders.
▪ Below are just some ways of constructing a 3×8 decoder.
(Explore other ways youself!)
❖ Using two 2×4 decoders with an inverter.
2x4
a Dec 0
b S1 1
c S0 2
E 3
a'

2x4
Dec 0
S1 1
S0 2
E 3
a

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 Reducing Decoders [1-3]
▪ Using two 2×4 decoders and a 1×2 decoder.

2x4
Dec 0
b S1 1
c S0 2
3
E
1x2
Dec a'
0
a S 1
E 2x4
Dec 0
1 S1 1
S0 2
3
E
a

Verify this circuit yourself!

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 Reducing Decoders [1-3]
▪ Using four 1×2 decoders and a 2×4 decoder.

1x2 0
c S Dec
1
E

1x2 0
c S Dec
1
0 E
2x4
a S1 1
Dec
b S0 2
E 3 1x2 0
c S Dec
1
1 E

1x2
c 0
S Dec
1
E
Verify this circuit yourself.
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 Reducing Decoders [1-3]
▪ Using smaller decoders, sometimes we may be able to save
some decoders.
▪ Example: F(a,b,c) = ∑ m(4,6,7)

0 Question: Do we really
2x4
b S1 1
Dec need this decoder for F?
c S0 2
E 3
1x2 0 a'
a S Dec
1
E
2x4 0
1 S1 Dec 1 F
S0 2
E 3
a

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 Reducing Decoders [1-3]
▪ So we can save a decoder.
1x2 0 0
a S Dec
1 b S1 2x4 1 F
E Dec
c S0 2
E 3
1

Similarly, we can save 2 small decoders below.

1x2 0
0 c S Dec
2x4 1
a S1 1 E
Dec
b S0 2 F
E 3
1x2
c 0
1 S Dec
1
E

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 Reducing Decoders [1-3]
▪ Second example: F(a,b,c) = ∑ m(0,1,2,3,7)

0
2x4 1
b S1 Question: Can we do
Dec 2
c S0
3 something about this?
E

1x2 0 0
a S 2x4
Dec 1 b S1 1
Dec 2 F
E c S0
3
1 E

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 Reducing Decoders [1-3]
▪ Second example: F(a, b, c) = ∑ m(0,1,2,3,7)
▪ Yes, we may remove the top 2×4 decoder, and connect the
appropriate output from the 1×2 decoder directly to the OR gate.

1x2 0 0
a S Dec 2x4 1
1 b S1 Dec 2
E c S0 F
3
E
1

Verify that this circuit is correct!

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 Reducing Decoders [1-3]
▪ Third example: F(a,b,c) = ∑ m(0,3,4,7)
We have the same pattern
of outputs from the 2
0
b S1
2x4
1 decoders (i.e. we take the
Dec
c S0 2 first and fourth outputs
E 3 from each decoder). Can
we do something about it?
1x2 0 0
a S Dec 2x4 F
1 b S1 1
E Dec
c S0 2
E 3
1

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 Reducing Decoders [1-3]
▪ Third example: F(a,b,c) = ∑ m(0,3,4,7)
▪ If we have the same pattern of outputs from 2 or more decoders
at the second level, we may keep one decoder, and use an OR
gate on the corresponding outputs from the first-level decoder.
Additional OR gate

1x2 0 0 F
a S Dec 2x4
1 b S1 1
E c Dec 2
S0
E 3
1

Verify that this circuit is correct!

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 Reducing Decoders [1-3]
▪ Third example: F (a,b,c) = ∑ m(0,3,4,7)
▪ Can we still simplify the circuit?
This may be eliminated. (why?)

1x2 0
a S Dec 2x4 0 F
1 b S1 Dec 1
E c S0 2
E 3
1
Because this is (a' + a) = 1

2x4 0 F
b S1 Dec 1
c S0 2
E 3

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 Reducing Decoders [1-3]
▪ Summary:
❖ If no outputs are needed from a 2nd-level decoder, just remove the
decoder.
❖ If all outputs are needed from a 2nd-level decoder, remove the decoder,
and connect the corresponding output from the 1st-level decoder to the
OR gate.
❖ If the set of outputs is the same for 2 or more decoders at the 2nd level,
keep one of the decoders and remove the rest. Add an OR gate to take
in the appropriate outputs from the 1st-level decoder.
▪ The above procedure may not guarantee a circuit that has the
least number of decoders.
▪ However, it is easy to follow. (To obtain the optimal circuit in
general, we need to play around with the inputs to the decoders,
which may be difficult.)
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 Reducing Decoders [1-3]
▪ Apply what you learned to verify the circuit below for this
function: F(a,b,c,d) = ∑ m(0,1,2,3,4,5,12,13)

0
2x4
a S1 Dec 1
b S0 2 0 F
2x4
E 3 c S1 Dec 1
d S0 2
1 E 3

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 Encoders [1-3]
▪ Encoding is the reverse of decoding.
▪ Given a set of input lines, where one has been selected, provide
a code corresponding to that line.
▪ Contains 2n (or fewer) input lines and n output lines.
▪ Implemented with OR gates.
▪ An example:
F0
D0
Select via F1 4-to-2
switches 2-bits
F2 Encoder code
D1
F3

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 Encoders [1-3]
▪ Truth table:

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 Encoders [1-3]
▪ With the help of K-map (and don’t care conditions), can obtain:
D0 = F1 + F3
D1 = F2 + F3
which correspond to circuit:

F0

F1
D0
Simple 4-to-2 encoder
F2
D1
F3

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 Encoders [1-3]
▪ Example: Octal-to-binary encoder.
❖ At any one time, only one input line has a value of 1.

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 Encoders [1-3]
▪ Example: Octal-to-binary encoder.
D0
D1
x = D4 + D5 + D6 + D7
D2
D3
D4 y = D2 + D3 + D6 + D7
D5
D6
D7
z = D1 + D3 + D5 + D7

8-to-3 encoder
Exercise: Can you design a 2n-to-n encoder without the K-map?

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 Priority Encoders
• Solves the ambiguities mentioned above.
• Multiple asserted inputs are allowed; one has
priority over all others.
• Separate indication of no asserted inputs.

* PJF - 21
 Example: 4-to-2 Priority Encoder
Truth Table

* PJF - 22
 4-to-2 Priority Encoder (cont.)
• The operation of the priority encoder is such
that:
• If two or more inputs are equal to 1 at the same
time, the input in the highest-numbered
position will take precedence.
• A valid output indicator, designated by V, is
set to 1 only when one or more inputs are
equal to 1. V = D3 + D2 + D1 + D0 by
inspection.

* PJF - 23
 Example: 4-to-2 Priority Encoder
K-Maps

* PJF - 24
 Example: 4-to-2 Priority Encoder
Logic Diagram

* PJF - 25
 8-to-3 Priority Encoder

* PJF - 26
 Demultiplexer
▪ Given an input line and a set of selection lines, the demultiplexer
will direct data from input to a selected output line.
▪ An example of a 1-to-4 demultiplexer:

Outputs

Y0 = D.S1'.S0'
Y1 = D.S1'.S0
Data D demux
Y2 = D.S1.S0'
Y3 = D.S1.S0

S1 S 0
select
 Demultiplexer

▪ The demultiplexer is actually identical to a decoder with

Y0 = D.S1'.S0'
2x4 Decoder
S1 Y1 = D.S1'.S0
S0 Y2 = D.S1.S0'
E Y3 = D.S1.S0

Exercise: Provide the truth table for above demultiplexer.

[2] R. P. Jain, “Modern Digital Electronics”, 4th Edition, Tata

[3] A. Anand Kumar, “Fundamentals of Digital Circuits”, PHI,

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