Lab D4 Pre-Lab Lab Work

(10 pts) (10 pts)

Counter Circuits

JK Flip Flop

The J-K flip-flop is the most versatile of the basic flip-flops. It has the input- following character
of the clocked D flip-flop but has two inputs, traditionally labelled J and K (from the initials of
the inventor – Jack Kilby).
▪ If J and K are different then the output Q takes the value of J at the next clock edge.
▪ If J and K are both LOW then no change occurs.
▪ If J and K are both HIGH at the clock edge then the output will toggle from one state
to the other. This toggle application finds extensive use in binary counters.
Counter Circuits

Asynchronous 3-bit Binary Counter

Up Counter
This type of counter circuit is based on frequency division. The output on QA to QC, which is
3 bits wide, is a binary count from 0 to 7 ( 000 to 111) for each clock pulse. The clock is
applied only to the first stage with the output of one flip- flop stage providing the clocking
signal for the next flip-flop stage. This type of counter is also known as an “up” or “forward”
counter (CTU). The three-bit asynchronous counter shown is typical and uses flip-flops in the
toggle mode. Asynchronous “Down” counters (CTD) are also available as shown below.

Down Counter
Binary 4-bit Synchronous Up Counter

The circuit above is of a simple 3-bit Up/Down synchronous counter using JK flip-flops
configured to operate as toggle or T-type flip-flops giving a maximum count of zero (000) to
seven (111) and back to zero again. Then the 3-Bit counter advances upward in sequence
(0,1,2,3,4,5,6,7) or downwards in reverse sequence (7,6,5,4,3,2,1,0).
Binary 4-bit Synchronous Down Counter

we can easily construct a 4-bit Synchronous Down Counter by connecting the AND gates to
the Q output of the flip-flops as shown to produce a waveform timing diagram the reverse of
the above. Here the counter starts with all of its outputs HIGH (1111) and it counts down on
the application of each clock pulse to zero, (0000) before repeating again.
Nowadays, both up and down counters are incorporated into single. Common chips available
are the 74HC190 4-bit BCD decade Up/Down counter, the 74F569 is a fully synchronous
Up/Down binary counter and the CMOS 4029 4-bit Synchronous Up/Down counter.
Goals
1. To be able to use JK flip flop IC.
2. To understand the mechanism of asynchronous and synchronous counters.
3. To be able to design a decade counter that count from 0 (0000) to 9 (1001).
4. To be able to display a number on a 7-segment display.
 Pre-Lab Assignments: Answer the questions regarding JK Flip Flop IC 7476.

254 flip
1. For IC 7476– how many JK flip flops are packed inside this IC package? ________ flop
2. What voltage level should be supplied to VCC of the IC?
________________________________________________________
5V

3. CLK is active low. What does it mean?

mstwis can inwirker mo
__________________________________________________________
4. What voltage level should be supply to pins J and K for logic ‘HIGH’ (1)?
__________________________________________________________
5V

5. How to set a function generator to generate TTL clock with 1-Hz frequency?
mon DCLOCK 10 Int frequency ide 1 He
__________________________________________________________
:

6. If logic ‘LOW’ is applied to PRESET pin, what happens to the output Q?

0 NW
__________________________________________________________
:
High
7. If logic ‘LOW’ is applied to CLEAR pin, what happens to the output Q?
writ preset n preset wo clear in no Ronni
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Answer the questions regarding an IC 7447 and a 7-segment display.

anwendres
8. What is the function of IC 7447? ___________________________
9. What must the input pins ‘DCBA’ and the output pins ‘abcdefg’ of the IC 7447 be to
show number ‘5’ on a 7-segments?
__________________________________________________________
D LOW
:

C HIGH
:
BILOW A HIGH

10. What does common anode mean?

anode Priorite on vireviunani sinluz-segment
__________________________________
common musa nin
11. Which pin number (1-10) is assigned for segment a-g?
 a b c d c f y
1011 00 8 8

110 1
32 !
0

00 1

i ge a
1

11

i
in 118 I i
g

18 000 110 1

Pre-Lab Design Task: Design an asynchronous decade counter (count 0 to 9)

using JK flip flop and other logic gate ICs as necessary. Use LEDs to display the output
status.

Question for discussion: How will you modify the above circuit to be able to
count from 0 to 12 (0000 to 1100).
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Experimental Procedure
3-bit Asynchronous Up Counters

1. Build the following circuit using J-K flip-flops (IC 7476). Connect all J, K, PRE , and
CLR pins to logic ‘1’.
2. Input 1-Hz TTL clock signal to the CLK pin of the first flip flop. Observe the
sequence of the output Q3, Q2, and Q1 from the LEDs. Record the result in TABLE 1.

TABLE 1
Input Output
Binary number
Sequence of clock Decimal number
C B A
0 0 0 0 ⑧

1 O O 1 I

2 I

3 0
8 1 3
4 1 8 0

5 1 E
6 o 6
7 i I 1 7

8 O ⑧ ⑧ O

9 08 I 1

3-bit Asynchronous Down Counters

3. Build the following circuit using J-K flip-flops (IC 7476). Connect all J, K, PRE , and
CLR pins to logic ‘1’.
4. Input 1-Hz TTL clock signal to the CLK pin of the first flip flop. Observe the
sequence of the output Q3, Q2, and Q1 from the LEDs. Record the result in TABLE 2.
 TABLE 2
Input Output
Binary number
Sequence of clock Decimal number
C B A
0 0 0 0 O

1 1 1 1 7
2 110 6

i
5

4
5
⑤
6 2

7 ⑧

8 8 O O I
9 1 1 1 7

3-bit Synchronous Up Counter (count 0-7):

5. Build the following circuit using J-K flip-flops (IC 7476) and AND gate (IC 7408).
Connect PRE , and CLR pins to logic ‘1’.
6. Input 1-Hz TTL clock signal to the CLK pin of the first flip flop. Observe the
sequence of the output Q3, Q2, and Q1 from the LEDs. Record the result in TABLE 3.

EXTRA QUESTION: What changes should be made to create a down counter from this
synchronous up counter? Explain.
di a residen an mine
 TABLE 3
Input Output
Binary number
Sequence of clock Decimal number
C B A
0 0 0 0 O

a
0

2
I
3 3

4
5 1 I
6 6

7 I 7

8 ⑧ ⑧
0
8
1
9 ⑧ 1

Decade Counter (count from 0 to 9)

7. Build the following circuit using decade counter IC (7490) and 7-segment decoder IC
(7447). Input clock signal to pin CLKA of 7490. Observe the 7-segment display. Record
the result in Table 4. Add LEDs to observe the status of the DCBA pins.

R 150
 Table 4
Input Output
Sequence of D C B A Decimal number
clock
0 L L L L 8

1 e h L It I

2 L L H L I

3 L L H H 3

4 L H L L 4

5 L H L H 5
6 H H 6
it
L

7 L H H 7

8 H L L L 8
9 H L L H 9
10 L L
↳ L O

What have you learnt from this lab session?

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so Asynchronus/synchronus count
up/down in 7-segment
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11W

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