Id210 Specs
Id210 Specs
Photonic Solutions Ltd Unit 2.2, Quantum Court, Research Avenue South,
HWU Research Park, Edinburgh, EH14 4AP, UK, Tel: +44 (0)131 664 8122
Email [email protected] Web www.photonicsolutions.co.uk
Dark count rate for a 1ns effective gate width in gated mode: 30
Disclaimer - The information and specification set forth in this document are subject to change at any time by ID Quantique without prior notice. Copyright© 2014 ID Quantique SA - All rights reserved -
ID210 v2014 07 10 - Specifications as of July 2014
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ID Quantique T +41 22 301 83 71 [email protected]
Geneva / Switzerland F +41 22 301 83 79 www.idquantique.com
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DC High / Free-running
DC Low / Disabled Internal
Threshold Mode Reset
Reset/Enable High Level Gate
Comp. Slope/Logic Gate
Reset/Enable R/E Reset/Enable Logic Buffer Output
Input Gate 50W
Relay Gate
50W
Pulse ID
Reset/Enable Mode Low Level
Reset
HF Counter Gate
Detection
Load
Reset
Internal
Reset
Polarization Pulse ID
Reset/Enable Mode System hardware Gate output block
Reset/Enable input block
Threshold
Aux1
Comp. Slope/Logic Pulse Shaping HF Counter
Aux1 Aux1 Aux1 Aux1 Aux1 High Level Detection 1
Input Relay Detection1
50W
Internal
Reset
Threshold
Aux2
Comp. Slope/Logic Pulse Shaping HF Counter Capture
Aux2 Aux2 Aux2 Aux2 Aux2 Electronics
Input Relay
50W
PRINCIPLE OF OPERATION
The ID210 Advanced System for Single Photon Detection is built around the following blocks:
¡
Trigger, Reset/Enable, Aux1 and Aux2 inputs blocks with SMA connectors on the ID210 front panel.
Through the ID210 user interface, each input can be set independently for receiving LVTTL-LVCMOS, NIM,
NECL, PECL3.3V or PECL5V signals. A VAR mode is also provided with a large input voltage range, an
adjustable threshold and slope/logic definition. AC/DC coupling selection is possible for the trigger input.
(see Inputs Specifications on page 6 for more details).
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Clock, Gate, Detection1 and Detection2 outputs blocks with SMA connectors on the ID210 front panel.
Through the ID210 user interface, each output can be set independently for providing LVTTL-LVCMOS, NIM,
NECL, PECL3.3V or PECL5V signals. The user can also switch to VAR mode in which the pulse width, the
logic definition, the high and low signal levels and the load can be adjusted. (see outputs specifications on
page 6 for more details).
¡
An avalanche photodiode and associated electronics.The key component at the heart of the ID210 is a
cooled InGaAs fiber-coupled avalanche photodiode (APD). The fiber (single mode or multi-mode) is
connectorized to a FC/PC connector on the ID210 front panel. The APD terminals are connected to:
- a DC high voltage controlled by the system to reach the efficiency set through the id210 interface,
- a pulser electronics that produces constant amplitude pulses for operation in single photon regime.
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ID Quantique T +41 22 301 83 71 [email protected]
Geneva / Switzerland F +41 22 301 83 79 www.idquantique.com
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¡
the System hardware
The system hardware allows the ID210 operation in internal gated, external gated, free-running or free-
gating modes.
Internal-gating mode:
The APD is biased above breakdown during gates of adjustable width and frequency. Internal gating is a
synchronous mode based on a clock provided by the internal clock generator. The 50% duty cycle clock
signal is available at the clock output and counted by the HF clock counter. A user-adjustable trigger delay
can be set between the clock and the gate signals. A gate of width set by user is open on the rising edge of
the delayed trigger. As consequence of an avalanche event within the gate, the HF detection counter is
incremented and a pulse of adjustable width is outputted at detection1 and detection2 connectors. The
quenching electronics closes the gate and, if selected by the user, a dead time is applied resulting in one or
several blanked pulses after a detection.
The HF Gate Counter provides an exact count of the effective gates seen by the APD.
Internal gated mode
1/Internal Gating Frequency
Clock Output
Dead Time
Trigger Delay
ate
dg
Gate Width nke
Gate Output bla
Quenching
HF Clock Counter +1 +1 +1 +1
HF Gate Counter +1 +1 +1
HF Detection Counter +1
External-gating mode:
The operation in external gating mode is very similar to the internal gating mode except that the clock is
provided by the user at the Trigger input.
External gated mode
Trigger Input
Dead Time
Trigger Delay
ate
dg
Gate Width nke
Gate Output bla
Quenching
HF Clock Counter +1 +1 +1 +1
HF Gate Counter +1 +1 +1
HF Detection Counter +1
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Geneva / Switzerland F +41 22 301 83 79 www.idquantique.com
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HF Gate Counter +1 +1 +1
HF Detection Counter +1 +1 +1
Free-gating mode:
The user feeds an electrical signal at the reset/enable input. The signal, after transit in the input block,
passes through multiplexers and the dead time stage. When no avalanche occurs, the gate output that
reflects the APD state (On/Off) is identical to the reset/enable input signal. When an avalanche occurs during
a gate, a pulse of adjustable width is produced at detection1 and detection2 outputs, the detection HF
counter is incremented and the quenching electronics stops the gate. When a dead time is applied for limiting
the afterpulsing, the gate signal remains at low level whatever the reset/enable state. This results in blanked
gate(s) or partially blanked gates. The HF gate counter provides the effective gates rate applied to the APD.
Free-gating mode
Reset/Enable Input
Dead Time
ked
lan
ate yb
dg iall
ke part
Gate Output blan gate
HF Gate Counter +1 +1 +1 +1
HF Detection Counter +1 +1 +1
¡
A two-channel event counter and a coincidence counter as an auxiliary independent block.
The signals outputted by Aux1 and Aux2
inputs blocks feed HF counter Aux1 and HF Aux1 Input
HF Counter Aux1&Aux2 +1 +1 +1 +1 +1
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Geneva / Switzerland F +41 22 301 83 79 www.idquantique.com
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OUTPUTS SPECIFICATIONS
Parameter Min Typical Max Units
High level voltage range (high Z to ground) 1 -2.0 +7.0 V
High level voltage range (50W
to ground) 3 -1.0 +3.5 V 1 Starting with a Predefined Standard, all
Low level voltage range (high Z to ground) 1 -3.0 +5.0 V the parameters can be modified by the user.
Low level voltage range (50W
to ground) 3 -1.5 +2.5 V
Voltage swing (high Z to ground) 2 +0.1 +7.0 V 2 The Outputs parameters or Predefined
Voltage swing (50W
to ground) 4 +0.05 +3.5 V Standards are included in setup files that
Logic + or - can be saved on internal memory.
Short pulse width (Detection1, Detection2) 4.5 5 5.5 ns
Large pulse width (Detection1, Detection2) 90 100 110 ns
Rise/fall times at 5V swing (10%-90%) 2.5 ns
Predefined standards 1 2 LVTTL/LVCMOS - NIM - NECL - PECL3.3V - PECL5V
Connectors SMA
Protection ESD
+ 1 + 3
0
0 + 2 Low level [V] + 1
Low level [V] Min. Min.
-1 + 1
-1
-2 0 0
-3 -2 -1 0 + 1 + 2 + 3 + 4 + 5 -3 -2 -1 0 + 1 + 2 + 3 + 4 + 5 -2 -1 0 + 1 + 2 + 3 -1 0 + 1 + 2
Low level [V] Low level [V]
1 Low level and high level 2 Minimum and maximum 3 Low level and high level 4 Minimum and maximum
voltage ranges when the output is voltage swings when the output is voltage ranges when the output is voltage swings when the output
loaded at high impedance to loaded at high impedance to loaded at 50Wto ground. is loaded at 50Wto ground.
ground. ground.
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ID Quantique T +41 22 301 83 71 [email protected]
Geneva / Switzerland F +41 22 301 83 79 www.idquantique.com
Best-in-Class
Performance
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ID Quantique T +41 22 301 83 71 [email protected]
Geneva / Switzerland F +41 22 301 83 79 www.idquantique.com
Best-in-Class
Performance
ORDERING OPTIONS
When ordering, please specify:
- Trigger rate 20MHz or 100MHz
- Remote control activation status
- Free-running activation status
SUPPLIED ACCESSORIES
¡Power cable
¡Optical fiber cleaner
¡User guide on USB key
¡Compact USB key board
¡1 meter FC/PC patchcord
Disclaimer - The information and specification set forth in this document are subject to change at any time by ID Quantique without prior notice. Copyright© 2014 ID Quantique SA - All rights reserved -
ID210 v2014 07 10 - Specifications as of July 2014