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DE Assignment-3

This document contains an assignment for a Digital Electronics course. It includes 10 questions related to asynchronous sequential circuits, gated latches, state diagrams, hazards in combinational circuits, types of memories, logic families, and transistor-transistor logic (TTL) gates. Students are asked to draw circuit diagrams, derive transition tables and flow tables, explain concepts like races and hazards, compare static and dynamic random-access memory (SRAM and DRAM), and illustrate the operation of a TTL NAND gate.

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43 views2 pages

DE Assignment-3

This document contains an assignment for a Digital Electronics course. It includes 10 questions related to asynchronous sequential circuits, gated latches, state diagrams, hazards in combinational circuits, types of memories, logic families, and transistor-transistor logic (TTL) gates. Students are asked to draw circuit diagrams, derive transition tables and flow tables, explain concepts like races and hazards, compare static and dynamic random-access memory (SRAM and DRAM), and illustrate the operation of a TTL NAND gate.

Uploaded by

shivajisingh12345678123456
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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ABES Engineering College, Ghaziabad

Department of Computer Science

Session: 2023-24 Semester: III Branch/Section: CS-A/B/C


Course Code: BOE-310 Course Name: Digital Electronics

Assignment 3

Date of Assignment: 12-Feb-2024 Date of submission:16/2/2024

S.No. Question CO

An asynchronous sequential circuit is described by the following CO4


excitation and output function,
1 Y= x1x2+ (x1+x2) y Z= Y
a) Draw the logic diagram of the circuit.
b) Derive the transition table, flow table and output map.
c) Describe the behavior of the circuit.
Design an asynchronous sequential circuit that has two internal CO4
states and one output. The excitation and output function describing
2 the circuit are as follows:
Y1= x1x2+ x1y2+ x2y1 Y2= x2+ x1y1y2+ x1y1 Z= x2+ y1.
a) Draw the logic diagram of the circuit.
b) Derive the transition table, output map and flow table.
3 Define Race. What are different types of Races, explain them with CO4
example.
Design a gated latch circuit with inputs, G (gate) and D (data), and one CO4
output, Q. Binary information present at the D input is transferred to the
Q output when G is equal to 1. The Q output will follow the D input as
long as G= 1. When G goes to 0, the information that was present at the
4
D input at the time of transition occurred is retained at the Q output. The
gated latch is a memory element that accepts the value of D when G= 1
and retains this value after G goes to 0, a change in D does not change
the value of the output Q.
Develop a state diagram and primitive flow table for a logic system CO4
that has two inputs, X and Y, and a single output X, which is to
behave in the following manner. Initially, both inputs and output
are equal to 0. Whenever X= 1 and Y= 0, the Z becomes 1 and
5 whenever X= 0 and Y= 1, the Z becomes 0. When inputs are zero, i.e.
X= Y= 0 or inputs are one, i.e. X= Y= 1, the output Z does not
change; it remains in the previous state. The logic system has edge
triggered inputs without having a clock. The logic system changes
state on the rising edges of the two inputs. Static input values are
not to have any effect in changing the Z output.

(i)Distinguish between static and dynamic hazard. How will you CO4
determine hazard in combinational circuits?
(ii)Draw the logic diagram of the product-of-sums expression
Y= (x1+x2’) (x2+x3)
6 Show that there is a static 0-hazard when x1 and x3 are equal to 0 and x2
goes from 0to 1. Find a way to remove the hazard by adding one more
OR gate.
iii) Design a hazard-free circuit to implement the following function.
F (A, B, C, D) = Σm (0, 1, 5, 6, 7, 9, 11).

7 Compare SRAM and DRAM. Also Compare all types of memories CO5

8 Illustrate the use of logic families in digital circuits. Explain Fan-in and CO5
Fan-out.
9 Why is ECL logic faster than TTL? CO5

10. Draw a neat diagram of TTL NAND gate and explain its operation CO5

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