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DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

QUESTION BANK

SUBJECT CODE/NAME : EC 8392/ DIGITAL ELECTRONICS

YEAR / SEMESTER : II / III

UNIT I DIGITAL FUNDAMENTALS

Number Systems – Decimal, Binary, Octal, Hexadecimal, 1‘s and 2‘s complements, Codes –
Binary, BCD, Excess 3, Gray, Alphanumeric codes, Boolean theorems, Logic gates, Universal
gates, Sum of products and product of sums, Minterms and Maxterms, Karnaugh map
Minimization and Quine-McCluskey method of minimization.

PART A
Q.
Questions BT Level Domain
No
1. State De-Morgan’s theorem and mention its use. BTL 1 Remembering
2. Express the function Y  A  BC in canonical POS. BTL 3 Applying
3. Convert the given decimal numbers to their binary equivalent
BTL 2 Understanding
108.364, 268.025.
4. Why totem pole outputs cannot be connected together? BTL 1 Remembering
5. Simplify the following Boolean expression into one literal.
BTL 4 Analyzing
W’X(Z’+YZ) + X(W+Y’Z).
6. Convert (115)10 and (235)10 into hexadecimal numbers. BTL 2 Understanding
7. Define ‘Minterm’ and ‘ Maxterm’. BTL 1 Remembering
8. Draw an active high tri-state Gate & write its truth table. BTL 3 Applying
9. Show how to connect NAND gates to get an AND gate and
BTL 2 Understanding
OR gate?
10. State Distributive law and Duality principle. BTL 1 Remembering
11. What is meant by Prime Implicant and Essential prime
BTL 1 Remembering
implicants?
12. Find the minimized Boolean expression of this function
BTL 1 Remembering
F=XY+X(Y+Z) +Y(Y+Z).
13. Implement the given function using NAND gates only.
F(X, Y, Z) = m(0,6) .
BTL 6 Creating

14. Find the canonical POS form of Y= A+B’C BTL 4 Analyzing

15. If A & B are Boolean variables and if A=1 & A  B =0,
BTL 5 Evaluating
determine B?
16. Apply De-Morgan’s theorem to simplify A  BC . BTL 3 Applying

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
17. Implement Y= (1,4,5,6,7) in SOP form using AOI logic. BTL 6 Creating
18. Determine the Boolean expression for the output of the system
shown in figure.

BTL 5 Evaluating

19.
Interpret the truth table of EX- OR gate. BTL 2 Understanding

20. Simplify: ABC  ABC using Boolean theorems. BTL 4 Analyzing

PART – B
1. (i) Find the Minimized logic function using K-Maps and Realize
using NAND and NOR gate.
BTL 1 Remembering
F (A, B, C, D) = m(1,3,5,8,9,11,15)  d(2,13) . (8)
(ii) Show that if all the gate in a two-level OR-AND gate network BTL 2 Understanding
are replaced by NOR gate, the output function does not change.
(5)
2. (i) Illustrate the MSOP representation for F(A,B,C,D,E) =
m(1,4,6,10,20,22,24,26)+d(0,11,16,27) using K-map
method. Draw the circuit of the minimal expression using BTL 2 Understanding
only NAND gates. (7) BTL 1 Remembering
(ii) Write about Excess 3 and Gray Code with an example.
(6)
3. (i) Develop the given function Y (M, N, O, P, Q)
= m(0,2,4,6,9,13,21,23,25,29,31) . Draw the K-map and
Implement the simplified expression using basic gates. BTL 4 Analyzing
(8)
(ii) Implement F= A’B’D’+ B’C’+E’ using NAND gates.
(5)
4. Evaluate the following Boolean expression using Boolean
Algebra and draw the logic diagram.
 
(i)T(X, Y, Z) = ( X  Y ) X Y  Z  X Y  X Z . (5)
BTL 5 Evaluating

(ii) XYZ  XYZ  XY (4)

(iii) XYZ  XZ  YZ (4)
5. (i) Why does a good logic designer minimize the use of NOT
gates? (3) BTL 2 Understanding
(ii) Find a MinSOP and MinPOS for the following function BTL 4 Analyzing
F= bcd  bcd  acd  abc  abcd . (10)

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6. (i) Using K-map method, Simplify the following Boolean

function =∑m(0,2,3,6,7) + d(8,10,11,15) and obtain BTL 2 Understanding
(a) minimal SOP (6)
(b) minimal POS expression & realize using only NAND
and NOR gates. (7)
7. (i) Draw the multilevel two input NAND circuit for the following
expression: F  ( AB  CD)E  BC(A  B) (3) BTL 4 Analyzing
(ii) How would you express the Boolean function using K-map
and draw the logic diagram BTL 1 Remembering
F (w,x,y,z)= m(0,1,2,4,5,6,8,9,12,13,14) . (10)
8. (i) Simplify the following function using K – map,
F=ABCD+AB’C’D’+AB’C+AB & realize the SOP using
only NAND gates and POS using only NOR gates. (8)
(ii) Simplify the logic circuit shown in figure (5)

BTL 4 Analyzing

9. Explain the minimization of the given Boolean function using

Quine-Mc-Cluskey method
BTL 1 Remembering
F= m(0,1,2,5,7,8,9,10,13,15) .Realize the simplified function
using logic gates. (13)

10. (i) Explain the implement of the following function using

NAND and inverter gates F=AB+A’B’+B’C.
(5) BTL 1 Remembering
(ii) Using K-map method, simplify the given Boolean function
and obtain minimum POS expression.
X= m(1,3,5,7,9)  d(8,11,15) . (8)


11. (i) Given Y(A,B,C,D)= M (0,1,3,5,6,7,10,14,15) , Draw the
K-Map and Obtain the simplified expression. Design the
minimum expression using basic gates. (8)
BTL 6 Creating
(ii) Construct the expression Y (A, B, C) = M (0,2,4,5,6) using
Only NOR-NOR logic. (5)

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12. What are the advantages of using tabulation method? Develop the
following Function using Tabulation method
F= (1,2,3,7,8,9,10,11,14,15) and implement using only NAND BTL 3 Applying
(13)
13. i. Convert (725.25)8 to its decimal, binary and Hexadecimal
equivalent. (6)
ii. Find 1’s and 2’s Complement of 8 digit binary numbers BTL 2 Understanding
10101101 (7)

14. (i) ImplementY= (A  C)(A  D)(A  B  C) (5)

(ii) Solve by perfect induction (8)
(a) A+AB = A
(b) A(A+B) = A BTL 3 Applying
(c) A+A’B = A+B and
(d) A(A’+B) =AB

PART C
1. Design the given function using Prime implicant method and
Verify your result using K map F= m(0,1,2,4,5,6,8,9,12,13,14) BTL 6 Creating
(15)
2. A staircase light is controlled by two switches , one is at the top
of the stairs and the other is at the bottom of the stairs :
i. Make a truth table for this system. (3)
ii. Write the logic function in SOP form. (3) BTL 5 Evaluating
iii. Realize the circuit using AOI logic. (4)
Realise the circuit using minimum number of NAND and
NORgates. (5)

3. Implement the following function using Quine McCluskey

method
BTL 6 Creating
F= m(0,1,2,8,9,15,17,21,24,25,27,31) +d(3,4,11) (15)

4. Develop the simplified Boolean expression for f(A,B,C,D,E)=

(0,5,6,8,9,10,11,16,20,24,25,26,27,29,31) (15) BTL 5 Evaluating

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UNIT II COMBINATIONAL CIRCUIT DESIGN

Design of Half and Full Adders, Half and Full Subtractors, Binary Parallel Adder – Carry look ahead Adder, BCD
Adder, Multiplexer, Demultiplexer, Magnitude Comparator, Decoder, Encoder, Priority Encoder.
PART A
Q.No Questions BT Domain
Level
1. Define Half adder and Full adder circuit. BTL 1 Remembering
2. Construct 4-bit parallel adder/subtractor using Full adders and EXOR gates. BTL 6 Creating
3. Relate carry generate, carry propagate, sum and carry-out of a carry look
BTL2 Understanding
ahead adder.
4. Write about the design procedure for combinational circuits. BTL 1 Remembering
5. Identify the basic principle used in order to check or generate the proper
BTL 3 Applying
parity bit in a given code word.
6. Distinguish between demultiplexer and decoder BTL 4 Analyzing
7. Convert a two-to-four line decoder with enable input to 1:4 demultiplexer. BTL2 Understanding
8. Write about the design procedure for combinational circuits. BTL 1 Remembering
9. Sketch the logic diagram and truth table for Full adder circuit. BTL 3 Applying
10. Compare the function of decoder and encoder. BTL 2 Understanding
11. Evaluate the logic circuit of a 2 bit comparator. BTL 5 Evaluating
12. Design the logic circuit of Half subtractor using truth table. BTL 6 Creating
13. State the function of select inputs of a MUX. BTL 1 Remembering
14. Develop the following function using suitable multiplexer F= Σm(0,2,5,7). BTL 4 Analyzing
15. How would you design the logic diagram of a 2 bit multiplier? BTL 1 Remembering
16. Draw the logic diagram of a serial adder. BTL3 Applying
17. Explain a 3 bit even parity generator. BTL5 Evaluating
18. Describe code converter? List their types. BTL 2 Understanding
19. Examine a single bit magnitude comparator to compare two words A and B. BTL 4 Analyzing
20. Convert gray code 101011 into its binary equivalent. BTL 2 Understanding
PART – B
1. (i) How will you design a full adder using two half adders and an OR gate.
(5) BTL 4 Analyzing
(ii) Analyze the principle and design of Parallel multiplier with diagrams (8)
2. (i) Design a 4-bit decimal adder using 4-bit binary adders. (7) BTL 6 Creating
(ii) Simplify the function using multiplexer F= (0,1,3,4,8,9,15) . (6) BTL 4 Analyzing
3. (i) Construct full subtractor using Demultiplexer. (6) BTL 3 Applying
(ii) Write short note on BCD adder. (7) BTL 1 Remembering
4. (i) Analyze the design of 8 x 1 multiplexer using only 2 x 1 multiplexer. (6)
(ii) Formulate the following Boolean function using 4 x 1 multiplexers. BTL 4 Analyzing
F(A, B,C, D)  (1,2,3,6,7,8,11,12,14) . (7) BTL 6 Creating

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5. (i) Draw the logic diagram of a 2-bit by 2-bit binary multiplier and explain
its operation. (6) BTL 3 Applying
(ii) Realize F(w, x, y, z)= Σ (1,4,6,7,8,9,10,11,15) using 8 to 1 Multiplexer. BTL 2 Understanding
(7)
6. (i) Realize a circuit to carryout both addition and subtraction. (7)
(ii) Deduce the design of a 1:8 demultiplexer circuit. (6) BTL 2 Understanding
7. How would you design
(i) Full adder using demultiplexer. (7) BTL 1 Remembering
(ii) Serial binary adder. (6) BTL 4 Analyzing
8. Illustrate BCD to excess 3 code converter using minimum number of NAND
gates. (13) BTL 2 Understanding
9. (i) Explain the working and draw the logic diagram of Binary to
Octal decoder. (6) BTL 1 Remembering
(ii) How would you design BCD to Gray code converter. Use don’t care. (7)
10. (i) Demonstrate 4-bit magnitude comparator with three outputs:
A>B, A=B and A<B. (7) BTL 2 Understanding
(ii) Build a 4-bit Priority Encoder circuit using gates. (6) BTL 3 Applying

11. (i) Give a combinational circuit that converts 4 bit Gray Code to a 4 bit
BTL 1 Remembering
binary number. Implement the circuit. (8)
(ii) Develop a Full adder using decoder. (5) BTL 3 Applying
12. (i) How would you design a 3:8 decoder using basic gates? (7) BTL 1 Remembering
(ii) How would you design a binary to gray code convertor? (6) BTL 4 Analyzing
13. (ii) Describe the design of Binary Multiplier using Shift Add method.
(6)
(ii) Show the design of excess 3 to BCD code converter using minimum BTL 1 Remembering
number of NAND gates (7)
14. (i) Estimate the logic diagram of BCD-Decimal decoder and explain its
operations. (7)
(ii) Interpret the design of a BCD to seven segment decoder with neat BTL 5 Evaluating
diagrams. (6)

PART C
1. With necessary diagrams, explain in detail about the working of a 4-bit look
ahead carry adder. Also mention its advantages over conventional adder.(15) BTL 5 Evaluating

2. Implement the following Boolean function using an 8:1 multiplexer

considering D as the input and A,B,C as selection lines : BTL 5 Evaluating
F( A, B, C, D) = AB’+BD+B’CD’ (15)

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3. Construct 4-bit binary multiplier and divider and explain its operation with
suitable example. (15) BTL 6 Creating
4. (i). Design an even parity generator that generates an even parity bit for
every input string of 3 bits. (10) BTL 6 Creating
(ii). Explain the need of Parity Checker circuit with necessary diagrams. (5)

UNIT III SEQUENTIAL CIRCUITS

Flip flops – SR, JK, T, D, Master/Slave FF – operation and excitation tables, Triggering of FF, Analysis and
design of clocked sequential circuits – Design - Moore/Mealy models, state minimization, state assignment,
circuit implementation – Design of Counters- Ripple Counters, Ring Counters, Shift registers, Universal Shift
Register. .
PART A
Q. BT
No Questions Level Domain
Bring out the difference between synchronous sequential circuits and
1. BTL 3 Applying
asynchronous sequential circuits.
2. Define the terms: state table and state assignment. BTL 1 Remembering
Construct the state diagram of Mod-10 ring counter and find the number of
3. BTL 5 Evaluating
Flip Flops required.
4. State the classification of Sequential circuits. BTL 1 Remembering

5. Realize JK Flip Flops. BTL 5 Evaluating

6. Analyze the differences between Latch and Flipflop. BTL 4 Analyzing

7. Build a T Flip-flop from a D Flip-flop. BTL 3 Applying

8. Illustrate the logic diagram of a clocked SR Flipflop. BTL 3 Applying

9. State the difference between Mealy and Moore state machines. BTL 1 Remembering
10. How does ripple counter differ from synchronous counter? BTL 2 Understanding
11. Point out the condition on JK FF to work as D FF. BTL 4 Analyzing
12. Model a NAND based logic diagram of Master Slave JK FF. BTL 2 Understanding
13. Build the state diagram and characteristics equation of a D FF. BTL 6 Creating
Find minimum number of flip-flops needed to design a counter of Modulus
14. BTL 1 Remembering
60.
A binary ripple counter is required to count upto 16,38310. How many Flip
15. Flops are required ? If the clock frequency is 8.192 MHz, What is the BTL 6 Creating
frequency at the output of MSB?
16. What is the primary disadvantage of asynchronous counter? BTL 1 Remembering

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Point out two differences between edge triggering and level triggering in
17. BTL 4 Analyzing
sequential circuits.
18. Explain about D-Latch with truth table. BTL 2 Understanding
How many flip-flops are required to build a binary counter that counts from
19. BTL 2 Understanding
0 to 1023?
20. Draw the state diagram for removing lockout in Counters. BTL 1 Remembering
PART – B
1. How would you design the Sequential circuit has three flip flops A, B, and
C; one input X_in ; and one output Y_out. The state diagram is shown in
below figure. The circuit is to be designed by treating the unused states as
don’t care conditions. Analyze the circuit obtain from the design to
determine the effect of the unused states. Use T flip flops in the design. (13)

BTL 1 Remembering

2. (i) Compare the diagram of a 4-bit SISO SIPO, PIPO and PISO shift
register and draw its waveforms. (8) BTL5 Evaluating
(ii) Realize D flip-flop using SR flip-flop. (5) BTL 2 Understanding

3. (i) Construct a 4-bit down counter using logic gates. (5)

(ii) Model a synchronous MOD-6 counter and explain with waveforms.
(8) BTL 3 Applying

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4. (i) Examine the number of state reduction in the following state table,
and tabulate the reduced state table. (7)

Present Next State Output

state X=0 X =1 X =0 X=1
A F B 0 0
B D C 0 0
C F E 0 0 BTL 4 Analyzing
D g A 1 0
E d C 0 0
F f B 1 1
G g H 0 1
H g A 1 0
(ii) Examine a BCD ripple counter with timing diagram. (6)

5. Analyze state reduction if possible after designing a clocked synchronous

sequential logic circuit using JK flip flops for the following state diagram.
Use state reduction if possible. (13)

BTL 4 Analyzing

6. (i) Show the operation of universal shift register with neat block diagram. BTL 1 Remembering
(7)
(ii) Estimate the design a counter to count the sequence 0, 1, 2, 4, 5, 6 BTL 5 Evaluating
,…..using SR FF’s. (6)

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7.
(i) Interpret design of a 3 bit synchronous counter using JK flip-flop.
(10) BTL 3 Applying
(ii) Differentiate between a state table, characteristic table and an BTL 2 Understanding
excitation table for D Flip Flop. (3)
8. How would you describe the design of following:
(i) Synchronous counter with states 0, 1, 2, 3, 0, 1, ..... using JK flip flop.
(7) BTL 1 Remembering
(ii) Write short notes on Mealy and Moore sequential circuits . (6)

9. (i) Use T flip-flop to design counter with the following repeated binary
sequence 0, 4, 7, 2, 3. (8) BTL 2 Understanding
(ii) Realize JK Flip Flop using SR Flip Flop (5) BTL 2 Understanding

10. (i) Illustrate with diagram an asynchronous decade counter & its
operation with neat waveforms. (7) BTL 1 Remembering
(ii) Predict the design of a synchronous 3-bit counter which counts in the BTL 2 Understanding
sequence 1, 3, 2, 6, 7, 5, 4, (repeat ) 1, 3..... using T FF . (6)
11. Using SR flipflops design a parallel counter which counts in the sequence
000,111,101,110,001,010,000,… (13) BTL 6 Creating

12. (i) Discuss in detail about the pulse- triggered S-R Flip Flop with
necessary diagrams. (7)
(ii) Deduce a clocked synchronous sequential machine using T flip flops
for the following state diagram. Use state reduction if possible .Also
use straight binary state assignment. (6) BTL 2 Understanding

BTL 4 Analyzing

13. (i) Using D flip-flop, Design a synchronous counter which counts in the
sequence 000,001,010,011,100,101,110,111,000. (10) BTL 3 Applying
(ii) Discuss the working of 4 bit Johnson counter with neat diagram. (3) BTL 1 Remembering

14. (i) Point out a sequence detector design which detects the sequence BTL 4 Analyzing
01110 using D flip flop. (7) BTL 1 Remembering

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(ii) Enumerate about Triggering of Flip-Flop. (6)

PART C
1. Design a J-K counter that goes through states 3,4, 6 , 7 and 3….. Is the
counter self – starting ? Modify the circuit such that whenever it goes to an BTL 6 Creating
invalid state it comes back to state 3. (15)
2. Explain the functions with the state diagram and characteristics equation of T
FF, D FF and JK FF and compare and contrast among the FFs? (15) BTL 5 Evaluating
3. A sequential machine has one input line where 0’s and 1’s are being
incident. The machine has to produce the output of ‘1’ only when exactly
BTL 6 Creating
two ’0’s are followed by ‘1’ or exactly two ‘1’s are followed by a ‘0’. Using
any statement assignment in JK flipflop, synthesize the machine. (15)
4. Determine the design of a clocked sequential machine using JK Flip Flops
for the state diagram shown in figure. Use state reduction if possible and
make proper state assignment. (15)

BTL 5 Evaluating

UNIT IV ASYNCHRONOUS SEQUENTIAL CIRCUITS

Stable and Unstable states, output specifications, cycles and races, state reduction, race free assignments,
Hazards, Essential Hazards, Pulse mode sequential circuits, Design of Hazard free circuits.

PART A
BT
Q. No Questions Domain
Level
1. Mention the steps for the design of asynchronous sequential circuit? BTL 1 Remembering
2. Classify Asynchronous sequential circuits. BTL 2 Understanding
Bring out the difference between fundamental mode and pulse mode
3. sequential circuits BTL 4 Analyzing

4. Define dynamic hazard? When do they occur? BTL 3 Applying

5. What are pulse mode circuits? BTL 2 Understanding
6. Distinguish between stable and unstable state. BTL 4 Analyzing

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7. State the significance of state assignment? BTL 2 Understanding

8. Outline about asynchronous sequential circuit? BTL 1 Remembering
9. Illustrate about fundamental mode sequential circuit? BTL 3 Applying
10. Recall about Hazards? How it can be avoided? BTL 1 Remembering
11. Compare the ASM chart with a conventional flow chart. BTL 2 Understanding

12. Compile fundamental mode and pulse mode asynchronous sequential BTL 6 Creating
circuits.
13. Analyze the causes of essential Hazard. BTL 4 Analyzing
14. Construct a combinational Hazard free circuits. BTL 6 Creating
15. Explain the analysis procedure of asynchronous sequential circuits. BTL 5 Evaluating
16. List the different techniques used in State assignment. BTL 1 Remembering
17. Model a Stable circuit and give one example. BTL 3 Applying
Identify the types of Hazards that exist in asynchronous sequential
18. BTL 1 Remembering
circuits.
Interpret critical race and give the methods for critical-race free state
19. BTL 5 Evaluating
assignment.

20. How can a race in digital circuits can be avoided? BTL 1 Remembering

PART – B

1.
Design an asynchronous sequential circuit with 2 inputs T and C. The
output attains a value of 1 when T=1 and C moves from 1 to 0. BTL 6 Creating
Otherwise the output is 0. (13)
2. (i) What are the types of hazards? Check whether the following circuit
contains a hazard or not Y = X1X2 + X2′X3.If the hazard is present,
BTL 1 Remembering
Demonstrate its removal. (13)

3. An asynchronous sequential circuit is described by the following

excitation and output function.

Y= X1X2+(X1+X2) Y, Z=Y.

i. Draw the logic diagram. (3) BTL 4 Analyzing

ii. Derive the transition table and output map. (5)

iii. Describe the behavior of the circuit (5)

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4. (i) What is a Hazard? Give hazard free realization for the following
BTL 1 Remembering
Boolean function. F (A, B, C, D) = ∑m (1,5,6,7) using AND- OR
gate network . (10)
(ii) Define Essential Hazards (3)
5. (i) Summarize the design procedure for a asynchronous sequential
circuit. (10) BTL 2 Understanding
(ii) Derive the state table of serial binary adder. (3)
6. Find a circuit that has no static hazards and implements the

Boolean function F(A,B,C,D) = Σ (0,2,6,7,8,,10,12) using AND-OR BTL 4 Analyzing

logic. (13)

7. Discuss the various problems arises in an asynchronous sequential

circuits. Explain any two problems in detail. BTL 2 Understanding
. (13)
8. (i) Explain in detail about Races. (5)
(ii) Explain the different methods of state assignment. (8) BTL 4 Analyzing

9. (i) Explain the fundamental mode asynchronous sequential circuit.

(7)
BTL 5 Evaluating
(ii) Explain the different types of Hazards. Design Hazard free circuits
for Y=X1X2+X2’Y. (6)
10.
Define asynchronous sequential circuits, cycles, critical race and Non
BTL 1 Remembering
Critical race. (13)

11.
Explain with neat diagram the different hazards and the
way to eliminate them. (13) BTL 3 Applying

12. What is the objective of state assignment in a asynchronous circuits

?Give example circuit for hazard free realization. (13) BTL 1 Remembering

13. Classify the methods of Race Free State assignment and explain in
BTL 2 Understanding
detail. (13)
14. Design an Asynchronous sequential circuit with input A and B and an output
Y. Initially at any time if both the inputs are 0, the output, Y=0 . When A or B
= 1, Y =1. When the other input also become 1, Y=0. The output stays at 0
BTL 3 Applying
until circuit goes back to initial state.
(13)

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PART – C
1. Design a asynchronous sequential circuit with two inputs X and Y and
with one output Z. Whenever Y is one, input X is transferred to Z. When
BTL 6 Creating
Y is zero, the output does not change for any change in X.
(15)
2. Design a asynchronous D- type latch with two inputs C and D and BTL 5 Evaluating
output Q. Assume fundamental mode of operation. (15)
3. Assess a circuit with primary inputs A and B to give an output Z equal
to 1 when A becomes 1 if B is already 1. Once Z = 1 it will remain so
until A goes to 0. Draw timing diagram, state diagram, Primitive flow
table for designing the circuit. BTL 6 Creating

(15)

4. Construct an asynchronous circuit that will output only the first pulse
BTL 5 Evaluating
received and will ignore other pulses. (15)

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UNIT V MEMORY DEVICES AND DIGITAL INTEGRATED CIRCUITS

Basic memory structure – ROM -PROM – EPROM – EEPROM –EAPROM, RAM – Static and dynamic
RAM - Programmable Logic Devices – Programmable Logic Array (PLA) - Programmable Array Logic
(PAL) – Field Programmable Gate Arrays (FPGA) - Implementation of combinational logic circuits using
PLA, PAL. Digital integrated circuits: Logic levels, propagation delay, power dissipation, fan-out and fan-in,
noise margin, logic families and their characteristics-RTL, TTL, ECL, CMOS

PART A

Q.No Questions BT Domain

Level
1. Compare and contrast the TTL, ECL gates. BTL 2 Understanding
2. Outline about CMOS logic circuits. BTL 1 Remembering
3. Point out the advantages of ECL. BTL 4 Analyzing
4. How does ROM retain information? BTL 1 Remembering
5. Distinguish between volatile and non-volatile memory. BTL 2 Understanding
6. Define propagation delay in logic gate. BTL 1 Remembering
7. Show the implementation of Y= A+B’C using CMOS logic. BTL 3 Applying
8. Explain fan-in & fan-out of a standard TTL IC. BTL 4 Analyzing
9. Classify the different types of programmable logic device. BTL 3 Applying
10. State the advantages of FPGA. BTL 1 Remembering
11. Classify the logic gate families. BTL 3 Applying
12. What is programmable logic array? How it differs from ROM? BTL 1 Remembering

Implement the function F1=∑ (0, 1, 2, 5, 7) and F2 = ∑ (1, 2, 4, 6)

13. BTL 4 Analyzing
using PROM.

14. Enumerate about EPROM. BTL 1 Remembering

15. Generalize the implementation of 2 bit multiplier using ROM. BTL 6 Creating
16. Formulate the implementation of Ex OR function using PROM. BTL 6 Creating
17. Explain the advantages of EEPROM over EPROM. BTL 5 Evaluating
18. Describe various features of PROM, PAL and PLA. BTL 2 Understanding
19. Distinguish between PAL and PLA. BTL 2 Understanding
20. How the ECL logic is different from TTL? BTL 5 Evaluating

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PART – B
1. (i) Describe about noise margin and propagation delay in logic gates
(7)
(ii) Construct a combinational circuit is defined as the function BTL 1 Remembering
F1 = AB’C’+AB’C+ABC and F2 = A’BC+AB’C+ABC.
Implement the digital circuit with a PLA having 3 inputs, 3 BTL 4 Analyzing
Product terms and 2 outputs. (6)
2. (i) Classify the types of PLDs and write notes on PLDs. (7)
(ii) Implement the following Boolean function using 3×4×2 PLA, BTL 2 Understanding
F1(x, y, z) = ∑ (0, 1, 3, 5) and F2(x, y, z) = ∑ (3, 5, 7). (6) BTL 3 Applying

3. (i) Demonstrate the realization of the following function using PAL

F1(x, y, z) = ∑ (1, 2, 4, 5, 7). And F2(x, y, z) = ∑ (0,1,3,5,7). (7) BTL 2 Understanding
(ii) Write a notes on FPGA with neat diagram. (6)
4. (i) State the advantages of CMOS logic. (3)
BTL 2 Understanding
(ii) Analyze a combinational circuit using ROM. The circuit
accepts a three bit number and outputs a binary number equal to
BTL 4 Analyzing
the square of the input number. (10)
5. Create the design of BCD to Excess 3 using PLA? (13) BTL 6 Creating
6. (i) Demonstrate the classification of semiconductor memories (7)
BTL 3 Applying
(ii) Manipulate the function using PLA F1=∑ (2, 4, 5, 10, 12, 13, 14)
and F2 = ∑ (2, 9, 10, 11, 13, 14, 15). (6)
7. (i) Discuss the basic concepts and the principle of operation of
Bipolar SRAM cell. (7) BTL 3 Applying
(ii) How can one make 64× 8 ROM using 32×4 ROMs? Draw such a
BTL 4 Analyzing
circuit & explain. (6)
8.
How can you create the design of 32 ×8 ROM and give an explanation
BTL 4 Analyzing
about it? (13)
9. (i) Differentiate static and dynamic RAM. Draw the circuits of one
cell of each and explain its working principle. (8)
(ii) Realize the following function using PLA BTL 2 Understanding
F (w, x, y, z) = Π (0, 3, 5, 7, 12, 15) + d (2, 9). (5)

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 10. (i) Implement the switching functions.
BTL 5 Evaluating
z1  abde  abce  bc  de
z2  ace
z3  bc  de  cde  bd and
z4  ace  ce
using a 5*8*4 PLA. (7) BTL 1 Remembering
(ii) Write short notes on EPROM and EEPROM. (6)
11. (i) Compare types of logic families and explain a short note on
CMOS logic gate. (8) BTL 4 Analyzing
(ii) Implement the following function using PLA F1=∑ (0, 1, 2, 4)
BTL 5 Evaluating
and F2 = ∑ (0, 5, 6, 7). (5)
12. Recognize the implementation of the following Boolean functions
using 4 × 3 × 4 PAL. (13)
(i) W(A,B,C,D)= ∑ (0,2, 6,7,8,9,12,13)
(ii) X(A,B,C,D)= ∑ (0, 2, 6, 7, 8, 9, 12, 13, 14) BTL 1 Remembering
(iii)Y(A, B, C, D) = ∑ ( 2, 3, 8, 9, 10, 12, 13)
(iv) Z(A,B,C,D)= ∑ (1, 3, 4, 6, 9, 12, 14)
(i) Examine the structure of ECL and TTL (7)
13. (ii) Outline about Tri state inverter configuration with neat BTL 1 Remembering
diagram. (6)

14. (i) Explain EAPROM and static RAM cell using MOSFET? (5)
(ii) Recognize 512 X 8 ROM using eight 64x8 ROM chips with an BTL 1 Remembering
enable input and a decoder? (8)
PART C
1. Design a combinational circuit using CMOS logic. The circuit
accepts a three bit number and outputs a binary number equal to the BTL 6 Creating
square of the input number. (15)
2. Develop the code converters using PROM devices. (15)
(i) Binary to gray code BTL 5 Evaluating
(ii) Gray to Binary code
3. (i) Interpret how does Programmable logic devices differ from
FPGA? (8)
(ii) Formulate the implementation of the following functions with
PLA having three inputs, four product terms, and two outputs. BTL 5 Evaluating
F1 (A, B, C) = (3, 5, 6, 7)
F2 (A, B, C) = (0, 2, 4, 7) (7)
4. Build the structure of PAL and PLA. How a combinational logic
function is implemented in PAL and PLA? Explain with an example BTL 6 Creating
for each. (15)

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