Presented to the College of Computer Studies

De La Salle University - Manila

Term 2, A.Y. 2023-2024

In partial fulfillment of the course

In CSARCH1

COIN Project Proposal: Visual Accessibility in Iconography

Group No. 77

Submitted by:
Baccay, Dominic Luis M.
Del Mundo, Rahmon Khayle U.
Madrinan, Raico Luis C.

Submitted to:
Laguna, Ann Franchesca

February 6, 2024
INTRODUCTION

As the design project required the 4 inputs to be passed through a 2-1-2-6 code, the group
formulated a truth table that adhered to such whilst also factoring in the alternate codes that can
be used for 2, 3, 8, and 9 as the given code used two weighted-2s.

W (2) X (1) Y (2) Z (6) Output

0 0 0 0 0

0 1 0 0 1

1 0 0 0 2

0 0 1 0 2

0 1 1 0 3

1 1 0 0 3

1 0 1 0 4

1 1 1 0 5

0 0 0 1 6

0 1 0 1 7

0 0 1 1 8

1 0 0 1 8

0 1 1 1 9

1 1 0 1 9

1 0 1 1 N/A

1 1 1 1 N/A

Table 1 – Implementation of 2-1-2-6 Truth Table

The group also noticed a pattern among the 7 segment display wherein there are only
designated numbers each segment lights up on, prompting the group to follow the pattern which
eventually lead to the truth table below.

2 1 2 6 a b c d e f g

0 0 0 0 1 1 1 1 1 1 0

0 1 0 0 0 1 1 0 0 0 0

0 0 1 0 1 1 0 1 1 0 1

1 0 0 0 1 1 0 1 1 0 1

0 1 1 0 1 1 1 1 0 0 1

1 1 0 0 1 1 1 1 0 0 1

1 0 1 0 0 1 1 0 0 1 1

1 1 1 0 1 0 1 1 0 1 1

0 0 0 1 1 0 1 1 1 1 1

0 1 0 1 1 1 1 0 0 0 0

0 0 1 1 1 1 1 1 1 1 1

1 0 0 1 1 1 1 1 1 1 1

0 1 1 1 1 1 1 1 0 1 1

1 1 0 1 1 1 1 1 0 1 1

1 0 1 1 0 0 0 0 0 0 0

1 1 1 1 0 0 0 0 0 0 0

Table 2 – 2-1-2-6 Truth Table & its corresponding segment displays

INITIAL DESIGN PHASE

Figure 1 – Initial CircuitVerse Design

The group's initial design consisted of listing down all numbers that lit up per segment in the
display, whilst utilizing AND gates to produce the inputs that weren’t readily accessible (0, 3, 4,
5, 7, 8, 9). We then converted to boolean expressions the numbers present on each segment,
which eventually led to errors.

The group initially decided to have separate gates for 0, 1,

2, 3, 4, 5, 6, 7, 8, 9 – which were all indirectly linked to the
2-1-2-6 input. These separate gates were then used to
power each segment a, b, c, d, e, f, g – where all numbers
associated with that segment were linked to such. For
instance, segment A was represented by the expression 0
+ 2 + 6 + 9; segment B was represented by the expression
0 + 1 + 2 + 3 + 4 + 7 + 8 + 9; and so on. The group was
initially under the impression that in order for the individual
segments of the display to light up, all numbers associated
with it should be included within the expression of such –
which although was true, the group had failed to implement
properly as it was flawed and needed multiple gates which was not efficient.
Through this initial design phase, the group was able to correctly display 0, 1, 2, 3, 4, 5, 6, 8,
and 9; consequently having errors on displaying number 7 properly. This opted the group to find
alternative solutions in formulating the correct expressions to power the design.

These undertakings urged the group to use karnaugh maps in finding the minimal SOP
expressions per segment for the circuit design.

FINAL DESIGN PHASE

Figure 2 – Final CircuitVerse Design

On the tables above, alternative codes for 2, 3, 8, and 9 were represented with their own values
to give way for the formulation of the karnaugh map for each segment. This was to ensure that
all input combinations were covered within the karnaugh mapping and no further errors surface.
Karnaugh maps will be utilized in formulating the expressions that will be linked to each
segment as the group aims to design the circuit board with as minimal gates as possible.

Karnaugh maps is a method for simplifying boolean expressions. During the initial phase we
didn’t do the karnaugh maps that’s why our circuit design is somehow a bit messy and a lot of
lines. But the group came up and looked for other possible solutions and we saw how karnaugh
maps are done. That's why we applied it and it looks readable now and traceable compared to
our initial design phase. We also based the logic gates in the Sum of Product (SoP) in order to
check if our logic gates are correct.

As there were 7 inputs needed for the 7-segment display (a, b, c, d, e, f, g), the group decided
to formulate a karnaugh map for each segment such that they are all represented and have their
own SOP expressions for minimal use of gates as they are linked to multiple numbers from 0 to
9.

FINAL DESIGN PHASE – KARNAUGH MAPS

SEGMENT A

Sum of Product: W’X’ + W’Z + XYZ’ + WY’

Verilog: assign A = (~W & ~X) | (~W & Z) | (X & Y & ~Z) | (W & ~Y);

SEGMENT B

Sum of Product: W’Y + WY’ + X’Z’ + W’X

Verilog: assign B = (~W & Y) | (W & ~Y) | (~X & ~Z) | (~W & X);
SEGMENT C

Sum of Product: W’Y’ + W’Z + Y’Z + WYZ’ + XZ’

Verilog: assign C = (~W & ~Y) | (~W & Z) | (~Y & Z) | (W & Y & ~Z) | (X & ~Z);

SEGMENT D

Sum of Product: W’Y + WY’ + W’X’ + XYZ’

Verilog: assign D = (~W & Y) | (W & ~Y) | (~W & ~X) | (X & Y & ~Z);
SEGMENT E

Sum of Product: W’X’ + X’Y’

Verilog: assign E = (~W & ~X) | (~X & ~Y);

SEGMENT F

Sum of Product: W’X’Y’ + WY’Z + W’YZ + WYZ’

Verilog: assign F = (~W & ~X & ~Y) | (W & ~Y & Z) | (~W & Y & Z) | (W & Y & ~Z);
SEGMENT G

Sum of Product: W’Y + WY’ + W’X’Z + YZ’

Verilog: assign G = (~W & Y) | (W & ~Y) | (~W & ~X & Z) | (Y & ~Z);
FINAL DESIGN PHASE – DISPLAY

As the group successfully completed the CircuitVerse design, the following outputs resulting to
the representation of 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9 are as follows:

INPUTS : W – 0; X – 0; Y – 0; Z – 0
OUTPUT : 0
INPUTS : W – 0; X – 1; Y – 0; Z – 0
OUTPUT : 1
INPUTS : W – 0; X – 0; Y – 1; Z – 0
OUTPUT : 2
INPUTS : W – 1; X – 0; Y – 0; Z – 0
OUTPUT : 2
INPUTS : W – 0; X – 1; Y – 1; Z – 0
OUTPUT : 3
INPUTS : W – 1; X – 1; Y – 0; Z – 0
OUTPUT : 3
INPUTS : W – 1; X – 0; Y – 1; Z – 0
OUTPUT : 4
INPUTS : W – 1; X – 0; Y – 1; Z – 0
OUTPUT : 5
INPUTS : W – 0; X – 0; Y – 0; Z – 1
OUTPUT : 6
INPUTS : W – 0; X – 1; Y – 0; Z – 1
OUTPUT : 7
INPUTS : W – 0; X – 0; Y – 1; Z – 1
OUTPUT : 8
INPUTS : W – 1; X – 0; Y – 0; Z – 1
OUTPUT : 8
INPUTS : W – 0; X – 1; Y – 1; Z – 1
OUTPUT : 9
INPUTS : W – 1; X – 1; Y – 0; Z – 1
OUTPUT : 9
INPUTS : W – 1; X – 1; Y – 1; Z – 1
OUTPUT : No Output
INPUTS : W – 1; X – 0; Y – 1; Z – 1
OUTPUT : No Output
FINAL DESIGN PHASE – VERILOG

The group’s Verilog file was initially exported through CircuitVerse, but the exported Verilog code
of such was not compatible with the given test bench, hence, the group utilized the Sum of
Product expressions formulated through the karnaugh mapping of each segment. These SOP
expressions were then converted into Verilog syntax.
module DE1(A, B, C, D, E, F, G, W, X, Y, Z);
input W, X, Y, Z;
output A, B, C, D, E, F, G;

assign A = (~W & ~X) | (~W & Z) | (X & Y & ~Z) | (W & ~Y);
assign B = (~W & Y) | (W & ~Y) | (~X & ~Z) | (~W & X);
assign C = (~W & ~Y) | (~W & Z) | (~Y & Z) | (W & Y & ~Z) | (X & ~Z);
assign D = (~W & Y) | (W & ~Y) | (~W & ~X) | (X & Y & ~Z);
assign E = (~W & ~X) | (~X & ~Y);
assign F = (~W & ~X & ~Y) | (W & ~Y & Z) | (~W & Y & Z) | (W & Y & ~Z);
assign G = (~W & Y) | (W & ~Y) | (~W & ~X & Z) | (Y & ~Z);
endmodule

As there are 4 inputs, 16 total combinations were tested within the testbench, all of which
successfully displayed the right output for each of the 7-segment displays. For instance, 0100
was tested which should result in 0110000.

W = 0;
X = 1;
Y = 0;
Z = 0;
#10
$display("ABCDEFG = %b%b%b%b%b%b%b", A,B,C,D,E,F,G);
#10

After compiling the module and testbench files through: iverilog -o simulation
de1_S12_S17_G77.v de1_S12_S17_G77_tb.v; and running the simulation through vvp
simulation; will give us this result:
CONCLUSION

The initial design of not considering the use of Karnaugh Map made the group
experienced a difficulty in the implementation of the 7 segment display with the 2 1 2 6 input
since what the group did is a lot of AND gates going to a XOR gate and in input we also applied
an inverter for the other lines. Based on the group’s findings, it is not recommended to brute
force the implementation of digital circuits, as it will lead to other bugs. With the help of
Karnaugh Mapping, the 2nd implementation of digital circuit design was efficient and hassle
free, as there were little to no bugs present.