Kingdom of Saudi Arabia ‫ميحرلا نمحرلا هللا مسب‬ ‫ةيدوعسلا ةيبرعلا ةكلمملا‬

Ministry of Education ‫يلاعلا ميلعتلا ةرازو ةيلامشلا‬

Northern Border University ‫دودحلا ةعماج‬
Collage of: Science and Arts Turaif ‫ةيلك‬: ‫فيرط بادآلاو مولعلا‬
Department: Computers &IT ‫مسقلا‬: ‫تامولعملا ةينقتو تابساحلا‬

Second Semester, Academic year 1442-1443 H

Midterm Exam Of: Computer Architecture (1105-323) - Level (5)
Date: 26/8/1443 H –Time: 10:30-12:00 - Room: A107-A108 No of Exam pages including cover: 7

Student’s NAME: .................................. Student’s Number: ...........................

Student
Signature CLOS Mark Question
Degree

Instructions: K2 4 1

1- Read the Question carefully

K1 6 2
2- Answer All the Question
3- Calculator allowed K2 8 3

S3 12 4

30
Nu.

Sum.

Thirty
Letters

Prof. Signature………….

Reviewer Signature …………...

Question 1 : - [6 marks]
Question 1: - Choose the correct answer [4 marks]
1. ……………….is a place where a single item of data can be stored.

(ALU - Control Unit - Registers - CPU)

2- ………is provides commands to the processor, to tell it what it needs to do.

(CISC - RISC - ISA - Pipelining)

3-………………the 'brain' of the computer.

( ALU - Control Unit - Registers - CPU)

4- ………………which performs the calculations on the data.

(ALU - Control Unit - Registers - Clock)

5- …………….is translating mnemonic operation codes to machine code.

(Throughput - Assembler - Compilers - Interpreters)

6- ……………. Used less number of general-purpose register as operation get performed in

memory itself.

(CISC - RISC - ISA - Pipelining)

7- …………… is a group of parallel wires that transfer data from one part of the computer

to another.

(CISC - BUS - CPU - ALU)

8. MIPS is implementation of ………………… architecture.

(CISC - RISC - ISA - Pipelining)

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Question 2: - Write TRUE for true statements and FALSE for false
statements [6 marks]

1 Supercomputers is a Hidden as components of systems.FALSE

2 Assembly language Level of abstraction closer to problem domainFALSE

3 The CISC architecture is Use pipelining to execute instruction.TRUE

4 Elapsed time is the total response time, including all aspects.TRUE

5
The RISC approach attempts to minimize the number of instructions per
program.FALSE
6 Little Endian: Most-significant byte at least address of a word.FALSE

RISC is improving performance by increasing the clock cycles per

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instruction FALSE.

8 The Memory is word addressed.TRUE

9 MIPS architecture has a fixed instruction width (16-bits).FALSE

10 Magnetic disk is an example of a non-volatile secondary memory. TRUE

11 The CISC architecture is simple instructions that execute faster FALSE

12 Performance improved by Increasing clock rate. TRUE

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 Question 3: - [8 marks]
I.Alternative compiled code sequences using instructions in classes A, B, C find [6 Marks]
a. Average CPI for each sequence.
b. CPU time for each sequence assume clock cycle = 10s.
c. MIPS for each sequence?

Class A B C
CPI for class 7 4 6
Instruction count in Millions
Code Sequence 1 5 7 4
Code Sequence 2 9 8 3
(
a) Ans:-………………………. …
……………………………………………………………………………………………
To find the average CPI for each code sequence, you need to divide the total number of instructions in
each class by the instruction count for the code sequence. For example,
…
for code sequence 1 the average CPI would be:
(5 instructions in class A * 7 CPI for class A) + (7 instructions in class B * 4 CPI for class B) + (4
instructions in class C * 6 CPI for class C) / (5 + 7 + 4) = 5.67
…………………………………………….………………………………………………………………………
…
………………………………………………………………..……..……………………………………………
For code sequence 2, the average CPI would be: …
(9 instructions in class A * 7 CPI for class A) + (8 instructions in class B * 4 CPI for class B) + (3 instructions in class C * 6 CPI for…
class C) / (9 + 8 + 3) = 5.67 …
…………………………………………………………………………………..………………………………… …
.………………………………………………………………………………………………………………………
(b) Ans:- …
…
To find the CPU time for each code sequence, you need to multiply the average CPI by the instruction count and the clock cycle
time. For example, …
for code sequence 1 the CPU time would be: …
(5.67 average CPI * 5 instructions) * 10 seconds/cycle = 283.5 seconds
…
For code sequence 2, the CPU time would be: …
(5.67 average CPI * 9 instructions) * 10 seconds/cycle = 510.3 seconds
…
…………………………………………………………………………………….………………………………
…
……………………………………………………………..………………………………………………………
…
c) Ans :-
…
To find the MIPS for each code sequence, you need to divide the instruction count by the CPU time.
For example,
for code sequence 1 the MIPS would be:

4
5 instructions / 283.5 seconds = 0.0177 MIPS

For code sequence 2, the MIPS would be:

9 instructions / 510.3 seconds = 0.0176 MIPS
……………………………………………………………………………………………………………………
……………………………………………………………………………………………………………………
……………………………………

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II. A Program is running on a specific machine with the following parameters: CPU clock cycle
is 20 ns and the program takes 80 million cycle to execute what is the CPU time? [2 Marks]

…Ans a. If the CPU clock cycle is 20 ns and the program takes 80 million cycles to execute, the CPU
time is 20 ns * 80 million cycles = 1600 million ns = 1600 ms.
…
………………………………………………………………………………………………………………………
…

Question 4: - [12 marks]

I. Represent the following MIPS instruction at the encoding formats [2 Marks]
C CODE:
Int Z=ox ACDE25A7
……………………………………………………………………………………..……..…………………
…… The MIPS instruction "Int Z=(ox)ACDE25A7" could be represented in the following encoding
formats:
 Assembly: lui $z, 0xACDE ori $z, $z, 0x25A7
 Machine code (binary): 001111 00000 101011001101111010
0010110110100111
…………………………………………………………………………………………..……………
………………………………………………………………………………………………………………
II. Show how this word would be stored in the memory below (Use Big Endian &little
Endian) representation? [1 Marks]
OX (0A 6B D7 98)
Memory Address 32 36 40 44

Byte Contents (Big Endian)

Byte Contents (little Endian)

Using big endian representation, the word "Int Z=(ox)ACDE25A7" would be stored in memory as
follows:
Memory Address 32 36 40 44

Byte Contents(Big
0xAC 0xDE 0x25 0xA7
Endian)

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 Byte Contents(little
0xA7 0x25 0xDE 0xAC
Endian)

III

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 III. Represent the following MIPS instruction at the encoding formats [9 Marks]

Sub $t6, $S1, $S6

Sw $t6, 32($S4)
ADDi $S3, $t6,35
Beq $S3, $t6,4
Srl $S5, $S3,4
J 200
……………………………………………………………………………………..……..…………………
…………………………………………………………………………………………………..……………
.…… Encoding formats for the given MIPS instructions:

1. Sub $t6, $S1, $S6

This instruction performs a subtraction operation on the values in registers $S1 and $S6, and stores the result in register $t6. It is
an R-format instruction, which means that it has the following fields:

1. opcode: specifies the type of instruction (all R-format instructions have an opcode of 0)
2. rs: specifies the first source register operand (in this case, $S1)
3. rt: specifies the second source register operand (in this case, $S6)
4. rd: specifies the destination register (in this case, $t6)
5. shamt: specifies a shift amount (not used in this instruction)
6. funct: specifies the function code for the instruction (in this case, 34, which represents the sub instruction)
The resulting 32-bit encoding for this instruction would be: 0 17 22 14 0 34
…………………………………………………………………………………………………………
………………………………………………………………………….……………………………………
2. Sw $t6, 32($S4)
This instruction stores the value in register $t6 at the memory location specified by the address in register $S4 plus an offset of 32. It
is an I-format instruction, which means that it has the following fields:

1. opcode: specifies the type of instruction (in this case, 43, which represents the
sw instruction)
2. rs: specifies the source register (in this case, $t6)
3. rt: specifies the destination register (in this case, $S4)
4. immediate: specifies an immediate value (in this case, 32)
………………………………………………………..………………………………………………………
The resulting 32-bit encoding for this instruction would be: 43 22 20 32

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…… 3. ADDi $S3, $t6,35

This instruction performs an addition operation on the value in register $t6 and the immediate value
35, and stores the result in register $S3. It is an I-format instruction, which means that it has the
following fields:

 opcode: specifies the type of instruction (in this case, 8, which represents
the addi instruction)
 rs: specifies the first source register operand (in this case, $t6)
 rt: specifies the destination register (in this case, $S3)
 immediate: specifies an immediate value (in this case, 35)
…………………………………………………………………………………………………………
The resulting 32-bit encoding for this instruction would be: 8 22 19 35
………………………………………………………………………………………………………..………
………………………………………………………………………………………………………………
4. Beq $S3, $t6,4

This instruction performs a branch operation if the values in registers $S3 and $t6 are equal. If the values are equal, the program
counter is updated to the target address specified by the immediate value (in this case, 4). It is an I-format instruction, which means
that it has the following fields:

 opcode: specifies the type of instruction (in this case, 4, which represents the beq instruction)
 rs: specifies the first source register operand (in this case, $S3)
 rt: specifies the second source register operand (in this case, $t6)
 immediate: specifies an immediate value (in this case, 4)
………………………………………………………………………………………………………………
The resulting 32-bit encoding for this instruction would be: 4 19 22 4
……………………………………………………………………………………..……..…………………
………………………………………………………………………………………………………………
.………………………………………………………………………………………………………………
5. Srl $S5, $S3,4

This instruction performs a logical right shift on the value in register $S3 by the shift amount specified in the immediate field (in
this case, 4), and stores the result in register $S5. It is an R-format instruction, which means that it has the following fields:

 opcode: specifies the type of instruction (all R-format instructions have an opcode of 0)
 rs: specifies the source register (in this case, $S3)
 rt: specifies the destination register (in this case, $S5)
 rd: specifies a destination register (not used in this instruction)
 shamt: specifies a shift amount (in this case, 4)
 funct: specifies the function code for the instruction (in this case, 2, which represents the srl
instruction)
……………………………………………………….………………………………………………………
The resulting 32-bit encoding for this instruction would be: 0 19 20 0 4 2
……………………………………..…………………………………………………………………………
………………………………………………………………………………………………………………
……………………………………………………………………………………..…………………………
………………………………………………………………………………………………………………

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.… 6. J 200

The MIPS instruction "J 200" is a jump instruction that updates the program counter to the target
address specified in the instruction (in this case, 200). It is a J-format instruction, which means that it
has the following fields:

 opcode: specifies the type of instruction (in this case, 2, which represents
the j instruction)
 address: specifies the target address of the jump (in this case, 200)
……………………………………………………………………………………………………………
The resulting 32-bit encoding for this instruction would be: 2 200

When this instruction is executed, the program counter is set to the target address specified in the
instruction, and execution continues at that address
…………………………………………………………………………….…………………………………
…………………………………………………………..……………………………………………………
Here is a summary of the encoding of the given MIPS instructions:

1. Sub $t6, $S1, $S6: 0 17 22 14 0 34 (R-format instruction)

2. Sw $t6, 32($S4): 43 22 20 32 (I-format instruction)
3. ADDi $S3, $t6,35: 8 22 19 35 (I-format instruction)
4. Beq $S3, $t6,4: 4 19 22 4 (I-format instruction)
5. Srl $S5, $S3,4: 0 19 20 0 4 2 (R-format instruction)
6. J 200: 2 200 (J-format instruction)
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With my Best Wishes

Lec. DoaaMohammed