Efficient Time-Domain In-Memory Computing

Based on TST-MRAM
Jinkai Wang∗, Yue Zhang∗†, Chenyu Lian∗, Yining Bai∗, Zhe Huang∗, Guanda Wang∗, Kun Zhang∗,
Youguang Zhang∗ and Weisheng Zhao∗†
Email: [email protected]
∗
Fert Beijing Institute, School of Microelectronics, BDBC, Beihang University, Beijing, China, 100191
†
Nanoelectronics Science and Technology Center, Hefei Innovation Research Institute, Beihang
University, Hefei, China, 230013

Abstract—In-memory computing is highly promising to their low power consumption, high density and good
address the processor-memory data transfer bottleneck in compatibility with existing CMOS technology [10]-[14].
current computational paradigm. We firstly propose a time- Among the NVM technologies, spin transfer torque magnetic
domain in-memory computing (TIMC) scheme based on high- random access memory (STT-MRAM), a representative of
speed low-power toggle spin torque random access memory spintronic memories, is one of the most promising
(TST-MRAM). The difference of voltage drops of bitline alternatives. The authors in [15] have proposed STT
caused by simultaneously-activated bit-cells is reflected to time computing-in-memory (STT-CiM) structure, in which a
domain. Reconfigurable logic operations can be performed by
modification for peripheral circuits of STT-MRAM
utilizing D flip-flops (DFFs) to record the outputs at different
leverages simultaneously-enabled multiple wordlines to
moments. In order to demonstrate the advantages of this
scheme in terms of speed and energy consumption, an efficient
perform logic, arithmetic and complex vector operations.
multi-digit addition circuit has been designed and analyzed. Computational RAM (CRAM) proposed in [16] implements
Compared with existing IMC schemes, such as spin-transfer an IMC paradigm that performs addition and multiplication
torque computing-in-memory (STT-CiM) structure, up to 67% within the memory array. However, STT-MRAM still suffers
energy saving and 10 times delay improvement can be achieved from long writing delay and high writing current, leading to
in the case of four-digit addition by using TIMC scheme. relatively high energy consumption. Although there are other
spintronic IMC concepts, such as a multi-regulated
Keywords—In-memory computing, Time-domain, Toggle reinforced magnetoresistive device implementing 15
spin torque MRAM, Multi-digit addition. Boolean logic functions [14] and a single perpendicularly
magnetized trilayer device integrating five typical Boolean
I. INTRODUCTION logic gates, their technical maturity is debatable.
The development of emerging applications, such as Toggle spin torque MRAM (TST-MRAM) was recently
automatic pilot and internet of things (IoT), etc., puts designed to solve the above problems of STT-MRAM [17].
forward a series of performance demands for computing Writing delay and current can be considerably improved due
system [1]-[3]. The current computing platforms are mainly to large spin-orbit coupling (SOC). In this paper, we propose
based on Von-Neumann architecture in which data are stored a time-domain IMC (TIMC) scheme based on TST-MRAM.
in the memory units and processed in the processing units The characteristic of spintronic memories allows multiple
separately. In execution phase, the processor fetches data bit-cells in a column to be simultaneously-activated and
from memory units via buses according to the instruction, sense the effective resistance on bitline, which makes it
and writes the results back after the computation is possible to directly compute logic functions of the data
completed [4]. Although the separation of memory unit and stored in the bit-cells. Based on this method, we utilize
processing unit has improved the computing ability, this fact multiple D flip-flops (DFFs) to record the outputs of inverter
suffers from long memory access latency which is limited by connected to the bitline at different moments to implement
the memory bandwidth. Besides, the frequent data transfer the basic Boolean logic. According to the feature of the data
between memory and processor causes huge power recorded by the DFFs at different moments, we construct a
consumption in Von-Neumann architecture [5], [6]. peripheral circuit to achieve efficient addition operation of
multiple digits. Simulation results show that TIMC structure
To address the above issues, in-memory computing (IMC) can perform basic Boolean logic and multi-digit addition
concept has been intensively investigated, which is a within 1.2 ns. For example, it achieves 1.1ns and 1.05ns
hardware design embedding logic into memory array. IMC respectively in the cases of three-digit and four-digit
can effectively reduce memory-processor data transfers, additions. Compared to the STT-CiM structure, the TIMC
allowing constructing a more energy-efficient information structure can reduce 67% energy consumption when
processing platform. There are several technologies to implementing four-digit addition.
perform logic in CMOS-based memories, such as static
random access memory (SRAM) and dynamic random The rest of this paper is organized in the following
access memory (DRAM) [7], [8]. However, these structure. Section II describes the approach to realize basic
conventional memories are volatile memories that normally Boolean logic, such as NAND, NOR and XOR. Section III
require considerable area and power consumption. Moreover, designs multi-digit addition operation. Section IV presents
as technology nodes scaling down, CMOS technology faces circuit and system simulation results, which demonstrates the
a serious challenge of leakage current [6], [9]. Recently, delay, reliability and energy of the proposed TIMC structure.
emerging non-volatile memory (NVM) technologies are Section V concludes this paper.
attractive solutions for building IMC platform. Thanks to

978-1-7281-3320-1/20/$31.00 ©2020 IEEE

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 II. TIME-DOMAIN IN-MEMORY COMPUTING STRUCTURE voltage drops can occur on RBL0. In order to distinguish the
TST-MRAM bit-cell consists of three transistors and a three different voltage drops, an inverter is connected to
magnetic tunnel junction (MTJ) with heavy metal (HM) RBL0. The output of inverter is low voltage until RBL0
layer, as shown in Fig. 1. There are three bitlines (BL, RBL, voltage is discharged to the threshold voltage of NMOS
CBL) and three wordlines (WL, RWL, CWL). In writing transistor. The variation of RBL0 voltage drop causes the
operation, the spin orbit torque (SOT) current firstly flows inversion of output voltage at different moments. Fig. 3 (a),
through HM to form in-plane magnetization in free layer due (b) and (c) show the inversion of inverter output voltage in
to spin-hall-effect (SHE). Another STT current is injected three configurations of the two bit-cell data. Reading the
into MTJ, which determines the state of MTJ: the current inverter output at two moments can distinguish the data
flowing from free layer (FL) to pinned layer (PL) writes “0” stored in two bit-cells on the RBL0. Instead of sense
(low resistance, RP), and opposite current writes “1” (high amplifier, we utilize two DFFs (DFF0 and DFF1) to record
resistance, RAP) [18]-[20]. At the beginning of reading the inverter outputs at two moments, which is more efficient
operation, BL will be pre-charged to high voltage. Two cases due to no reference voltage required. Fig. 3 (f), (g) and (h)
of effective resistance on BL are generated when a bit-cell is show the three possible outputs of two DFFs corresponding
activated. Its variation reflects the logical relationship among to three effective resistance cases.
simultaneously-activated bit-cells. In addition, as the
effective resistance has an effect on the voltage drop of BL,
the logical relationship can be explored through detecting the
voltage drop of BL in time-domain.

Fig. 1. TST-MRAM bit-cell structure.

Fig. 3. Transient simulation results of TIMC structure. (a) RBL0 and the
output of inverter in ‘11’ case. (b) RBL0 and the output of inverter in
‘01/10’ case. (c) RBL0 and the output of inverter in ‘00’ case. (d) CP0. (e)
CP1. (f) outputs of DFF0 and DFF1 in ‘11’ case. (g) outputs of DFF0 and
DFF1 in ‘01/10’ case. (h) outputs of DFF0 and DFF1 in ‘00’ case.

The output results of two DFFs are listed in Table I. It is

obvious that the output D0 of DFF0 represents a NOR gate
Fig. 2. Proposed TIMC structure. and the output D1 of DFF1 represents a NAND gate. Based
on the feature of DFF outputs, a circuit to implement XOR
Fig. 2 shows the schematic of proposed TIMC circuit. logic operation is designed, as shown in Fig. 2. When D0 and
Firstly, the pre-charged bitline RBL0 is discharged through D1 are both ‘0’ or ‘1’, the pull-up channel is turned off and
two simultaneously-activated bit-cells. In the discharged one of the two pull-down channels is turned on, which
channel of RBL0, the MTJs in two bit-cells are connected in causes the voltage of node N drops to low voltage. When
parallel, which leads to three possible states for effective D0= ‘0’ and D1= ‘1’, node N is high voltage because the pull-
resistance of two MTJs. Correspondingly, three different up channel is turned on and both of the two pull-down

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 channels are turned off. In summary, NOR, NAND and XOR Based on above analysis, in n-digit addition, the number
logic operations can be achieved through one discharge of of simultaneously-activated bit-cells in the circuit is 2n-1.
bitline in TIMC circuit. According to the characteristics of TIMC structure, there are
2n cases of effective resistance. Therefore, 2n-1 DFFs are
III. EFFICIENT MULTI-DIGIT ADDITION needed to record the output of inverter at 2n-1 moments. The
overall circuit structure is demonstrated in Fig. 5. The
outputs of 2n-1 DFFs also have 2n cases, which can be
classified according to the number of the data ‘1’ stored in
bit-cells. When computing the sum S, XOR operation is
firstly performed for the inverse of two DFF outputs. Note
that, the inverse of the last DFF output does not need to
implement XOR operation and it can be directly used as an
input in the next stage operation. S can then be calculated by
carrying out OR operation for all the outputs from the
previous stage. Summation formula can be written as

S = ( D0 XOR D1 ) OR ( D2 XOR D3 )
Fig. 4. Principle of carry for multi-digit addition: (a) three-digit addition; (1)
(b) four-digit addition. ... OR( D2 n-4 XOR D2 n-3 )OR D2 n-2
The efficiency of processing appertains to the The n-1 carries are obtained by performing XOR operation
performance of the arithmetic and logic units, such as adders, for the inverse of adjacent even bit DFF outputs. Similarly,
multipliers and dividers [21]. Due to the fundamental role of the highest carry comes from the output of penultimate DFF.
addition in all arithmetic operations, the design of addition Carries can be expressed as
operation is especially crucial [22]. Fig. 4 illuminates the
carry principle of multi-digit addition. M represents the order
of magnitude in binary numbers and M0 is the lowest order Ci = D1 XOR D3
of magnitude. Fig. 4 (a) shows the three-digit addition
Ci +1 = D5 XOR D7
operation. As three bits are added together in M0, a carry will
be produced as an input for M1 if there are more than two ‘1’ …
in M0. In this case, four bits are added in M1. If these bits are
all ‘1’, there will be a carry for M3. At the same time, it is Ci + n-3 = D2 n-5 XOR D2 n-7
also possible that M2 generates a carry for M3. This will lead
Ci + n -2 = D2 n-3 (2)
to two carries as inputs for M3. Therefore, two carries as
additional inputs are required to be considered in the three-
digit addition. The similar mechanism can be given for four-
digit addition, as shown in Fig. 4 (b). Three carries as
additional inputs are required to be included for the four-digit
addition. And so on, there will be n-1 carries considered in n-
digit addition.

Fig. 6. Transient simulation results of full-adder based on TIMC structure.

(a) case ‘000’. (b) case ‘001/010/100’. (a) case ‘011/101/110’. (b) Ccase
‘111’.

We choose the full-adder as an example to explain the

multi-digit addition more clearly. As full-adder has two data
and a carry, three bit-cells in the same column are needed for
storing the data. Three DFFs are thus used to record the
output of inverter at three moments. From equations (1) and
(2), S can be obtained by performing XOR and OR
operations for the inverse of three DFF outputs, and the carry
is the inverse of DFF1 output. Fig. 6 shows the transient
Fig. 5. Circuit structure of multi-digit addition.
results of S and carry in four possible configurations for full-
adder based on TIMC structure. It can be found that the

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 computational complexity of full-adder is effectively reduced phenomenon is more obvious in Fig.7 (b), which shows all
in TIMC structure. Besides, in traditional processors, the possible cases of inverter output for three-digit addition.
addition operation of multiple digits is always achieved Therefore, in order to make multi-digit addition more reliable,
through connecting or cascading a series of full-adders. The it is necessary to improve the time difference in the future
summation also requires numbers of iterations. The proposed work.
multi-digit addition is completed in one discharge course of
bitline, which can greatly improve the efficiency of addition
operation by reducing the amount of computing iteration and
delay time.

IV. EVALUATION AND DISCUSSION

TIMC structure adopts hybrid CMOS/TST-MRAM
design, where the variation of bitline voltage drop in TST-
MRAM array is leveraged to perform logic operations
through certain peripheral CMOS circuit. This method is
extensively recognized in IMC platform designs due to the
combination of the strengths of spintronic memory and
CMOS circuit. In order to demonstrate the advantage of our
proposed TIMC scheme in terms of delay and energy
consumption, we compare it with STT-CiM, an existing
hybrid CMOS/STT-MRAM IMC design. To fairly compare
the performance between these two designs, we analyze
them in the same simulation environment. The 28nm CMOS
process, compact models of STT-MRAM and TST-MRAM
[17], [18] are used in the SPICE simulations. Table II shows
the comparisons between TIMC and STT-CiM in terms of
delay and energy consumption for different logic functions.
STT-CiM structure requires multiple iterations through full-
adder to perform multi-digit addition. In each iteration, the
results of full-adder needed writing back into bit-cells for the
next full-adder. Therefore, compared to TIMC structure, both
delay and energy consumption of STT-CiM structure are
obviously higher. For basic Boolean logic and full-adder
operation, the performance of TIMC structure is also
superior to STT-CiM due to the fewer control signals and no Fig. 7. Monte-Carlo simulations for inverter outputs of all possible cases.
need of reference voltages. Besides, the delay of multi-digit (a) Full-adder. (b) Three-digit addition operation.
addition gradually decreases with the increase of bit number
in TIMC structure. The reason of this phenomenon is that the
simultaneously-activated bit-cells are connected in parallel. V. CONCLUSION
The more bit-cells in parallel is, the smaller the effective
resistance will be, which causes faster voltage drop of bitline. This work focuses on a TIMC scheme based on TST-
MRAM. Compared with STT-MRAM, TST-MRAM
provides faster magnetization switching and lower power
consumption. Logical relationship relying on the variation of
voltage drop of bitline can be reflected to time domain.
Different logic operations can then be implemented by
detecting the data stored in DFFs at different moments. An
efficient multi-digit addition circuit based on the proposed
TIMC scheme is proposed and simulated. The evaluation
results show that the proposal greatly improve the speed and
energy consumption performance compared with the existing
IMC structure. This work blazes an alternative path for
realizing IMC and will inspire more innovative designs for
future computing systems.

ACKNOWLEDGMENT
The reliability of TIMC structure will decrease as the
number of simultaneously-activated bit-cells increases. Fig. 7 This work was supported in part by the National Natural
shows the 1000 Monte Carlo results of the inverter output of Science Foundation of China (Grant No. 61971024 and
full-adder and three-digit addition, respectively. Compared to 51901008), Young Elite Scientist Sponsorship Program by
full-adder, the time differences between inversion moments CAST (Grant No. 2017QNRC001), the International
of inverter output for two adjacent cases are smaller in three- Mobility Project (Grant No. B16001) and National Key
digit addition. Moreover, the time difference between ‘000’ Technology Program of China (Grant No.
case and ‘001’ case (ΔT0) in full-adder is the smallest 2017ZX01032101).
compared with other cases as shown in Fig. 7 (a). This

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 REFERENCES [11] S. Angizi, Z. He, N. Bagherzadeh and D. Fan, “Design and
Evaluation of a Spintronic In-Memory Processing Platform for
[1] M. Kang, S. Lim, S. Gonugondla and N. R. Shanbhag, “An In- Nonvolatile Data Encryption,” IEEE Transactions on Computer-
Memory VLSI Architecture for Convolutional Neural Networks,” Aided Design of Integrated Circuits and Systems, vol. 37, no. 9, pp.
IEEE Journal on Emerging and Selected Topics in Circuits and 1788-1801, 2018.
Systems, vol. 8, no. 3, pp. 494-505, 2018.
[12] G. D. Wang et al., “Ultra-Dense Ring-Shaped Racetrack Memory
[2] M. Kang and N. R. Shanbhag, “In-Memory Computing Architectures Cache Design,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 66, no.
for Sparse Distributed Memory,” IEEE Journal on Emerging and 1, pp. 215-225, 2019.
Selected Topics in Circuits and Systems, vol. 10, no. 4, pp. 494-505,
2016. [13] Z. Z. Zhang, Y. Z. Zhu, Y. Zhang, K. Zhang, J. Nan, Z. Y. Zheng, Y.
G. Zhang, W. S. Zhang, “Skyrmion-based Ultra-low Power Electric-
[3] W. H. Chen, K. X. Li, W. Y. Lin, K. H. Hsu, P. Y. Li, C. H. Yang, C. field-controlled Reconfigurable (SUPER) Logic Gate,” IEEE Electron
X. Xue, E. Y. Yang, Y. K. Chen, Y. S. Chang, T. H. Hsu, Y. C. King, Device Letters, vol. 40, no. 12, pp. 1984-1987, 2019.
C. J. Lin, R. S. Liu, C. C. Hsieh, K. T. Tang and M. F. Chang, “A
65nm 1Mb nonvolatile computing-in-memory ReRAM macro with [14] K. Zhang, Y. Zhang, Z. Z Zhang, Z. Y Zheng, G. D Wang, Y. G
sub-16ns multiply-and-accumulate for binary DNN AI edge Zhang, Q. W Liu, S. S Yan and W. S Zhao, “Large Magnetoresistance
processors,” IEEE International Solid-State Circuits Conference and 15 Boolean Logic Functions Based on a ZnCoO Film and Diode
(ISSCC), San Francisco, CA, USA, 2018, pp. 494-495. Combined Device,” Advanced Electronic Materials, vol. 5, no. 3, pp.
1800812, 2019.
[4] Y. Zhang, C. Zhang, J. Nan, Z. Zhang, X. Zhang, J.-O. Klein, D.
[15] S. Jain, A. Ranjan, K. Roy and A. Raghunathan, “Computing in
Ravelosona, G. Sun, and W. Zhao, “Perspectives of racetrack memory
Memory with Spin-Transfer Torque Magnetic RAM,” IEEE
for large-capacity on-chip memory: From device to system,” IEEE
Transactions on Very Large Scale Integration (VLSI) Systems, vol.
Transactions on Circuits and Systems I: Regular Papers, vol. 63, no.
26, no. 3, pp. 470-483, 2018.
5, pp. 629–638, 2016.
[5] P. Chi, S. Li, Z. Qi, P. Gu, C. Xu, T. Zhang, J. Zhao, Y. Liu, Y. [16] M. Zabihi, Z. I. Chowdhury, Z. Zhao, Ul. R. Karpuzcu, J. P. Wang
Wang, and Y. Xie, “Prime: A novel processing-in-memory and S. S. Sapatnekar, “In-Memory Processing on the Spintronic
architecture for neural network computation in reram-based main CRAM: From Hardware Design to Application Mapping,” IEEE
memory,” ACM/IEEE 43rd Annual International Symposium on Transactions on Computers, vol. 68, no. 8, pp. 1159-1173, 2019.
Computer Architecture (ISCA), Seoul, South Korea, 2016, pp. 27-39. [17] Z. H. Wang, H. C. Zhou, M. X. Wang, W. L. Cai, D. Q. Zhu, J. O.
[6] Y. Wang, H. Yu, L. Ni, G. B. Huang, M. Yan, C. Weng, W. Yang and Klein and Weisheng Zhao, “Proposal of Toggle Spin Torques
J. Zhao, “An Energy-Efficient Nonvolatile In-Memory Computing Magnetic RAM for Ultrafast Computing,” IEEE Electron Device
Architecture for Extreme Learning Machine by Domain-Wall Letters, vol. 40, no. 5, pp. 726-729, 2019.
Nanowire Devices,” IEEE Trans. Nanotechnology, vol. 14, no. 6, pp. [18] Y. Zhang, B. Yan, W. Kang, Y. Q. Cheng, J. O. Klein, Y. G. Zhang,
998-1012, 2015. Y. R. Chen and W. S. Zhao, “Compact Model of Subvolume MTJ and
[7] J. Zhang, Z. Wang and N. Verma, “In-Memory Computation of a Its Design Application at Nanoscale Technology Nodes,” IEEE
Machine-Learning Classifier in a Standard 6T SRAM Array,” IEEE Transactions on Electron Device, vol. 62, no. 6, pp. 2048-2055, 2015.
Journal of Solid-State Circuits, vol. 52, no. 4, pp. 915-924, 2017. [19] Z. Y. Zheng et al., “Enhanced Spin-Orbit Torque and Multilevel
[8] A. Agrawal, A. Jaiswal, C. Lee and K. Roy, “X-SRAM: Enabling In- Current-Induced Switching in W / Co − Tb / Pt Heterostructure,”
Memory Boolean Computations in CMOS Static Random Access Phys. Rev. Applied, vol. 12, no.4, pp. 044032, 2019.
Memories,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 65, no. 12, [20] G. D. Wang et al., “Compact Modeling of Perpendicular-Magnetic-
pp. 4219-4232, 2018. Anisotropy Double-Barrier Magnetic Tunnel Junction with Enhanced
[9] M. Natsui, D. Suzuki, N. Sakimura, R. Nebashi, Y. Tsuji, A. Thermal Stability Recording Structure,” IEEE Transactions on
Morioka, T. Sugibayashi, S. Miura, H. Honjo, K. Kinoshita, S. Ikeda, Electron Devices, vol. 66, no.5, pp. 2431-2436, 2019.
T. Endoh, H. Ohno and T. Hanyu, “Nonvolatile Logic-in-Memory [21] H. Naseri and S. Timarchi, “Low-Power and Fast Full Adder by
LSI Using Cycle-Based Power Gating and its Application to Motion- Exploring New XOR and XNOR Gates,” IEEE Transactions on Very
Vector Prediction”, IEEE Trans. Nanotechnology, vol. 50, no. 2, pp. Large Scale Integration (VLSI) Systems, vol.26, no. 8, pp. 1481-
476-489, 2015. 1493, 2018.
[10] M. A. Lebdeh, H. Abunahla, B. Mohammad and M. Al-Qutayri, “An [22] H. T. Bui, Y. Wang and Y. Jiang, “Design and analysis of low-power
Efficient Heterogeneous Memristive XNOR for In-Memory 10-transistor full adders using novel XOR-XNOR gates,” IEEE
Computing,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 64, no. 9, Transactions on Circuits and Systems II: Analog and Digital Signal
pp. 2427-2437, 2017. Processing, vol. 49, no. 1, pp. 25-30, 2002.

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