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Lecture30 Ee689 Cdrs

The document discusses Clock and Data Recovery (CDR) circuits. It provides an overview of CDRs and describes different types of CDR phase detectors including: 1) Hogge phase detector which is linear and provides both phase error sign and magnitude information. 2) Alexander (2x-oversampled) phase detector which is non-linear and only provides phase error sign information. 3) Oversampling phase detectors which use multiple clock phases to sample data and can have multiple output levels to detect rate of phase change.

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Ranvir Singh
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50 views21 pages

Lecture30 Ee689 Cdrs

The document discusses Clock and Data Recovery (CDR) circuits. It provides an overview of CDRs and describes different types of CDR phase detectors including: 1) Hogge phase detector which is linear and provides both phase error sign and magnitude information. 2) Alexander (2x-oversampled) phase detector which is non-linear and only provides phase error sign information. 3) Oversampling phase detectors which use multiple clock phases to sample data and can have multiple output levels to detect rate of phase change.

Uploaded by

Ranvir Singh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 21

ECEN689: Special Topics in High-Speed

Links Circuits and Systems


Spring 2010

Lecture 30: CDRs

Sam Palermo
Analog & Mixed-Signal Center
Texas A&M University
Announcements
• Project Preliminary Report #2 due Monday
April 26 in class
• Exam 2 is April 30
• Posted Fwd Clock Bandpass Filtering Paper
• Will Post
• CDR Papers
• Example PLL models

2
Agenda
• CDR overview
• CDR Phase Detectors
• Analog & Digital CDRs

3
Embedded Clock I/O Circuits
• TX PLL

• TX Clock Distribution

• CDR
• Per-channel PLL-based
• Dual-loop w/ Global PLL &
• Local DLL/PI
• Local Phase-Rotator PLLs
• Global PLL requires RX
clock distribution to
individual channels

4
Embedded Clocking (CDR)
PLL-based CDR Dual-Loop CDR
VCTRL Frequency 800MHZ
CP PFD Ref Clk
Synthesis
VCO PLL Vctrl
4
ΦPLL[0]

5-stage coupled VCO


Σ ΦPLL[4:0] ΦPLL[4:0]
proportional
ΦRX[n:0]
(3.2GHz)
gain
5:1 5:1
5 Mux/ MUX MUX 10

Din RX CP
integral
gain
Interpolator
Pairs 15

PD early/ Ψ[4:0]
late early/
RX late sel
FSM
Loop Filter (16Gb/s) PD
Phase-Recovery Loop
• Clock frequency and optimum phase position are extracted from incoming data
• Phase detection continuously running
• Jitter tracking limited by CDR bandwidth
• With technology scaling we can make CDRs with higher bandwidths and the jitter tracking
advantages of source synchronous systems is diminished
• Possible CDR implementations
• Stand-alone PLL
• “Dual-loop” architecture with a PLL or DLL and phase interpolators (PI)
• Phase-rotator PLL
5
CDR Phase Detectors
• CDR phase detectors compare the phase between the input
data and the recovered clock sampling this data and
provides information to adjust the sampling clocks’ phase
• Phase detectors can be linear or non-linear
• Linear phase detectors provide both sign and magnitude
information regarding the sampling phase error
• Hogge

• Non-linear phase detectors provide only sign information


regarding the sampling phase error
• Alexander or 2x-Oversampled or Bang-Bang
• Oversampling (>2)
• Baud-Rate
6
Hogge Phase Detector
Late

Early

[Razavi]
Late

(Late – Early) Early

[Lee] “1” Average Output • Linear phase detector


Amplitude
• For phase transfer 0rad is w.r.t
optimal Tb/2 spacing between
sampling clock and data
• φe = φin - φclk
• TD is the transition density – no
transitions, no information
= (TD )
1
K PD
“-1” Average Output π • A value of 0.5 can be assumed for
Amplitude random data 7
Hogge Phase Detector Nonidealities
Late

Early

[Razavi]
Late

• Flip-Flop Clk-to-Q delay widens Late pulse, but doesn’t


impact Early pulse
• CDR will lock with a phase shift to equalize to Early and
Late pulse widths
8
Hogge Phase Detector Nonidealities

Late

Early

[Razavi]

• CDR phase shift compensated with a dummy delay element


• Other issues:
• Need extremely high-speed XOR gates
• Phase skew between Early and Late signals induces a “triwave”
disturbance (ripple) on the control voltage
9
Alexander (2x-Oversampled) Phase Detector
• Most commonly used CDR phase detector
• Non-linear (Binary) “Bang-Bang” PD
• Only provides sign information of phase
error (not magnitude)
• Phase detector uses 2 data samples and
one “edge” sample
• Data transition necessary
En
Dn ⊕ Dn +1
• If “edge” sample is same as second
bit (or different from first), then the
clock is sampling “late”
En ⊕ Dn En
• If “edge” sample is same as first bit
(or different from second), then the
clock is sampling “early”
En ⊕ Dn +1
[Sheikholeslami]
10
Alexander Phase Detector Characteristic
(No Noise)
(Late – Early)

[Lee]

• Phase detector only outputs phase error sign information in


the form of a late OR early pulse whose width doesn’t vary
• Phase detector gain is ideally infinite at zero phase error
• Finite gain will be present with noise, clock jitter, sampler
metastability, ISI
11
Alexander Phase Detector Characteristic
(With Noise)
• Total transfer
characteristic is the
convolution of the ideal
PD transfer characteristic
and the noise PDF
• Noise linearizes the
phase detector over a
phase region
corresponding to the [Lee]
peak-to-peak jitter
K PD ≈
2
(TD )
J PP Output
“1” Average
Pulse Width
Output Amplitude
• TD is the transition density –
no transitions, no information
• A value of 0.5 can be
assumed for random data “-1” Average Output
Output Amplitude Pulse Width
12
Oversampling Phase Detectors

[Sheikholeslami]

• Multiple clock phases are used to sample incoming data bits


• PD can have multiple output levels
• Can detect rate of phase change for frequency acquisition
13
Mueller-Muller Baud-Rate Phase Detector
“1”
• Baud-rate phase detector
[Musa]
only requires one sample
clock per symbol (bit)

“-1” “-1”
• Mueller-Muller phase
detector commonly used

• Attempting to equalize the


amplitude of samples taken
before and after a pulse

14
Mueller-Muller Baud-Rate Phase Detector

[Spagna ISSCC 2010]


15
Analog PLL-based CDR

“Linearized” KPD

[Lee]

16
Analog PLL-based CDR

[Lee]

• CDR “bandwidth” will vary with input phase variation


amplitude with a non-linear phase detector
• Final performance verification should be done with a
time-domain non-linear model
17
Digital PLL-based CDR

[Sonntag JSSC 2006]


18
Digital PLL-based CDR

Open-Loop Gain:

[Sonntag JSSC 2006]


19
Digital PLL-based CDR

[Sonntag JSSC 2006]


20
Next Time
• CDR circuits

21

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