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Chapter VI: Generate and Process Statements

• In this chapter, we will cover the following topics:

– The generate statement.

– The if/generate statement.

– Sequential assignment and the process statement.

– The if-then-else statement.

– The case statement.

– Examples.

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Generate Statement:
• Previously, we implemented a 16:1 multiplexer using
five instances of the 4:1 multiplexer.
• The structure of the code suggests that a loop
would make the code more compact.
• In programming, there are two types of loops:
conditional and unconditional.
• The syntax of an unconditional generate statement
in VHDL is:
<label>:
for <parameter> in <range> generate
<concurrent statements>;
end generate;
• The label is compulsory.
• Instance names do not require an index.
• Nested generate statements are allowed in VHDL.
Digital Design II (EE411) | Dr. Samir Bendoukha
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Example 1: 16-Bit Ripple Adder

library IEEE;
use IEEE.std_logic_1164.all;
entity Adder16 is
port(ci: in STD_LOGIC;
X,Y: in STD_LOGIC_VECTOR(0 to 15)
S: in STD_LOGIC_VECTOR(0 to 16));
end Adder16;
architecture behavior of Adder16 is
signal C: STD_LOGIC_VECTOR(0 to 16);
component FA is
port(ci,x,y: in STD_LOGIC;
s,co: out STD_LOGIC);
end component;
begin
C(0) <= ci;
G1: for i in 0 to 15 generate
FAs: FA port map (C(i),X(i),Y(i),S(i),C(i+1));
end generate;
S(16) <= C(16);
End

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Example 2: 16:1 Multiplexer

• The 16:1 multiplexer can now be implemented as
follows:
library IEEE;
use IEEE.std_logic_1164.all;
entity Mux16to1 is
port(W: in STD_LOGIC_VECTOR(0 to 15);
S: in STD_LOGIC_VECTOR(3 downto 0);
f: out STD_LOGIC);
end Mux16to1;
architecture behavior of Mux16to1 is
signal X: STD_LOGIC_VECTOR(0 to 3);
component Mux4to1 is
port(W: in STD_LOGIC_VECTOR(0 to 3);
S: in STD_LOGIC_VECTOR(1 downto 0);
f: out STD_LOGIC);
end component;
begin
…

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Example 2: 16:1 Multiplexer

• The 16:1 multiplexer can now be implemented as
follows:
begin
G1:
for i in 0 to 3 generate
Muxes: Mux4to1 port map
(W(4*i to 4*i+3),S(1 downto 0),X(i));
end G1;
MUX5: Mux4to1 port map (X(0 to 3),S(3 downto 2),f);
end behavior;

• Note that the indexes of the inputs are as follows:

– 𝑖 =0→𝑀 0 𝑡𝑜 3 .
– 𝑖 =1→𝑀 4 𝑡𝑜 7 .
– 𝑖 =2→𝑀 8 𝑡𝑜 11 .
– 𝑖 =3→𝑀 12 𝑡𝑜 15 .

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Conditional Generate:
• The syntax of a conditional generate statement in
VHDL is:
<label>:
if <condition> generate
<concurrent statements>;
end generate;
• The condition can be any relational operation of
which the output is a logical (true or false).

• Considering the 2:4 decoder we saw earlier, let us

attempt to write a code using the conditional and
unconditional generate statements to implement a
4:16 decoder.

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Example 1: 4:16 Binary Decoder

• This is a
diagram of
the 2:16 binary
decoder.
• If 𝑬𝒏 = 𝟎, all of
the outputs
are 0.
• If 𝑬𝒏 = 𝟏, 𝒘𝟐
and 𝒘𝟑 are
used to select
one of the
four decoders
on the right,
then 𝒘𝟎 and
𝒘𝟏 select one
of the outputs.

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Example 1: 4:16 Binary Decoder

• Below is the implementation of a 4:16 binary
decoder:
library IEEE;
use IEEE.std_logic_1164.all;
entity Dec4to16 is
port(W: in STD_LOGIC_VECTOR(3 downto 0);
En: in STD_LOGIC;
Y: out STD_LOGIC_VECTOR(0 to 15));
end Dec4to16;
architecture behavior of Dec4to16 is
component Dec2to4 is
port(W: in STD_LOGIC_VECTOR(1 downto 0);
En: in STD_LOGIC;
Y: out STD_LOGIC_VECTOR(0 to 3));
end component;
signal M: STD_LOGIC_VECTOR(0 to 3);
begin
…

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Example 1: 4:16 Binary Decoder

• Below is the implementation of a 4:16 binary
decoder:
begin
G1: for i in 0 to 3 generate
Dec_right: Dec2to4 port map
(W(1 downto 0),M(i),Y(4*i to 4*i+3));
G2: if i=3 generate
Dec_left: Dec2to4 port map
(W(i downto i-1),En,M);
end G2;
end G1;
end behavior;

• Can you explain this code?

• Note that the loop generates four 2:4 decoders
each one with the different enable
• conditional statement generates a fifth 2:4 decoder
when 𝒊 = 𝟑.

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Process Statement:
• Up to this point in VHDL, we have only dealt with
concurrent assignments and statements.
• VHDL also allows for sequential statements, which
must be placed within a process:
process (<sig1>,< sig1 >,…) is
begin
<sequential statement>;
end process;
• The list of signals named between the parenthesis is
called the sensitivity list.
• When one of these signals changes, the process
becomes active and the code within it is executed
in sequential order.
• Assignments made inside the process are not seen
outside it until all the statements are executed.

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If-Then-Else Statement:
• The if-then-else statement has the syntax:
if <condition> then
<statement 1>;
else
<statement 2>;
end if;
• The if-then-else statement may also include the
elseif command:
if <condition 1> then <statement 1>;
elseif <condition 2> then <statement 2>;
else <statement 3>;
end if;
• When multiple conditions exist, the elseif command
may be repeated as required.

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Example 1: 2:1 Multiplexer

• The following is a sequential implementation of the
2:1 multiplexer using the if-then-else statement:
library IEEE;
use IEEE.std_logic_1164.all;
entity Mux2to1 is
port(w0,w1,s: in STD_LOGIC;
f: out STD_LOGIC);
end Mux2to1;
architecture behavior of Mux2to1 is
begin
process (w0,w1,s) is
begin
if s=‘0’ then
f <= w0;
else
f <= w0;
end if;
end process;
end behavior;

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Example 1: 2:1 Multiplexer

• Below is another implementation of the multiplexer.
• How is the circuit affected if the assignment (f <=
w0) is moved below the if-then-else statement?
library IEEE;
use IEEE.std_logic_1164.all;
entity Mux2to1 is
port(w0,w1,s: in STD_LOGIC;
f: out STD_LOGIC);
end Mux2to1;
architecture behavior of Mux2to1 is
begin
process (w0,w1,s) is
begin
f <= w0;
if s=‘1’ then
f <= w0;
end if;
end process;
end behavior;

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Example 2: Priority Encoder

• Here is the VHDL code for a priority encoder:
library IEEE;
use IEEE.std_logic_1164.all;
entity priority is
port(W: in STD_LOGIC_VECTOR(3 downto 0);
Y: out STD_LOGIC_VECTOR(1 downto 0);
z: out STD_LOGIC);
end priority;
architecture behavior of priority is
begin
process (w) is
begin
if W(3)=‘1’ then Y <= “11”;
elseif W(2)=‘1’ then Y <= “10”;
elseif W(1)=‘1’ then Y <= “01”;
else Y <= “00”;
end if;
end process;
z <= ‘0’ when w=“0000” else ‘1’;
end behavior;

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Example 2: Priority Encoder

• The code can be rewritten in the form:
library IEEE;
use IEEE.std_logic_1164.all;
entity priority is
port(W: in STD_LOGIC_VECTOR(3 downto 0);
Y: out STD_LOGIC_VECTOR(1 downto 0);
z: out STD_LOGIC);
end priority;
architecture behavior of priority is
begin
process (w) is
Begin
Y <= “00”;
if W(3)=‘1’ then Y <= “11”; end if;
elseif W(2)=‘1’ then Y <= “10”; end if;
elseif W(1)=‘1’ then Y <= “01”; end if;
end process;
z <= ‘1’;
if w=“0000” then z <= ‘0’; end if;
end behavior;

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Example 3: 1-Bit Comparator

• Below is a VHDL implementation of a 1-bit
comparator using the if-then-else statement.
• This simplified comparator test only for equality.
library IEEE;
use IEEE.std_logic_1164.all;
entity Compare1 is
port(A,B: in STD_LOGIC;
AeqB: out STD_LOGIC);
end Compare1;
architecture behavior of Compare1 is
begin
process (A,B) is
begin
AeqB <= ‘0’;
if A=B then
AeqB <= ‘1’;
end if;
end process;
end behavior;

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Example 3: 1-Bit Comparator

• If the default assignment (AeqB <= ‘0’;) is
removed, VHDL assumes the coder implies memory.
library IEEE;
use IEEE.std_logic_1164.all;
entity Compare1 is
port(A,B: in STD_LOGIC;
AeqB: out STD_LOGIC);
end Compare1;
architecture behavior of Compare1 is
begin
process (A,B) is
begin
if A=B then AeqB <= ‘1’; end if;
end process;
end behavior;

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The Case Statement:

• The case statement can also be used inside a
process.
• It has the form:
case <signal> is
when <value 1> =>
<assignment 1>;
when <value 2> =>
<assignment 2>;
when others =>
<assignment 3>;
end case;
• The clauses may repeat as many times as required
to cover all possible values of the inputs/outputs.

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Example 1: 2:1 Multiplexer

• The following is a sequential implementation of the
2:1 multiplexer using the case statement:
library IEEE;
use IEEE.std_logic_1164.all;
entity Mux2to1 is
port(w0,w1,s: in STD_LOGIC;
f: out STD_LOGIC);
end Mux2to1;
architecture behavior of Mux2to1 is
begin
process (w0,w1,s) is
begin
case s is
when ‘0’ => F <= w0;
when others => F <= w1;
end case;
end process;
end behavior;

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Example 2: 2:4 Binary Decoder

entity Dec2to4 is
port(W: in STD_LOGIC_VECTOR(1 downto 0);
En: in STD_LOGIC;
Y: out STD_LOGIC_VECTOR(0 to 3));
end Dec2to4;
architecture behavior of Dec2to4 is
begin
process (W,En) is
begin
if En=‘1’ then
case W is
when “00” => Y <= “1000”;
when “01” => Y <= “0100”;
when “10” => Y <= “0010”;
when others => Y <= “0001”;
end case;
else
Y <= “0000”;
end if;
end process;
end behavior;

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Example 3: BCD to 7-Segment

• The following is a sequential implementation of the
2:1 multiplexer using the case statement:

library IEEE;
use IEEE.std_logic_1164.all;
entity Seg7 is
port(bcd: in STD_LOGIC_VECTOR(3 downto 0);
leds: out STD_LOGIC_VECTOR(1 to 7));
end Seg7;

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Example 3: BCD to 7-Segment

architecture behavior of Seg7 is
begin
process (bcd) is
begin
case bcd is --abcdefg
when “0000” => leds <= “1111110”;
when “0001” => leds <= “0110000”;
when “0010” => leds <= “1101101”;
when “0011” => leds <= “1111001”;
when “0100” => leds <= “0110011”;
when “0101” => leds <= “1011011”;
when “0110” => leds <= “1011111”;
when “0111” => leds <= “1110000”;
when “1000” => leds <= “1111111”;
when “1001” => leds <= “1110011”;
when others => leds <= “-------”;
end case;
end process;
end behavior;

• Note: the notation (‘-’) denotes “don’t care”.

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Example 4: Arithmetic Logic Unit

• The ALU is a logic circuit that can perform various
arithmetic and logical operations.
• It is an essential part of any microprocessor.
• For instance, the standard chip 74381 is a simple
ALU with 4-bit inputs.
• The functionality of the
74381 chip is
summarized in this table.
• The select lines 𝒔𝟐 𝒔𝟏 𝒔𝟎
determine what
operation is to be
carried out by the ALU.
• A VHDL implementation
of this ALU is given in
the next slides.

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Example 4: Arithmetic Logic Unit

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ALU is
port(S: in STD_LOGIC_VECTOR(2 downto 0);
A,B: in STD_LOGIC_VECTOR(3 downto 0);
F: out STD_LOGIC_VECTOR(3 downto 0));
end ALU;
architecture behavior of ALU is
begin
process (S,A,B) is
begin
case S is
when “000” => F <= “0000”;
when “001” => F <= B-A;
when “010” => F <= A-B;
when “011” => F <= A+B;
when “100” => F <= A xor B;
when “101” => F <= A or B;
when “110” => F <= A and B;

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Example 4: Arithmetic Logic Unit

when others => F <= “1111”;
end case;
end process;
end behavior;

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End of Chapter VI

Digital Design II (EE411) | Dr. Samir Bendoukha