DS90CR287/DS90CR288A +3.

3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-85 MHZ

July 2001

DS90CR287/DS90CR288A
+3.3V Rising Edge Data Strobe LVDS 28-Bit Channel
Link-85 MHZ
General Description Features
The DS90CR287 transmitter converts 28 bits of LVCMOS/ n 20 to 85 MHZ shift clock support
LVTTL data into four LVDS (Low Voltage Differential Signal- n 50% duty cycle on receiver output clock
ing) data streams. A phase-locked transmit clock is transmit- n 2.5 / 0 ns Set & Hold Times on TxINPUTs
ted in parallel with the data streams over a fifth LVDS link. n Low power consumption
Every cycle of the transmit clock 28 bits of input data are n ± 1V common mode range (around +1.2V)
sampled and transmitted. The DS90CR288A receiver con-
n Narrow bus reduces cable size and cost
verts the four LVDS data streams back into 28 bits of
LVCMOS/LVTTL data. At a transmit clock frequency of 85 n Up to 2.38 Gbps throughput
MHZ, 28 bits of TTL data are transmitted at a rate of 595 n Up to 297.5 Megabytes/sec bandwidth
Mbps per LVDS data channel. Using a 85 MHZ clock, the n 345 mV (typ) swing LVDS devices for low EMI
data throughput is 2.38 Gbit/s (297.5 Mbytes/sec). Both n PLL requires no external components
devices are also offered in 64 ball, 0.8mm fine pitch ball grid n Rising edge data strobe
array (FBGA) package which provides a 44 % reduction in n Compatible with TIA/EIA-644 LVDS standard
PCB footprint over the 56L TSSOP package. n Low profile 56-lead TSSOP package
This chipset is an ideal means to solve EMI and cable size n Both devices are also available in 64 ball, 0.8mm fine
problems associated with wide, high-speed TTL interfaces. pitch ball grid array (FBGA) package

Block Diagrams

DS90CR287 DS90CR288A

DS101087-1 DS101087-27

Order Number DS90CR287MTD or DS90CR287SLC Order Number DS90CR288AMTD or DS90CR288ASLC

See NS Package Number MTD56 or SLC64A See NS Package Number MTD56 or SLC64A

TRI-STATE ® is a registered trademark of National Semiconductor Corporation.

© 2001 National Semiconductor Corporation DS101087 www.national.com

DS90CR287/DS90CR288A
Pin Diagram for TSSOP Packages
DS90CR287 DS90CR288A

DS101087-21 DS101087-22

Typical Application

DS101087-23

www.national.com 2
 DS90CR287/DS90CR288A
Absolute Maximum Ratings (Note 1) DS90CR288AMTD 12.4 mW/˚C above +25˚C
If Military/Aerospace specified devices are required, Maximum Package Power
please contact the National Semiconductor Sales Office/ Dissipation @ +25˚C
Distributors for availability and specifications. SLC64A Package:
DS90CR287SLC 2.0 W
Supply Voltage (VCC) −0.3V to +4V
DS90CR288ASLC 2.0 W
CMOS/TTL Input Voltage −0.5V to (VCC + 0.3V)
Package Derating:
CMOS/TTL Output Voltage −0.3V to (VCC + 0.3V)
DS90CR287SLC 10.2 mW/˚C above +25˚C
LVDS Receiver Input Voltage −0.3V to (VCC + 0.3V)
DS90CR288ASLC 10.2 mW/˚C above +25˚C
LVDS Driver Output Voltage −0.3V to (VCC + 0.3V)
ESD Rating
LVDS Output Short Circuit
(HBM, 1.5kΩ, 100pF) > 7kV
Duration Continuous
(EIAJ, 0Ω, 200pF) > 700V
Junction Temperature +150˚C
Latch Up Tolerance @ +25˚C > ± 300mA
Storage Temperature −65˚C to +150˚C
Lead Temperature
Recommended Operating
(Soldering, 4 sec.) +260˚C
Solder Reflow Temperature
Conditions
(20 sec for FBGA) +220˚C Min Nom Max Units
Maximum Package Power Dissipation @ +25˚C Supply Voltage (VCC) 3.0 3.3 3.6 V
MTD56 (TSSOP) Package: Operating Free Air
DS90CR287MTD 1.63 W Temperature (TA) −10 +25 +70 ˚C
DS90CR288AMTD 1.61 W Receiver Input Range 0 2.4 V
Package Derating: Supply Noise Voltage (VCC) 100 mVPP
DS90CR287MTD 12.5 mW/˚C above +25˚C

Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
LVCMOS/LVTTL DC SPECIFICATIONS
VIH High Level Input Voltage 2.0 VCC V
VIL Low Level Input Voltage GND 0.8 V
VOH High Level Output Voltage IOH = −0.4 mA 2.7 3.3 V
VOL Low Level Output Voltage IOL = 2 mA 0.06 0.3 V
VCL Input Clamp Voltage ICL = −18 mA −0.79 −1.5 V
IIN Input Current VIN = 0.4V, 2.5V or VCC +1.8 +15 µA
VIN = GND −10 0 µA
IOS Output Short Circuit Current VOUT = 0V −60 −120 mA
LVDS DRIVER DC SPECIFICATIONS
VOD Differential Output Voltage RL = 100Ω 250 290 450 mV
∆VOD Change in VOD between 35 mV
Complimentary Output States
VOS Offset Voltage (Note 4) 1.125 1.25 1.375 V
∆VOS Change in VOS between 35 mV
Complimentary Output States
IOS Output Short Circuit Current VOUT = 0V, RL = 100Ω −3.5 −5 mA
IOZ Output TRI-STATE ® Current PWR DWN = 0V, ±1 ± 10 µA
VOUT = 0V or VCC
LVDS RECEIVER DC SPECIFICATIONS
VTH Differential Input High Threshold VCM = +1.2V +100 mV
VTL Differential Input Low Threshold −100 mV
IIN Input Current VIN = +2.4V, VCC = 3.6V ± 10 µA
VIN = 0V, VCC = 3.6V ± 10 µA

3 www.national.com
DS90CR287/DS90CR288A
Electrical Characteristics (Continued)

Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
TRANSMITTER SUPPLY CURRENT
ICCTW Transmitter Supply Current RL = 100Ω, f = 33 MHz 31 45 mA
Worst Case (with Loads) CL = 5 pF, f = 40 MHz 32 50 mA
Worst Case
f = 66 MHz 37 55 mA
Pattern
(Figures 1, 2) f = 85 MHz 42 60 mA
ICCTZ Transmitter Supply Current PWR DWN = Low
Power Down Driver Outputs in TRI-STATE 10 55 µA
under Powerdown Mode
RECEIVER SUPPLY CURRENT
ICCRW Receiver Supply Current Worst CL = 8 pF, f = 33 MHz 49 70 mA
Case Worst Case f = 40 MHz 53 75 mA
Pattern f = 66 MHz 81 114 mA
(Figures 1, 3)
f = 85 MHz 96 135 mA
ICCRZ Receiver Supply Current Power PWR DWN = Low 140 400 µA
Down Receiver Outputs Stay Low during
Powerdown Mode
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for VCC = 3.3V and TA = +25˚C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except VOD and ∆VOD).
Note 4: VOS previously referred as VCM.

Transmitter Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Min Typ Max Units
LLHT LVDS Low-to-High Transition Time (Figure 2) 0.75 1.5 ns
LHLT LVDS High-to-Low Transition Time (Figure 2) 0.75 1.5 ns
TCIT TxCLK IN Transition Time (Figure 4) 1.0 6.0 ns
TPPos0 Transmitter Output Pulse Position for Bit0 (Figure 14) f = 85 MHz −0.20 0 0.20 ns
TPPos1 Transmitter Output Pulse Position for Bit1 1.48 1.68 1.88 ns
TPPos2 Transmitter Output Pulse Position for Bit2 3.16 3.36 3.56 ns
TPPos3 Transmitter Output Pulse Position for Bit3 4.84 5.04 5.24 ns
TPPos4 Transmitter Output Pulse Position for Bit4 6.52 6.72 6.92 ns
TPPos5 Transmitter Output Pulse Position for Bit5 8.20 8.40 8.60 ns
TPPos6 Transmitter Output Pulse Position for Bit6 9.88 10.08 10.28 ns
TCIP TxCLK IN Period (Figure 5 ) 11.76 T 50 ns
TCIH TxCLK IN High Time (Figure 5) 0.35T 0.5T 0.65T ns
TCIL TxCLK IN Low Time (Figure 5) 0.35T 0.5T 0.65T ns
TSTC TxIN Setup to TxCLK IN (Figure 5) f = 85 MHz 2.5 ns
THTC TxIN Hold to TxCLK IN (Figure 5) 0 ns
TCCD TxCLK IN to TxCLK OUT Delay (Figure 7) TA = 25˚C, 3.8 6.3 ns
VCC = 3.3V
TPLLS Transmitter Phase Lock Loop Set (Figure 9) 10 ms
TPDD Transmitter Powerdown Delay (Figure 12) 100 ns
TJIT TxCLK IN Cycle-to-Cycle Jitter (Input clock requirement) 2 ns

www.national.com 4
 DS90CR287/DS90CR288A
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Min Typ Max Units
CLHT CMOS/TTL Low-to-High Transition Time (Figure 3) 2 3.5 ns
CHLT CMOS/TTL High-to-Low Transition Time (Figure 3) 1.8 3.5 ns
RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 15) f = 85 MHz 0.49 0.84 1.19 ns
RSPos1 Receiver Input Strobe Position for Bit 1 2.17 2.52 2.87 ns
RSPos2 Receiver Input Strobe Position for Bit 2 3.85 4.20 4.55 ns
RSPos3 Receiver Input Strobe Position for Bit 3 5.53 5.88 6.23 ns
RSPos4 Receiver Input Strobe Position for Bit 4 7.21 7.56 7.91 ns
RSPos5 Receiver Input Strobe Position for Bit 5 8.89 9.24 9.59 ns
RSPos6 Receiver Input Strobe Position for Bit 6 10.57 10.92 11.27 ns
RSKM RxIN Skew Margin (Note 5) (Figure 16) f = 85 MHz 290 ps
RCOP RxCLK OUT Period (Figure 6) 11.76 T 50 ns
RCOH RxCLK OUT High Time (Figure 6) f = 85 MHz 4 5 6.5 ns
RCOL RxCLK OUT Low Time (Figure 6) 3.5 5 6 ns
RSRC RxOUT Setup to RxCLK OUT (Figure 6) 3.5 ns
RHRC RxOUT Hold to RxCLK OUT (Figure 6) 3.5 ns
RCCD RxCLK IN to RxCLK OUT Delay @ 25˚C, VCC = 3.3V (Note 6)(Figure 8) 5.5 7 9.5 ns
RPLLS Receiver Phase Lock Loop Set (Figure 10) 10 ms
RPDD Receiver Powerdown Delay (Figure 13) 1 µs
Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min
and max) and the receiver input setup and hold time (internal data sampling window-RSPOS). This margin allows LVDS interconnect skew, inter-symbol interference
(both dependent on type/length of cable), and source clock (less than 150 ps).
Note 6: Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver (RCCD). The total latency
for the 217/287 transmitter and 218/288A receiver is: (T + TCCD) + (2*T + RCCD), where T = Clock period.

AC Timing Diagrams

DS101087-2

FIGURE 1. “Worst Case” Test Pattern

DS101087-3

DS101087-4

FIGURE 2. DS90CR287 (Transmitter) LVDS Output Load and Transition Times

5 www.national.com
DS90CR287/DS90CR288A
AC Timing Diagrams (Continued)

DS101087-5
DS101087-6

FIGURE 3. DS90CR288A (Receiver) CMOS/TTL Output Load and Transition Times

DS101087-7

FIGURE 4. DS90CR287 (Transmitter) Input Clock Transition Time

DS101087-9

FIGURE 5. DS90CR287 (Transmitter) Setup/Hold and High/Low Times

DS101087-10

FIGURE 6. DS90CR288A (Receiver) Setup/Hold and High/Low Times

DS101087-11

FIGURE 7. DS90CR287 (Transmitter) Clock In to Clock Out Delay

www.national.com 6
 DS90CR287/DS90CR288A
AC Timing Diagrams (Continued)

DS101087-12

FIGURE 8. DS90CR288A (Receiver) Clock In to Clock Out Delay

DS101087-13

FIGURE 9. DS90CR287 (Transmitter) Phase Lock Loop Set Time

DS101087-14

FIGURE 10. DS90CR288A (Receiver) Phase Lock Loop Set Time

7 www.national.com
DS90CR287/DS90CR288A
AC Timing Diagrams (Continued)

DS101087-16

FIGURE 11. 28 ParalIeI TTL Data Inputs Mapped to LVDS Outputs

DS101087-17

FIGURE 12. Transmitter Powerdown DeIay

DS101087-18

FIGURE 13. Receiver Powerdown Delay

www.national.com 8
 DS90CR287/DS90CR288A
AC Timing Diagrams (Continued)

DS101087-19

FIGURE 14. Transmitter LVDS Output Pulse Position Measurement

9 www.national.com
DS90CR287/DS90CR288A
AC Timing Diagrams (Continued)

DS101087-28

FIGURE 15. Receiver LVDS Input Strobe Position

www.national.com 10
 DS90CR287/DS90CR288A
AC Timing Diagrams (Continued)

DS101087-20

C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos — Transmitter output pulse position (min and max)
RSKM ≥ Cable Skew (type, length) + Source Clock Jitter (cycle to cycle)(Note 7) + ISI (Inter-symbol interference)(Note 8)
Cable Skew — typically 10 ps–40 ps per foot, media dependent
Note 7: Cycle-to-cycle jitter is less than 150ps at 85MHZ.
Note 8: ISI is dependent on interconnect length; may be zero
FIGURE 16. Receiver LVDS Input Skew Margin

DS90CR287 MTD56 (TSSOP) Package Pin Description —

Channel Link Transmitter
Pin Name I/O No. Description
TxIN I 28 TTL level input.
TxOUT+ O 4 Positive LVDS differential data output.
TxOUT− O 4 Negative LVDS differential data output.
TxCLK IN I 1 TTL IeveI clock input. The rising edge acts as data strobe. Pin name TxCLK IN.
TxCLK OUT+ O 1 Positive LVDS differential clock output.
TxCLK OUT− O 1 Negative LVDS differential clock output.
PWR DOWN I 1 TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at
power down.
VCC I 4 Power supply pins for TTL inputs.
GND I 5 Ground pins for TTL inputs.
PLL VCC I 1 Power supply pin for PLL.
PLL GND I 2 Ground pins for PLL.
LVDS VCC I 1 Power supply pin for LVDS outputs.
LVDS GND I 3 Ground pins for LVDS outputs.

DS90CR287 SLC64A (FBGA) Package Pin Summary —

Channel Link Transmitter
Pin Name I/O No. Description
TxIN I 28 TTL level input.
TxOUT+ O 4 Positive LVDS differential data output.
TxOUT− O 4 Negative LVDS differential data output.
TxCLKIN I 1 TTL IeveI clock input. The rising edge acts as data strobe. Pin name TxCLK IN.
TxCLK OUT+ O 1 Positive LVDS differential clock output.
TxCLK OUT− O 1 Negative LVDS differential clock output.
PWR DOWN I 1 TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at
power down.
VCC I 4 Power supply pins for TTL inputs.
GND I 5 Ground pins for TTL inputs.
PLL VCC I 1 Power supply pin for PLL.

11 www.national.com
DS90CR287/DS90CR288A
DS90CR287 SLC64A (FBGA) Package Pin Summary —
Channel Link Transmitter (Continued)
Pin Name I/O No. Description
PLL GND I 2 Ground pins for PLL.
LVDS VCC I 2 Power supply pin for LVDS outputs.
LVDS GND I 4 Ground pins for LVDS outputs.
NC 6 Pins not connected.

DS90CR287 SLC64A (FBGA) Package Pin Description —

Channel Link Transmitter
By Pin By Pin Type
Pin Pin Name Type Pin Pin Name Type
A1 TxIN27 I D3 GND G
A2 TxOUT0- O E4 GND G
A3 TxOUT0+ O E8 GND G
A4 LVDS VCC P G1 GND G
A5 LVDS VCC P G6 GND G
A6 TxCLKOUT- O B3 LVDS GND G
A7 TxCLKOUT+ O B4 LVDS GND G
A8 TxOUT3+ O B7 LVDS GND G
B1 TxIN1 I D5 LVDS GND G
B2 TxIN0 I C6 PLL GND G
B3 LVDS GND G D6 PLL GND G
B4 LVDS GND G D7 PWR DOWN I
B5 TxOUT2- O C8 TxCLKIN I
B6 TxOUT3- O B2 TxIN0 I
B7 LVDS GND G B1 TxIN1 I
B8 NC D2 TxIN2 I
C1 TxIN3 I C1 TxIN3 I
C2 NC D1 TxIN4 I
C3 NC F1 TxIN5 I
C4 TxOUT1- O E2 TxIN6 I
C5 TxOUT2+ O E3 TxIN7 I
C6 PLL GND G G2 TxIN8 I
C7 PLL VCC P H1 TxIN9 I
C8 TxCLKIN I G3 TxIN10 I
D1 TxIN4 I H3 TxIN11 I
D2 TxIN2 I F4 TxIN12 I
D3 GND G G4 TxIN13 I
D4 TxOUT1+ O H4 TxIN14 I
D5 LVDS GND G H5 TxIN15 I
D6 PLL GND G E5 TxIN16 I
D7 PWR DOWN I F5 TxIN17 I
D8 TxIN26 I H6 TxIN18 I
E1 VCC P H7 TxIN19 I
E2 TxIN6 I H8 TxIN20 I
E3 TxIN7 I G7 TxIN21 I
E4 GND G F7 TxIN22 I
E5 TxIN16 I G8 TxIN23 I
E6 VCC P E7 TxIN24 I

www.national.com 12
 DS90CR287/DS90CR288A
DS90CR287 SLC64A (FBGA) Package Pin Description —
Channel Link Transmitter (Continued)
By Pin By Pin Type
E7 TxIN24 I F8 TxIN25 I
E8 GND G D8 TxIN26 I
F1 TxIN5 I A1 TxIN27 I
F2 NC A6 TxCLKOUT- O
F3 NC A7 TxCLKOUT+ O
F4 TxIN12 I A2 TxOUT0- O
F5 TxIN17 I A3 TxOUT0+ O
F6 NC C4 TxOUT1- O
F7 TxIN22 I D4 TxOUT1+ O
F8 TxIN25 I B5 TxOUT2- O
G1 GND G C5 TxOUT2+ O
G2 TxIN8 I B6 TxOUT3- O
G3 TxIN10 I A8 TxOUT3+ O
G4 TxIN13 I A4 LVDS VCC P
G5 VCC P A5 LVDS VCC P
G6 GND G C7 PLL VCC P
G7 TxIN21 I E1 VCC P
G8 TxIN23 I E6 VCC P
H1 TxIN9 I G5 VCC P
H2 VCC P H2 VCC P
H3 TxIN11 I B8 NC
H4 TxIN14 I C2 NC
H5 TxIN15 I C3 NC
H6 TxIN18 I F2 NC
H7 TxIN19 I F3 NC
H8 TxIN20 I F6 NC
G : Ground
I : Input
O : Output
P : Power
NC : No connect

DS90CR288A MTD56 (TSSOP) Package Pin Description —

Channel Link Receiver
Pin Name I/O No. Description
RxIN+ I 4 Positive LVDS differential data inputs.
RxIN− I 4 Negative LVDS differential data inputs.
RxOUT O 28 TTL level data outputs.
RxCLK IN+ I 1 Positive LVDS differential clock input.
RxCLK IN− I 1 Negative LVDS differential clock input.
RxCLK OUT O 1 TTL level clock output. The rising edge acts as data strobe. Pin name RxCLK OUT.
PWR DOWN I 1 TTL level input.When asserted (low input) the receiver outputs are low.
VCC I 4 Power supply pins for TTL outputs.
GND I 5 Ground pins for TTL outputs.
PLL VCC I 1 Power supply for PLL.
PLL GND I 2 Ground pin for PLL.
LVDS VCC I 1 Power supply pin for LVDS inputs.
LVDS GND I 3 Ground pins for LVDS inputs.

13 www.national.com
DS90CR287/DS90CR288A
DS90CR288A SLC64A (FBGA) Package Pin Summary —
Channel Link Receiver
Pin Name I/O No. Description
RxIN+ I 4 Positive LVDS differentiaI data inputs.
RxIN− I 4 Negative LVDS differential data inputs.
RxOUT O 28 TTL level data outputs.
RxCLK IN+ I 1 Positive LVDS differential clock input.
RxCLK IN− I 1 Negative LVDS differential clock input.
RxCLK OUT O 1 TTL Ievel clock output. The rising edge acts as data strobe.
PWR DOWN I 1 TTL level input. When asserted (low input) the receiver outputs are low.
VCC I 4 Power supply pins for TTL outputs.
GND I 5 Ground pins for TTL outputs.
PLL VCC I 1 Power supply for PLL.
PLL GND I 2 Ground pin for PLL.
LVDS VCC I 2 Power supply pin for LVDS inputs.
LVDS GND I 4 Ground pins for LVDS inputs.
NC 6 Pins not connected.

DS90CR288A SLC64A (FBGA) Package Pin Description —

Channel Link Receiver
By Pin By Pin Type
Pin Pin Name Type Pin Pin Name Type
A1 RxOUT17 O A4 GND G
A2 VCC P B1 GND G
A3 RxOUT15 O B6 GND G
A4 GND G D8 GND G
A5 RxOUT12 O E3 GND G
A6 RxOUT8 O E5 LVDS GND G
A7 RxOUT7 O G3 LVDS GND G
A8 RxOUT6 O G7 LVDS GND G
B1 GND G H5 LVDS GND G
B2 NC F6 PLL GND G
B3 RxOUT16 O G8 PLL GND G
B4 RxOUT11 O E6 PWR DOWN I
B5 VCC P H6 RxCLKIN- I
B6 GND G H7 RxCLKIN+ I
B7 RxOUT5 O H2 RxIN0- I
B8 RxOUT3 O H3 RxIN0+ I
C1 RxOUT21 O F4 RxIN1- I
C2 NC G4 RxIN1+ I
C3 RxOUT18 O G5 RxIN2- I
C4 RxOUT14 O F5 RxIN2+ I
C5 RxOUT9 O G6 RxIN3- I
C6 RxOUT4 O H8 RxIN3+ I
C7 NC E7 RxCLKOUT O
C8 RxOUT1 O E8 RxOUT0 O
D1 VCC P C8 RxOUT1 O
D2 RxOUT20 O D7 RxOUT2 O
D3 RxOUT19 O B8 RxOUT3 O
D4 RxOUT13 O C6 RxOUT4 O

www.national.com 14
 DS90CR287/DS90CR288A
DS90CR288A SLC64A (FBGA) Package Pin Description —
Channel Link Receiver (Continued)
By Pin By Pin Type
D5 RxOUT10 O B7 RxOUT5 O
D6 VCC P A8 RxOUT6 O
D7 RxOUT2 O A7 RxOUT7 O
D8 GND G A6 RxOUT8 O
E1 RxOUT22 O C5 RxOUT9 O
E2 RxOUT24 O D5 RxOUT10 O
E3 GND G B4 RxOUT11 O
E4 LVDS VCC P A5 RxOUT12 O
E5 LVDS GND G D4 RxOUT13 O
E6 PWR DOWN I C4 RxOUT14 O
E7 RxCLKOUT O A3 RxOUT15 O
E8 RxOUT0 O B3 RxOUT16 O
F1 RxOUT23 O A1 RxOUT17 O
F2 RxOUT26 O C3 RxOUT18 O
F3 NC D3 RxOUT19 O
F4 RxIN1- I D2 RxOUT20 O
F5 RxIN2+ I C1 RxOUT21 O
F6 PLL GND G E1 RxOUT22 O
F7 PLL VCC P F1 RxOUT23 O
F8 NC E2 RxOUT24 O
G1 RxOUT25 O G1 RxOUT25 O
G2 NC F2 RxOUT26 O
G3 LVDS GND G H1 RxOUT27 O
G4 RxIN1+ I E4 LVDS VCC P
G5 RxIN2- I H4 LVDS VCC P
G6 RxIN3- I F7 PLL VCC P
G7 LVDS GND G A2 VCC P
G8 PLL GND G B5 VCC P
H1 RxOUT27 O D1 VCC P
H2 RxIN0- I D6 VCC P
H3 RxIN0+ I B2 NC
H4 LVDS VCC P C2 NC
H5 LVDS GND G C7 NC
H6 RxCLKIN- I F3 NC
H7 RxCLKIN+ I F8 NC
H8 RxIN3+ I G2 NC
G : Ground
I : Input
O : Output
P : Power
NC : No Connect

15 www.national.com
DS90CR287/DS90CR288A
Applications Information The high-speed transport of LVDS signals has been demon-
strated on several types of cables with excellent results.
The TSSOP version of the DS90CR287 and However, the best overall performance has been seen when
DS90CR288A are backward compatible with the existing using Twin-Coax cable. Twin-Coax has very low cable skew
5V Channel Link transmitter/receiver pair (DS90CR283, and EMI due to its construction and double shielding. All of
DS90CR284). To upgrade from a 5V to a 3.3V system the the design considerations discussed here and listed in the
following must be addressed: supplemental application notes provide the subsystem com-
1. Change 5V power supply to 3.3V. Provide this supply munications designer with many useful guidelines. It is rec-
to the VCC, LVDS VCC and PLL VCC. ommended that the designer assess the tradeoffs of each
2. Transmitter input and control inputs except 3.3V TTL/ application thoroughly to arrive at a reliable and economical
CMOS levels. They are not 5V tolerant. cable solution.
3. The receiver powerdown feature when enabled will RECEIVER FAILSAFE FEATURE: These receivers have
lock receiver output to a logic low. input failsafe bias circuitry to guarantee a stable receiver
output for floating or terminated receiver inputs. Under these
The Channel Link devices are intended to be used in a
conditions receiver inputs will be in a HIGH state. If a clock
wide variety of data transmission applications. Depending
signal is present, data outputs will all be HIGH; if the clock
upon the application the interconnecting media may vary.
input is also floating/terminated, data outputs will remain in
For example, for lower data rate (clock rate) and shorter
the last valid state. A floating/terminated clock input will
cable lengths ( < 2m), the media electrical performance is
result in a HIGH clock output.
less critical. For higher speed/long distance applications
the media’s performance becomes more critical. Certain BOARD LAYOUT: To obtain the maximum benefit from the
cable constructions provide tighter skew (matched elec- noise and EMI reductions of LVDS, attention should be paid
trical length between the conductors and pairs). Addi- to the layout of differential lines. Lines of a differential pair
tional applications information can be found in the follow- should always be adjacent to eliminate noise interference
ing National Interface Application Notes: from other signals and take full advantage of the noise
canceling of the differential signals. The board designer
AN = #### Topic should also try to maintain equal length on signal traces for
AN-1041 Introduction to Channel Link a given differential pair. As with any high speed design, the
impedance discontinuities should be limited (reduce the
AN-1108 Channel Link PCB and Interconnect
numbers of vias and no 90 degree angles on traces). Any
Design-In Guidelines
discontinuities which do occur on one signal line should be
AN-806 Transmission Line Theory mirrored in the other line of the differential pair. Care should
AN-905 Transmission Line Calculations and be taken to ensure that the differential trace impedance
Differential Impedance match the differential impedance of the selected physical
media (this impedance should also match the value of the
AN-916 Cable Information
termination resistor that is connected across the differential
CABLES: A cable interface between the transmitter and pair at the receiver’s input). Finally, the location of the
receiver needs to support the differential LVDS pairs. The CHANNEL LINK TxOUT/RxIN pins should be as close as
21-bit CHANNEL LINK chipset (DS90CR217/218A) requires possible to the board edge so as to eliminate excessive pcb
four pairs of signal wires and the 28-bit CHANNEL LINK runs. All of these considerations will limit reflections and
chipset (DS90CR287/288A) requires five pairs of signal crosstalk which adversely effect high frequency performance
wires. The ideal cable/connector interface would have a and EMI.
constant 100Ω differential impedance throughout the path. It
INPUTS: The TxIN and control pin inputs are compatible
is also recommended that cable skew remain below 140ps (
with LVTTL and LVCMOS levels. This pins are not 5V toler-
85 MHZ clock rate) to maintain a sufficient data sampling
ant.
window at the receiver.
UNUSED INPUTS: All unused inputs at the TxIN inputs of
In addition to the four or five cable pairs that carry data and
the transmitter may be tied to ground or left no connect. All
clock, it is recommended to provide at least one additional
unused outputs at the RxOUT outputs of the receiver must
conductor (or pair) which connects ground between the
then be left floating.
transmitter and receiver. This low impedance ground pro-
vides a common mode return path for the two devices. Some TERMINATION: Use of current mode drivers requires a
of the more commonly used cable types for point-to-point terminating resistor across the receiver inputs. The CHAN-
applications include flat ribbon, flex, twisted pair and Twin- NEL LINK chipset will normally require a single 100Ω resistor
Coax. All are available in a variety of configurations and between the true and complement lines on each differential
options. Flat ribbon cable, flex and twisted pair generally pair of the receiver input. The actual value of the termination
perform well in short point-to-point applications while Twin- resistor should be selected to match the differential mode
Coax is good for short and long applications. When using characteristic impedance (90Ω to 120Ω typical) of the cable.
ribbon cable, it is recommended to place a ground line Figure 17 shows an example. No additional pull-up or pull-
between each differential pair to act as a barrier to noise down resistors are necessary as with some other differential
coupling between adjacent pairs. For Twin-Coax cable ap- technologies such as PECL. Surface mount resistors are
plications, it is recommended to utilize a shield on each recommended to avoid the additional inductance that ac-
cable pair. All extended point-to-point applications should companies leaded resistors. These resistors should be
also employ an overall shield surrounding all cable pairs placed as close as possible to the receiver input pins to
regardless of the cable type. This overall shield results in reduce stubs and effectively terminate the differential lines.
improved transmission parameters such as faster attainable DECOUPLING CAPACITORS: Bypassing capacitors are
speeds, longer distances between transmitter and receiver needed to reduce the impact of switching noise which could
and reduced problems associated with EMS or EMI. limit performance. For a conservative approach three
parallel-connected decoupling capacitors (Multi-Layered Ce-

www.national.com 16
 DS90CR287/DS90CR288A
Applications Information (Continued) traces for power and ground and ensure each capacitor has
its own via to the ground plane. If board space is limiting the
ramic type in surface mount form factor) between each VCC number of bypass capacitors, the PLL VCC should receive
and the ground plane(s) are recommended. The three ca- the most filtering/bypassing. Next would be the LVDS VCC
pacitor values are 0.1 µF, 0.01µF and 0.001 µF. An example pins and finally the logic VCC pins.
is shown in Figure 18. The designer should employ wide

DS101087-24

FIGURE 17. LVDS Serialized Link Termination

INPUT CLOCK: The input clock should be present at all

times when the part in enabled. If the clock is stopped, the
PWR DOWN pin should be asserted to disable the PLL.
Once the clock is active again, the part can then be enabled.
Do not enable the part without a clock present.
COMMON MODE vs. DIFFERENTIAL MODE NOISE MAR-
GIN: The typical signal swing for LVDS is 300 mV centered
at +1.2V. The CHANNEL LINK receiver supports a 100 mV
threshold therefore providing approximately 200 mV of dif-
ferential noise margin. Common mode protection is of more
importance to the system’s operation due to the differential
data transmission. LVDS supports an input voltage range of
DS101087-25
Ground to +2.4V. This allows for a ± 1.0V shifting of the
FIGURE 18. CHANNEL LINK center point due to ground potential differences and common
Decoupling Configuration mode noise.
POWER SEQUENCING AND POWERDOWN MODE: Out-
CLOCK JITTER: The CHANNEL LINK devices employ a
puts of the CNANNEL LINK transmitter remain in TRI-
PLL to generate and recover the clock transmitted across the
STATE ® until the power supply reaches 2V. Clock and data
LVDS interface. The width of each bit in the serialized LVDS
outputs will begin to toggle 10 ms after VCC has reached 3V
data stream is one-seventh the clock period. For example, a
and the Powerdown pin is above 1.5V. Either device may be
85 MHZ clock has a period of 11.76 ns which results in a
placed into a powerdown mode at any time by asserting the
data bit width of 1.68 ns. Differential skew (∆t within one
Powerdown pin (active low). Total power dissipation for each
differential pair), interconnect skew (∆t of one differential pair
device will decrease to 5 µW (typical).
to another) and clock jitter will all reduce the available win-
dow for sampling the LVDS serial data streams. Care must The CHANNEL LINK chipset is designed to protect itself
be taken to ensure that the clock input to the transmitter be from accidental loss of power to either the transmitter or
a clean low noise signal. Individual bypassing of each VCC to receiver. If power to the transmit board is lost, the receiver
ground will minimize the noise passed on to the PLL, thus clocks (input and output) stop. The data outputs (RxOUT)
creating a low jitter LVDS clock. These measures provide retain the states they were in when the clocks stopped.
more margin for channel-to-channel skew and interconnect When the receiver board loses power, the receiver inputs are
skew as a part of the overall jitter/skew budget. shorted to V CC through an internal diode. Current is limited
(5 mA per input) by the fixed current mode drivers, thus
avoiding the potential for latchup when powering the device.

17 www.national.com
DS90CR287/DS90CR288A
Applications Information (Continued)

DS101087-26

FIGURE 19. Single-Ended and Differential Waveforms

www.national.com 18
 DS90CR287/DS90CR288A
Physical Dimensions inches (millimeters) unless otherwise noted

56-Lead Molded Thin Shrink Small outline Package, JEDEC

Order Number DS90CR287MTD or DS90CR288AMTD
Dimensions shown in millimeters only
NS Package Number MTD56

64 ball, 0.8mm fine pitch ball grid array (FBGA) package

Dimensions shown in millimeters only
Order Number DS90CR287SLC or DS90CR288ASLC
NS Package Number SLC64A

19 www.national.com
DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-85 MHZ
Notes

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform
into the body, or (b) support or sustain life, and can be reasonably expected to cause the failure of
whose failure to perform when properly used in the life support device or system, or to affect its
accordance with instructions for use provided in the safety or effectiveness.
labeling, can be reasonably expected to result in a
significant injury to the user.
National Semiconductor National Semiconductor National Semiconductor National Semiconductor
Corporation Europe Asia Pacific Customer Japan Ltd.
Americas Fax: +49 (0) 180-530 85 86 Response Group Tel: 81-3-5639-7560
Email: [email protected] Email: [email protected] Tel: 65-2544466 Fax: 81-3-5639-7507
Deutsch Tel: +49 (0) 69 9508 6208 Fax: 65-2504466
English Tel: +44 (0) 870 24 0 2171 Email: [email protected]
www.national.com Français Tel: +33 (0) 1 41 91 8790

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.