16/01/24

Computer Architecture and Opera2ng System

Prof. Indranil Sengupta

Department of Computer Science and Engineering
IIT Kharagpur

Memory Addressing and Architecture

Types

1
 16/01/24

Overview of Memory Organiza2on

• Memory is one of the most important sub-systems of a computer that

determines the overall performance.
• Conceptual view of memory:
• Array of storage locaCons, with each storage locaCon having a unique address.
• Each storage locaCon can hold a fixed amount of informaCon (mulCple of bits, which
is the basic unit of data storage).
• A memory system with M locaCons and N bits per locaCon, is referred to
as an M x N memory.
• Both M and N are typically some powers of 2.
• Example: 1024 x 8, 65536 x 32, etc.

16/01/24 Computer Architecture and Opera2ng System (CS31702) 3

Some Terminologies

• Bit: A single binary digit (0 or 1).

• Nibble: CollecCon of 4 bits.
• Byte: CollecCon of 8 bits.
• Word: Does not have a unique definiCon.
(Varies from one computer to another; typically 32 or 64 bits)

16/01/24 Computer Architecture and Opera2ng System (CS31702) 4

2
 16/01/24

How is Memory Organized?

• Memory is oRen byte organized.

• Every byte of the memory has a unique address.

• MulCple bytes of data can be accessed by an instrucCon.

• Example: Half-word (2 bytes), Word (4 bytes), Long Word (8 bytes).

• For higher data transfer rate, memory is oRen organized such that
mulCple bytes can be read or wriUen simultaneously.
• Necessary to bridge the processor-memory speed gap.
• Shall be discussed later.

16/01/24 Computer Architecture and Opera2ng System (CS31702) 5

Processor-Memory
Performance Gap
• With technological
advancements, both
processor and memory are
becoming faster.
• However, the speed gap is
steadily increasing.
• Special techniques are
needed to bridge this gap.
• Cache memory
• Memory interleaving

16/01/24 Computer Architecture and Opera2ng System (CS31702) 6

3
 16/01/24

How do we Specify Memory Sizes?

Unit Bytes In Decimal
8 bits (B) 1 or 20 100
Kilobyte (KB) 1024 or 210 103
Megabyte (MB) 1,048,576 or 220 106
Gigabyte (GB) 1,073,741,824 or 230 109
Terabyte (TB) 1,099,511,627,776 or 240 1012
Petabyte (PB) 250 1015
Exabyte (EB) 260 1018
ZeUabyte (ZB) 270 1021

16/01/24 Computer Architecture and Opera2ng System (CS31702) 7

• If there are n bits in the address,

the maximum number of storage
locaCons can be 2n.
• For n=8, 256 locaCons. Address
• For n=16, 64K locaCons. (n bits)
• For n=20, 1M locaCons. Data MEMORY
• For n=32, 4G locaCons. (m bits)

• Modern-day memory chips can

store several Gigabits of data.
• Dynamic RAM (DRAM). RD WR EN

16/01/24 Computer Architecture and Opera2ng System (CS31702) 8

4
 16/01/24

Address Contents
0000 0000 0000 0000 0000 0001
0000 0001 0000 0100 0101 0000
0000 0010 1010 1000 0000 0000

: :
1111 1111 1011 0000 0000 1010

An example: 28 x 16 memory

16/01/24 Computer Architecture and Opera2ng System (CS31702) 9

Some Examples
1. A computer has 64 MB (megabytes) of byte-addressable memory. How
many bits are needed in the memory address?
• Address Space = 64 MB = 26 x 220 B = 226 B
• If the memory is byte addressable, we need 26 bits of address.
2. A computer has 1 GB of memory. Each word in this computer is 32 bits.
How many bits are needed to address any single word in memory?
• Address Space = 1 GB = 230 B
• 1 word = 32 bits = 4 B
• We have 230 / 4 = 228 words
• Thus, we require 28 bits to address each word.
• If the memory is “byte addressable”, we would need 30 bits of address.
16/01/24 Computer Architecture and Opera2ng System (CS31702) 10

5
 16/01/24

Byte Ordering Conven2ons

• Many data items require mulCple bytes for Data Type Size (in Bytes)
storage.
Character 1
• Different computers use different data ordering
Integer 4
convenCons.
Long integer 8
• Low-order byte first
FloaCng-point 4
• High-order byte first
• Thus a 16-bit number 11001100 00101010 can be Double-precision 8
stored as either: Typical data sizes

11001100 00101010 or 00101010 11001100

16/01/24 Computer Architecture and Opera2ng System (CS31702) 11

• The two convenCons have been named as:

a) LiZle Endian
• The least significant byte is stored at lower address followed by the most significant byte.
Examples: Intel processors, DEC alpha, etc.
• Same concept followed for arbitrary mulC-byte data.
b) Big Endian
• The most significant byte is stored at lower address followed by the least significant byte.
Examples: IBM’s 370 mainframes, Motorola microprocessors, TCP/IP, etc.
• Same concept followed for arbitrary mulC-byte data.

16/01/24 Computer Architecture and Opera2ng System (CS31702) 12

6
 16/01/24

An Example
• Represent the following 32-bit number in both LiUle-Endian and Big-Endian in memory
from address 2000 onwards:
01010101 00110011 00001111 11000011
LiZle Endian Big Endian
Address Data Address Data
2000 11000011 2000 01010101
2001 00001111 2001 00110011
2002 00110011 2002 00001111
2003 01010101 2003 11000011

16/01/24 Computer Architecture and Opera2ng System (CS31702) 13

Memory Access by Instruc2ons

• The program instrucCons and data are stored in memory.
• In von-Neumann architecture, they are stored in the same memory.
• In Harvard architecture, they are stored in different memories.
• For execuCng the program, two basic operaCons are required.
a) Load: The contents of a specified memory locaCon is read into a processor
register. LOAD R1, 2000
b) Store: The contents of a processor register is wriUen into a specified memory
locaCon. STORE 2020, R3

16/01/24 Computer Architecture and Opera2ng System (CS31702) 14

7
 16/01/24

An Example
• Compute S = (A + B) – (C – D)
A typical program in assembly
LOAD R1,A language.
LOAD R2,B Assembly language instrucCons
ADD R3,R1,R2 // R3 = A + B are machine dependent.
LOAD R1,C
LOAD R2,D
SUB R4,R1,R2 // R4 = C – D
SUB R3,R3,R4 // R3 = R3 – R4
STORE S,R3

16/01/24 Computer Architecture and Opera2ng System (CS31702) 15

Classifica2on of Computer Architecture

• Broadly can be classified into two types:
a) Von-Neumann architecture
b) Harvard architecture

16/01/24 Computer Architecture and Opera2ng System (CS31702) 16

8
 16/01/24

Von-Neumann Architecture
• InstrucCons and data are stored in the same
memory module.
• Suitable for most of the general purpose
Program /
processors. Data
Processor
• Disadvantage: Memory
• The processor-memory bus acts as the boUleneck.
• All instrucCons and data are moved back and forth
through the pipe.

16/01/24 Computer Architecture and Opera2ng System (CS31702) 17

Harvard Architecture
• Separate memory for program and data.
Program
• InstrucCons are stored in program memory Memory
and data are stored in data memory.
Processor
• InstrucCon and data accesses can be done
Data
in parallel. Memory
• However, the processor-memory
boUleneck remains.

16/01/24 Computer Architecture and Opera2ng System (CS31702) 18