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04 Vlsi

The document describes the 16 basic steps for fabricating an NMOS transistor on a silicon substrate. Key steps include growing a silicon dioxide layer, depositing and patterning photoresist to define device regions, etching to form openings, growing a polysilicon gate layer, diffusing dopants to form source and drain regions, and depositing metal layers to connect the devices. The process uses lithography, oxidation, deposition, doping and etching to build up the layers that make up the NMOS transistor on a silicon chip.

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Md. Abdul Mukit
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31 views12 pages

04 Vlsi

The document describes the 16 basic steps for fabricating an NMOS transistor on a silicon substrate. Key steps include growing a silicon dioxide layer, depositing and patterning photoresist to define device regions, etching to form openings, growing a polysilicon gate layer, diffusing dopants to form source and drain regions, and depositing metal layers to connect the devices. The process uses lithography, oxidation, deposition, doping and etching to build up the layers that make up the NMOS transistor on a silicon chip.

Uploaded by

Md. Abdul Mukit
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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VLSI (MOS Fabrication)

Lecture-04

8/17/2022 1
MOS Fabrication
• There are a large number and variety of
Source Gate Drain
basic fabrication steps used in the Polysilicon
production of modern MOS ICs. The same SiO2
process can be used for the designed of
NMOS or PMOS or CMOS devices. The
gate material could be either metal or n+
Body
n+
poly-silicon . The most commonly used p bulk Si
substrate is bulk silicon or silicon-on-
sapphire (SOS). Substrate, body or bulk

NMOS Transistor

8/17/2022 2
NMOS Fabrication
• Step-1: Processing is carried on • Step-2: A layer of silicon dioxide
single crystal silicon of high (SiO2) typically 1 micrometer thick
purity on which required is grown all over the surface of the
Impurities are introduced as wafer to protect the surface.
crystal is grown.

8/17/2022 3
NMOS Fabrication
• Step-3: The surface is now • Step-4: The photo resist layer is
covered with the photoresist then exposed to ultraviolet light
which is deposited onto the through masking which defines
wafer and spun to an even those regions into which diffusion
distribution of the required is to take place together with
thickness. transistor channels.

8/17/2022 4
NMOS Fabrication
• Step-4:

8/17/2022 5
NMOS Fabrication
• Step-5 (a): The substrate now is • Step-5 (b): The remaining
ready to be etched to remove photoresist removed and an
the remaining photoresist at the opening to the substrate created.
substrate and to create an
opening at the substrate.

Opening
ACID
8/17/2022 6
NMOS Fabrication
• Step-6: A layer of the thin oxide • Step-7: A thin layer of polysilicon is
is form SiO2 (0.1 micrometer grown all over the entire chip
typical) is grown over the entire surface of the wafer to from the
chip surface at high temperature. gate.

8/17/2022 7
NMOS Fabrication
• Step-8: A layer of photoresist is • Step-9: Use same lithographic
grown over the polysilicon layer. process to pattern polysilicon.
Photoresist is exposed to UV light.

Used to deposit Polysillicon


8/17/2022 8
in gate area
NMOS Fabrication
• Step-10: Etching will remove the • Step-11: Now diffuse n+ dopants
portion of thin SiO2 which is not and forms n+ regions. n+ doping to
exposed to UV light. form SOURCE and DRAIN.

8/17/2022 9
NMOS Fabrication
• Step-12: A thick layer of SiO2 is • Step-13: To get metallic contact we
again grown. need to add another SiO2 layer. The
contact cuts are formed for S, D
and G.

8/17/2022 10
NMOS Fabrication
• Step-14: Now we need to wire • Step-15: Now for metallization
together the devices. Cover the sputter on aluminum over whole
chip with the field oxide. wafer pattern to remove excess
metal, leaving wires.

8/17/2022 11
NMOS Fabrication
• Step-16: This metal layer is then masked and etched to form the
required interconnection pattern.

Source Gate Drain


Polysilicon
SiO2

n+ n+
Body
p bulk Si

NMOS Transistor

8/17/2022 12

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