6642 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 38, NO.

5, MAY 2023

An Interleaved High Step-Up DC/DC

Converter-Based Three-Winding Coupled
Inductors With Symmetrical Structure
Hongzhu Li , Member, IEEE, Chao Li , Xuanjin Sun , Student Member, IEEE, Lihong Cheng, and Wenrui Li

Abstract—This article proposes an interleaved high step-up con- In recent years, scholars have proposed a series of high step-up
verter based on three-winding coupled inductor (TW-CI) with schemes such as cascade, switched inductor, switched capacitor
symmetrical structure. By utilizing the TW-CI along with a voltage (SC), interleaved technology, isolated voltage boosting, voltage
multiplier cell, the proposed converter achieves high power transfer
ability as well as minimized voltage stress across power switches multiplier cell (VMC), coupled inductor (CI), and other voltage
and diodes. The converter has significantly improved the voltage boosting techniques [1], [2], [3]. The CI is a straightforward,
gain by integrating two TW-CIs with the passive clamp circuit. The efficient, and convenient approach to achieve a high voltage
leakage inductor energy of the TW-CI is recycled to improve the conversion ratio when compared to other voltage boosting tech-
voltage gain and efficiency while facilitating the soft switching con-
niques. The CI converters have the flexibility to adjust the
dition for the power switches. Additionally, the voltage stress across
the power switches is decreased with the help of the clamping ca- turns-ratio to control the necessary voltage gain.
pacitors. Therefore, low-voltage-rated semiconductors with small In various boosting techniques, CI is widely used because
on-resistance can be chosen which reduce conduction losses and of its simplicity and convenience. A series of high step-up
improve the overall performance. Moreover, two series-connected converters with the CI were proposed in [2]. However, the
capacitors of the primary side are introduced, which effectively
leakage inductor of CI would result in voltage spikes, which
balance the voltage between the power switches and the capacitors
during steady and dynamic states. Finally, a 400 W experimental leads to more voltage stress on semiconductors. In [4] and [5],
prototype with 24–400 V is built to verify the accuracy of the the impact of the leakage inductor was eliminated by integrating
proposed converter. the SC technology into the converters. By utilizing the VMCs
Index Terms—Dc–dc converter, high step-up, low voltage stress, with SC, the energy of the leakage inductor is recovered in [6]
three-winding coupled inductor (TW-CI), zero-current switching. and [7]. In this way, the voltage gain had improved and a group
of expandable CI high step-up converters with clamping were
I. INTRODUCTION given.
In high-power applications, the interleaved high step-up con-
O ACHIEVE the global carbon neutrality target, the global
T energy system structure has been adjusted on a regular
basis, and the proportion of new energy sources connected to the
verters were used as an efficient solution to increase the con-
version efficiency, reduce the current ripple, etc. Therefore,
a series of high step-up converters with interleaved structure
power grid has continued to increase. However, the renewable were proposed. The interleaved structure applied to high step-up
energy sources, such as photovoltaic, fuel cells, offer a low volt- converters were presented in [8], [9], and [10]. A high step-up
age level (12∼48 V), which provide insufficient voltage for the active-switched-inductor converter with CI was proposed in
inverter. Therefore, a high step-up and high-performance dc–dc [11]. The interleaved technique is employed into the Sepic in
converter is required. The high step-up and high-performance [12]. By integrating different fundamental converters, a novel
dc–dc converter is directly connected to the renewable energy high step-up converter with interleaved structure was proposed
sources and contributes to raising the voltage to a higher level in [13]. The aforementioned interleaved converters can im-
(200∼400 V). prove the transmission power capability. However, the above
converters are asymmetrical, which makes it challenging to
Manuscript received 25 October 2022; revised 2 January 2023; accepted 10
February 2023. Date of publication 14 February 2023; date of current version 10 select the components. And those converters demand a lot of
March 2023. This work was supported in part by the National Natural Science passive components, which raises the cost. Therefore, a double
Foundation of China under Grant 52177047, in part by the Natural Science switch converter with symmetric structure was proposed in [14],
Foundation of Liaoning Province under Grant 2019-MS-159, and in part by the
Scientific Research Fund of Liaoning Provincial Education Department under which has achieved the voltage balance of power switches and
Grant LJZK0326. Recommended for publication by Associate Editor Q. Shafiee. capacitors in steady and dynamic state.
(Corresponding author: Chao Li.) An interleaved structure with double CI structure was pro-
The authors are with the Faculty of Electrical and Control Engineering,
Liaoning Technical University, Huludao 125105, China (e-mail: lihongzhu@ posed in [15] and [16]. A series of high step-up dc–dc converters
lntu.edu.cn; [email protected]; [email protected]; 2632689062@ with three-winding coupled inductor (TW-CI) were proposed in
qq.com; [email protected]). [17], [18], [19], [20], [21], and [22], which effectively improved
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TPEL.2023.3244809. the voltage gain of the converters. The interleaved converter with
Digital Object Identifier 10.1109/TPEL.2023.3244809 TW-CI was presented in [23], which has improved the voltage
0885-8993 © 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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LI et al.: INTERLEAVED HIGH STEP-UP DC/DC CONVERTER-BASED TW-CIS WITH SYMMETRICAL STRUCTURE 6643

gain and power transfer capability. By integrating TW-CIs with a

VMC, the voltage gain of the interleaved converter was improved
in [24].
Inspired by the mentioned papers, the symmetrical interleaved
dc–dc converter with TW-CI is presented in this article. By using
two capacitors at the input, the voltage balance of the power
switches and capacitors are realized in a steady and dynamic
states. The diode-capacitor cells are used as a passive clamp
to absorb the energy of the leakage inductor, which eliminates
voltage stress across the power switches. In this way, the current
peak and voltage stress of the power switches is effectively
suppressed, and the zero current switching (ZCS) of power
switches are realized.
In this article, an interleaved high step-up converter-based
TW-CI was proposed. The main benefits of the proposed con-
verter can be regarded as follows:
1) Ultrahigh step-up is obtained by integrating two group of
TW-CI.
2) The proposed converter is a symmetrical structure, and the
stresses in the circuit are distributed.
3) The interleaved structure results in shared thermal stress
across the phases and low input current ripple.
4) The ZCS of the power switches are implemented to de-
crease the switching losses, the efficiency has significantly
increased.
5) The voltage stress on the semiconductors is significantly
lower than the output voltage.
6) The current falling rate of the diodes is controlled by the
leakage inductor of the TW-CI.
7) The symmetric construction is used instead of asymmetric
high step-up converters, which is beneficial for reducing
the electromagnetic interference (EMI) of system.
The rest of this article is as follows. The topology of the
proposed converter is presented, and the operating principles are
analyzed in Section II. Section III is devoted to the steady-state
analysis of the proposed converter. The efficiency and loss
Fig. 1. Evolution of topology. (a) High step-up converter with TW-CI.
analysis of the proposed converter are presented in Section IV. (b) Symmetrical high step-up converter with TW-CI. (c) Proposed converter.
The design of the proposed converter is presented in Section V.
Section VI is devoted to the comparative analysis and the exper-
imental results analysis of the proposed converter. Finally, the
conclusion of this article is presented in Section VII.

II. PROPOSITION AND MODAL ANALYSIS OF CONVERTERS

A. Structure of the Proposed Converter
The TW-CI is employed to the basic high step-up converter
with CI. The high step-up converter with TW-CI is shown in
Fig. 1(a). To improve the power transfer ability, the two phase
of the high step-up converter with TW-CI is interleaved, and Fig. 2. Equivalent circuit of the proposed converter.
the new topology is shown in Fig. 1(b). As seen in Fig. 1(c),
the input of the high step-up converter is divided into two
capacitors, which can realize the voltage balance of the power B. Modal Analysis of the Proposed Converter
switches under steady and dynamic states. The voltage gain of The equivalent circuit of the converter is shown in Fig. 2. The
the proposed converter is further enhanced, and its circuitry is TW-CI consists of magnetizing inductor Lm , leakage inductor
symmetrical. The energy of leakage inductor is recycled with Lk , secondary-tertiary wingdings. The turns-ratio of TW-CI are
the help of the clamping capacitors to reduce the voltage spikes ns1 , ns2 , nt1 , and nt2 . The main working waveform in one cycle
of the semiconductors. is shown in Fig. 3.

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6644 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 38, NO. 5, MAY 2023

The magnetizing inductors Lm1 , Lm2 and the leakage inductors

Lk1 , Lk2 are charged by the power supply Vin . The current of
the magnetizing inductors, iLm1 and iLm2 , increase linearly. The
load is supplied by the capacitors Cout1 and Cout2 . Because the
rise speed of the current of leakage inductor iLk1 coincides with
the drop speed of the current of leakage inductor iLk2 , the input
current iin is almost unchanged in this mode. The current flow
in the circuit is shown in Fig. 4(c).
Vin
iLk1 = iLm1 = iLm1 (t2 ) + (t − t2 ) (1)
Lm1
Vin
iLk2 = iLm2 = iLm2 (t2 ) + (t − t2 ) . (2)
Lm2
Mode 4 (t3 ≤ t ≤ t4 ): In this mode, the power switch S1 turns
OFF, and the diodes D12 , D21 , and D23 are forward biased. Since
the magnetizing and leakage inductors are charged by power
supply Vin , the currents iLm1 and iLk1 grow linearly. The C12 is
charged by the power supply Vin and C11 via the D12 . And the
C21 is charged by the leakage inductor Lk2 via the D21 . During
this mode, the input current is determined by adding the currents
of the power switch S2 and diode D23 . The current flow is shown
in Fig. 4(d).
Vin = VC12 − VC11 − VN s1 − VN t2 . (3)
Mode 5 (t4 ≤ t ≤ t5 ): In this mode, the energy of the leakage
inductor Lk2 has been released. The rest of this mode is similar
to mode 4. The current flow is shown in Fig. 4(e).
Mode 6 (t5 ≤ t ≤ t6 ): In this mode, the power switch S1
is turned ON, and the D12 and D23 are forward biased. The
magnetizing inductor Lm2 and the leakage inductor Lk2 are
charged by the power supply Vin and C1 , which causes the
current iLm2 and iLk2 to grow linearly. Though the D23 , the load
absorbs the energy of secondary-tertiary windings Ns2 , Nt1 , and
C12 . Due to the conduction of S1 , the C12 is charge by the Ns1
and Nt2 via D22 . The current flow is shown in Fig. 4(f).
Fig. 3. Key waveform of the proposed converter. Mode 7 (t6 ≤ t ≤ t7 ): In this mode, the power switches
S1 and S2 are ON-state, and the D12 is forward biased. The
power supply Vin charges the magnetizing inductor Lm2 and
Mode 1 (t0 ≤ t ≤ t1 ): At t = t0 , the magnetizing inductor the leakage inductor Lk2 , which causes the current iLm2 and
Lm1 and leakage inductor Lk1 are charged by the source Vin iLk2 to increase linearly. Due to the D13 and D23 are reverse
and capacitor C1 , which result the current iLm1 and iLk1 to biased, the load is supplied by the Cout1 and Cout2 . The current
increase linearly. The energy of C12 and the secondary-tertiary flow is shown in Fig. 4(g).
windings Ns1 , Nt2 are delivered to the load via the diode D13 . Mode 8 (t7 ≤ t ≤ t8 ): In this mode, all of the diodes are
The secondary-tertiary windings Ns1 and Nt2 charge the C22 via reverse biased and the power switch S1 and S2 are kept in the ON-
the D22 . Since the power switch S2 is just turned ON, the input state. The magnetizing inductors Lm1 and Lm2 , and the leakage
current iin will quickly increase. The current flow is shown in inductors Lk1 and Lk2 are linearly charged by the power supply
Fig. 4(a). Vin . During this mode, the current flow in the circuit is shown
Mode 2 (t1 ≤ t ≤ t2 ): During this mode, the power switches in Fig. 4(h). The following relationship can be derived from the
S1 and S2 remain ON-state, the D22 is forward biased. The current of leakage and magnetizing inductor:
magnetizing inductor Lm1 and the leakage inductor Lk1 are
Vin
charged by the power supply Vin , which result the currents iLm1 iLk1 = iLm1 = iLm1 (t7 ) + (t − t7 ) . (4)
and iLk1 to increase linearly. The capacitor C22 is charged by the Lm1
secondary-tertiary windings Ns2 and Nt1 via the D22 . Because Mode 9 (t8 ≤ t ≤ t9 ): In this mode, the power switch S2
the diodes D13 and D23 are reverse biased, the load is charged remains OFF-state, and the D11 , D13 , and D22 are forward biased.
by Cout1 and Cout2 . The current flow in this mode is shown in The magnetizing inductor Lm2 and the leakage inductor Lk2 are
Fig. 4(b). charged by the source Vin , the current of iLm2 and iLk2 increases
Mode 3 (t2 ≤ t ≤ t3 ): In this mode, all of the diodes are reverse linearly. The power supply Vin and the C21 are charged C22 via
biased and the power switches S1 and S2 are kept in the ON-state. the D22 . The leakage inductor Lk1 is charged C11 via the D11 .
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LI et al.: INTERLEAVED HIGH STEP-UP DC/DC CONVERTER-BASED TW-CIS WITH SYMMETRICAL STRUCTURE 6645

Fig. 4. Operation modes in one period. (a) Mode 1 [t0 ∼t1 ]. (b) Mode 2 [t1 ∼t2 ]. (c) Mode 3 [t2 ∼t3 ]. (d) Mode 4 [t3 ∼t4 ]. (e) Mode 5 [t4 ∼t5 ]. (f) Mode 6 [t5 ∼t6 ].
(g) Mode 7 [t6 ∼t7 ]. (h) Mode 8 [t7 ∼t8 ]. (i) Mode 9 [t8 ∼t9 ]. (j) Mode 10 [t9 ∼t10 ].

Through the D13 , the load is charged by C2 and Cout2 . The 3) The capacitance is infinite, and the voltage ripple is ig-
current flow is shown in Fig. 4(i). The following equations can nored.
be achieved for this mode. 4) The turn ratios of the TW-CI are: ns1 = Ns1 /Np1 , ns2 =
Ns2 /Np2 , nt1 = Nt1 /Np1 , nt2 = Nt2 /Np2 .
Vin = VC22 − VC21 − VN s2 − VN t1 (5)
Vin A. Voltage Gain of the Proposed Converter
iLk2 = iLm2 = iLm2 (t7 ) + (t − t7 ) . (6)
Lm2 The coupled coefficient of TW-CI is presumed as follows:
Mode 10 (t9 ≤ t ≤ t10 ): In this mode, the power switch S2 is Lm1 Lm2
forward biased, and the D11 is forward biased. Since the energy k= = . (7)
Lm1 + Lk1 Lm2 + Lk2
of the leakage inductor Lk1 has been discharged. The rest of this
mode is similar to mode 9. The current flow is shown in Fig. 4(j). The secondary-tertiary windings voltage of the TW-CI is
expressed as follows:
⎧
III. STEADY-STATE ANALYSIS OF PROPOSED CONVERTER ⎪
⎪ VN s1 = ns1 VLm1
⎨
VN s2 = ns2 VLm2
For convenience in analysis, the following assumptions are . (8)
⎪
⎪ VN t1 = nt1 VLm1
made: ⎩
VN t2 = nt2 VLm2
1) All of the switching components are an ideal component.
2) The parasitic parameters of the inductive and capacitive To facilitate steady-state analysis, the four short-time transi-
components are ignored. tion modes of modes 1, 2, 6, and 7 are ignored. By applying

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6646 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 38, NO. 5, MAY 2023

Kirchhoff’s voltage law (KVL) to the loops shown in Fig. 4(c),

the following equation can be derived.
(3) (3)
VLm1 = VLm2 = kVin . (9)
By applying KVL to the loops shown in Fig. 4(d), the follow-
ing equations can be obtained.
(4)
VLm1 = kVin (10)
(4) (4)
Vin = VC12 − VC11 − VN s1 − VN t2 (11)
(4)
VLm2 = kVC21 . (12)
By applying KVL to the loops shown in Fig. 4(h), the follow-
ing equation can be derived.
(8) (8)
VLm1 = VLm2 = kVin . (13) Fig. 5. Relationship between k, n, D, and voltage gain.

By applying KVL to the loops shown in Fig. 4(i), the following

equations can be obtained.
1 + knt2 + k (ns1 − nt2 ) (1 − D)
(9) VV psC12 = Vo (24)
VLm2 = kVin (14) 3 + 4n + D
(9) (9) 1 + knt1 + k (ns2 − nt1 ) (1 − D)
Vin = VC22 + VN s2 + VN t1 − VC21 (15) VV psC22 = Vo (25)
3 + 4n + D
(9)
VLm1 = kVC11 . (16) 1
VV psCout1 = VV psCout2 = Vo . (26)
According to the voltage-second balance of the magnetizing 2
inductor Lm1 and Lm2 , the voltage of C11 , C12 , and C22 can be According to (22)–(26), the voltage stress of the capacitors
solved by using (8)–(16): is related to duty and output voltage. The voltage stress of the
D capacitors is lower than the output voltage, and the maximum
VC11 = VC21 = Vin (17) voltage stress is only half of the output voltage.
1−D
  The voltage stress of the power switches and diodes can be
1 + knt2
VC12 = k (ns1 − nt2 ) + Vin (18) calculated as follows.
1−D
  1
1 + knt1 VV psS1 = VV psS2 = Vo (27)
VC22 = k (ns2 − nt1 ) + Vin . (19) 3 + 4n + D
1−D
1
The voltage gain of the converter is deduced as follows: VV psD11 = VV psD21 = Vo (28)
3 + 4n + D
Vo 3 + k (ns1 + ns2 + nt1 + nt2 ) + D 1 + 2n
G= = . (20) VV psD12 = VV psD22 = Vo (29)
Vin 1−D 3 + 4n + D
From (20), the voltage gain of the converter is related to the 1 + 2n
VV psD13 = VV psD23 = Vo . (30)
coupling coefficient k, turns-ratio n, and duty D. The voltage 3 + 4n + D
gain ratio is shown as a function of k, n, and D in Fig. 5.
When the turns ratio is n = ns1 = ns2 = nt1 = nt2 . The voltage According to (27)–(30), the voltage stress across the power
gain is determined as follows: switches and diodes are lower than the output voltage. Therefore,
it is possible to utilize the semiconductors with lower parasitic
Vo 3 + 4kn + D
G= = . (21) parameters (MOSFETs with lower RDS(on) and diodes with lower
Vin 1−D forward drop voltage VF ), which reduces the power losses and
the cost.
B. Voltage Stress of the Proposed Converter According to the charge conservation law of the clamping
According to (8)–(19) and (21), the voltage stress of capac- capacitors, the average current of the output diodes can be
itors C1 , C2 , C11 , C12 , C21 , and C22 are derived as follows: obtained as follows:

1
1−D ID12 = ID13 = ID22 = ID23 = Io . (31)
VV psC1 = VV psC2 = Vo (22) 1−D
2 (3 + 4n + D)
D From the analysis of the converter operating in continuous
VV psC11 = VV psC21 = Vo (23) conduction mode (CCM), the average current of the magnetizing
3 + 4n + D

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LI et al.: INTERLEAVED HIGH STEP-UP DC/DC CONVERTER-BASED TW-CIS WITH SYMMETRICAL STRUCTURE 6647

and leakage inductor is B. Capacitance and Magnetic Loss

3 + 4n + D The loss of the capacitors can be expressed as follows:
ILk1(Avg) = ILk2(Avg) = ILm1 = ILm2 = Io .
2 (1 − D) Pc = 2
Irms−ckj Rckj
(32)
k=1,2 j=1,2
 2 2
IV. EFFICIENCY AND LOSS ANALYSIS OF THE + Irms−ck Rck + Irms−coutk Rcoutk . (39)
PROPOSED CONVERTER k=1,2

The loss analysis of the proposed converter is performed by The RMS current of the capacitors are
considering the loss of the power switches, diodes, capacitors, T 2
and magnetic components. 0 irms−C11 dt
Irms−C11 = Irms−C21 =
T
A. Switch and Diode Loss T 2
0 irms−C21 dt
The power switches realize the ZCS conduction, so the losses =
T
of power switches can be calculated as follows.
2 2
(4n + D + 3) (12n + 3D + 5)
Ps = Irms−s1 Rs1 + Irms−s2 Rs2 = Io (40)
6 (1 − D) (4n + D + 1)
 2 2
Cr Vs1 + Vs2 + (Vs1 Is1−of f + Vs2 Is2−of f ) tf
+ fs T 2
2 0 irms−C12 dt
(33) Irms−C12 = Irms−C22 =
T
where tf and Cr are the falling time and output capacitance of T 2
0 irms−C22 dt
the switches; Vs1 , Vs2 , Is1-off , and Is2-off are the voltage and =
current stress. And the RMS current of the power switches are T

2Io 6
T 2 T 2 = (41)
0 irms−s1 dt 0 irms−s2 dt 3 1−D
Irms−s1 = Irms−s2 = =
T T T 2
0 irms−Cout1 dt
(3 + 4n + D) Io √ Irms−Cout1 = Irms−Cout2 =
= 3 − 2D. (34) T
2 (1 − D)
T 2
The loss of the diodes can be expressed as follows. 0 irms−Cout2 dt
=
T
2
PD = (VF Io + Irms−Djk rDjk ) (35)
j=1,2 k=1,2,3 3D + 1
= Io (42)
3 (1 − D)
where VF is the forward voltage drop of diodes, and the RMS
current of diodes are T 2 T 2
0 irms−C1 dt 0 irms−C2 dt
Irms−C1 = Irms−C2 = =
T 2 T 2 T T
0 irms−D11 dt 0 irms−D21 dt 
Irms−D11 = Irms−D21 = =
T T Io 6
= . (43)
3 1−D
Io 6(3D(D + 8n + 2) + 24n(2n + 1) + 7)
= The loss of the TW-CI includes the loss of copper and mag-
6 (4n + D + 1) (1 − D)
netic.
(36)
PCI = Pcu,CI + Pcore,CI (44)
T 2 T 2
0 irms−D12 dt 0 irms−D22 dt Pcu,CI = 2
rpi + 2
Irms−D12 = Irms−D22 = = Irms−Lki Irms−Lsi rsi
T T i=1,2 i=1,2
2Io 2
= (37) + Irms−Lti rti (45)
3 (1 − D) i=1,2

T 2 T 2 where Irms-Lpi , Irms-Lsi , and Irms-Lti are the current of TW-CI;

0 irms−D13 dt 0 irms−D23 dt
Irms−D13 = Irms−D23 = = and rpi , rsi , and rti are the resistance of TW-CI.
T T
T 2 T 2
2Io
= . (38) 0 irms−Lk1 dt 0 irms−Lk2 dt
Irms−Lk1 = Irms−Lk2 = =
3 (1 − D) T T

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6648 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 38, NO. 5, MAY 2023

Fig. 7. Loss distribution map when power is 400 W.

V. PARAMETER DESIGN OF THE PROPOSED CONVERTER

Fig. 6. Output efficiency of the proposed converter.
This article has built an experimental prototype with
24–400 V, the switching frequency is 50 kHz, and the rated
 power is 400 W.
24n(2n−3D+7)−(21D+62)D+131
Io 3
= (46) A. Design of TW-CI
2 (1 − D)
T 2 T 2
According to (21), the turns-ratio of the TW-CI is related to the
0 irms−N s1 dt 0 irms−N s2 dt voltage gain and duty D. The turns-ratio of TW-CI is calculated
Irms−Ls1 = Irms−Ls2 = =
T T as follows:

2Io 6 1−D D 3
= (47) n≥ Vo − − . (52)
3 1−D 4Vin 4 4

T 2 T 2 The turns-ratio is taken as n = 1 when D is selected as 0.55.

0 irms−N t1 dt 0 irms−N t2 dt Considering the maximum ripple current, the ripple current
Irms−Lt1 = Irms−Lt2 = =
T T coefficient is selected as γ. The minimum value of magnetizing
 inductance can be calculated as follows:
2Io 6
= (48) Vin D Vin D
3 1−D Lm1 = Lm2 = Lm ≥ = . (53)
ΔiLm max fs γILm fs
Pcore,CI = Ve Kc fsα Bmax
β
(49)
The current ripple coefficient is selected as γ = 0.3. According
where Ve represents the volume of the magnet. Bmax is the to (53), the value of TW-CIs should be larger than 52.93 μH.
maximum magnetic flux of the magnetic component. The Kc , Therefore, the value of TW-CIs is chosen as 60 μH.
α, and β are an empirical constant.
The overall loss of the proposed converter is calculated as B. Design of Capacitance
follows.
The capacitance is limited by the maximum ripple of the
PLoss = Ps + PD + Pc + PCI . (50) output voltage and the power. Assuming the voltage ripple
coefficient is α%, the capacitance can be calculated as follows:
The theoretical efficiency is calculated as follows.
Io 2Po
P Cout1 = Cout2 ≥ = . (54)
η= (51) ΔVcout1 fs α%Vo2 fs
P + PLoss
where P represents the output power. The voltage ripple coefficient is taken α = 0.3. According to
The theoretical efficiency of the proposed converter can be (54), the capacitance of Cout1 and Cout2 should be larger than
deduced from equations (33)–(51). When the power is 360 W, 33.3 μF. Considering the commonly used value of capacitor, the
the highest theoretical efficiency is 97.068%, and the measured capacitance of Cout1 and Cout2 is taken as 47 μF.
efficiency is 96.62%. When the converter is operating at the The values of CC11 , CC12 , CC21 , and CC22 are obtained as
rated power of 400 W, the theoretical efficiency is 97.05% and follows:
the measured efficiency is 96.60%. The effect of power on the Io 3 + 4n + D
CC11 = CC21 ≥ = Po (55)
theoretical efficiency is illustrated in Fig. 6. Moreover, the loss ΔVC11 fs α%DVo2 fs
distribution at 400 W rated power is depicted in Fig. 7.
Io
The loss of the proposed converter can be further mitigated by CC12 ≥
choosing the components with smaller parasitic parameters. In ΔVC12 fs
order to decrease the loss of the magnetic component, magnetic 3 + 4n + D
= Po
integration and expanding the cross-sectional area of wire can α% (1 + knt2 + k (ns1 − nt2 ) (1 − D)) Vo2 fs
be used. (56)

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LI et al.: INTERLEAVED HIGH STEP-UP DC/DC CONVERTER-BASED TW-CIS WITH SYMMETRICAL STRUCTURE 6649

TABLE I
MAIN CIRCUIT OF THE CHANGER’S PARAMETERS

Fig. 8. Comparison of voltage gain when n = 1.

Io
CC22 ≥
ΔVC22 fs
3 + 4n + D
= Po .
α% (1 + knt1 + k (ns2 − nt1 ) (1 − D)) Vo2 fs
(57) Fig. 9. Comparison of voltage stress when n = 1.

The turns-ratio is selected as ns1 = ns2 = nt1 = nt2 = 1, the

coupling coefficient is selected as k = 1, and the voltage ripple TW-CI are proposed in [18], [19], [20], and [21]. The TW-CI
coefficient is selected as α = 3. According to (55)–(57), the was combined with SCs in [24].
capacitance of the CC11 and CC21 are obtained as 22.8 μF, and As shown in Fig. 8, the voltage gain of these converters is
the CC12 and CC22 are calculated as 6.29 μF. Considering the illustrated to better compare the difference between the TW-CI
commonly used value of capacitor, the capacitance of the CC11 and the CI converters. In the same conditions of turn-ratios of n
and CC21 are taken as 47 μF and the CC12 and CC22 are selected = 1, Fig. 9 has compared the voltage stress of the proposed and
as 10 μF. The input C1 and C2 are used to realize the voltage the converters in Table II. According to the above-mentioned
balance of the capacitors and power switches. The requirement discussions, the proposed converter with low voltage stress
of the capacitance is not strict, so the capacitance of the C1 and across semiconductors can achieve ultrahigh voltage conversion
C2 is selected as 47 μF. According to the design of components, ratio.
the major components of the proposed converter are shown in
Table I. B. Experimental Results Analysis
A 400 W prototype is built to verify the accuracy of the
VI. COMPARATIVE ANALYSIS AND EXPERIMENTAL proposed converter. Fig. 10(a) shows the input and output
RESULTS ANALYSIS voltage waveforms, which achieves a high voltage conversion
ratio of 24–400 V. The current waveform of TW-CI is shown
A. Comparative Analysis
in Fig. 10(b) and (c). According to Fig. 10(d), the power
The proposed converter is compared with other proposed high switches turn-ON under ZCS with low voltage stress. As shown
step-up converters based on CI. Table II summarizes the number in Fig. 10(e) and (f), the voltage stress across the power switches
of switches, diodes, capacitors, voltage gain, voltage stress, is about 55 V, which is lower than the output voltage. The stress
and magnetic components for each converter. A high step-up waveforms of diodes D11 and D21 are shown in Fig. 10(g) and (j).
converter was obtained by integrating the SC with the coupling The voltage stress of the diodes is about 55 V, which is approx-
inductor in [4]. By utilizing the CI with VMC, the interleaved imately 0.1375 times of the output voltage. The waveforms of
technique was presented in [8], [15], [16], and [21]. A symmetric diodes D12 , D22 , D13 , and D23 , are shown in Fig. 10(h), (k), (i),
dual-switched high step-up converter was proposed in [15]. The and (l), respectively. The waveforms of iLk1 and iLk2 are depicted
active switched-inductor high step-up converters with TW-CI in Fig. 10(m). As illustrated in Fig. 10(n), which depicts the volt-
was presented in [17] and [20], which has enhanced the overall age waveforms of output voltage when the load changes quickly,
performance. The single switch high step-up converters with the output power immediately changed from 200 to 400 W when
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6650 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 38, NO. 5, MAY 2023

Fig. 10. Experimental waveforms. (a) Input and output voltage. (b) Current of the TW-CI 1. (c) Current of the TW-CI 2. (d) ZCS of switches. (e) Voltage and
current stress of S1 . (f) Voltage and current stress of S2 . (g) Voltage and current stress of D11 . (h) Voltage and current stress of D12 . (i) Voltage and current stress
of D13 . (j) Voltage and current stress of D21 . (k) Voltage and current stress of D22 . (l) Voltage and current stress of D23 , 4. (m) Waveforms of iLk1 and iLk2 .
(n) Dynamic response of the change in the load (200 to 400 W). (o) Dynamic response of the change in the input voltage. (p) Input voltage and input current.

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LI et al.: INTERLEAVED HIGH STEP-UP DC/DC CONVERTER-BASED TW-CIS WITH SYMMETRICAL STRUCTURE 6651

TABLE II
COMPARISON OF THE PROPOSED CONVERTER WITH OTHER EXISTED CONVERTER

proposed converter is verified through the experimental results

of the laboratory prototype. The photograph of the prototype is
shown in Fig. 11.

VII. CONCLUSION
By integrating two high step-up dc–dc converters with TW-
CI, this article has proposed an interleaved high step-up dc/dc
converter-based TWCI with symmetrical structure. The theo-
retical analysis and experimental results demonstrate that the
main characteristics of the proposed converter can be regarded
as follows:
1) The proposed converter has a symmetrical structure, the
stress of the circuit semiconductors is small, and it is
suitable for the high power transfer ability.
2) With the help of input and output capacitors, the volt-
Fig. 11. Photograph of the experimental prototype. age stress of power switches is reduced. As the voltage
stress of semiconductors is smaller than output voltage,
the load changed. Fig. 10(o) represents the dynamic response of low-voltage-rating semiconductors are used. The voltage
the proposed converter when the input voltage quickly changes balance of the power switches and the capacitors can be
from 24 to 48 V. The registered results demonstrate the stability realized under steady and dynamic states.
and good dynamics of the converter, which can be experimented 3) Because the power switches achieve ZCS and the diode
under other variable conditions. The voltage and current wave- D11 , D21 turn OFF naturally, the measured efficiency was
form of input is shown in Fig. 10(p). Finally, the accuracy of the measured as 96.6%.

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6652 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 38, NO. 5, MAY 2023

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