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DSP-Unit 5

Digital signal prossesing

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Pranav Pr
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0% found this document useful (0 votes)
17 views20 pages

DSP-Unit 5

Digital signal prossesing

Uploaded by

Pranav Pr
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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‘St Parameters No. 1 Instruction cycle 2 Instruction execution 3 Memories 4 Onchip/or chip memories 5 Program flow control 6 Pipelining 7 Operand Fetch 8 Address and data bus multiplexing, 9 Computational units, 10 Onchip address and data bus 21 Addressing, modes 12 Application DSP processor Instructions are executed in single cycle of the clock Parallel execution is possible. Separate data and program memory. Program and Data memories are present on chip extendable off chip. Program sequencer and instruction register take care of program flow Pipelining is implicate through instruction register and instruction cache. Multiple operands can be fetched simultaneously. Address and data bus are not multiplexed. They are separate ‘on chip as well as off chip. Three separate computational units: ALU, MAC and shifter. Separate address and data bus for program and data memory. Direct and indirect addressing, modes. Signal processing, audio processing, speech processing and array processing etc Microprocessor Multiple clocks cycles are required for execution of one instruction. Execution of instruction is always sequential. No such separate memories are present. Normally on chip cache memory present, main memory is off chip. Program counter take care of flow of execution. Queuing is perform explicate by one queue register to support pipelining, Operands are fetched sequentially Address and data bus are multiplexed. Only one main unit ALU. Address and data bus are the two buses on the chip, Direct, indirect, Register, Register indirect, Immediate addressing mode ete General Purpose applications. Scanned with CamScanner Scanned with CamScanner Scanned with CamScanner Scanned with CamScanner Scanned with CamScanner Scanned with CamScanner Scanned with CamScanner o7 16 bit Busos C ep[a+4h? PPS Bus — Cassy Code + | RR tae Pore Moro pee ee eon +6 CPU ; Pasa 2.005 Pal» Pnchp werner sae Maroong. Pop pp pare Neway Dooce FR % [Jnve], Cee: 42n, PPB Con, p>, 4 — Cay add, —~ Genoriadar Q ABBY oa. oA feycla S ae 2 Proxy keg Pe Mbrropic. Uort — PR Cam © CALAvo+ ID 2. *. P ged do MebipliontAddoy ‘ ae | Aus +o Onc hp pampkoral. , a Scanned with CamScanner 2. Soteine!| Mersey, Q hon —S eo Me = p Oy > PAS S00 Deiat nm epee me , if SPAM — DearS do o.r4— DI er Se viey a MM. —-26C , tay Shorod, P/D pu Pog)vschons ot. Pom phonal Rogie Meappat 1D Date Memory (DM), Go chip Bors ~ Comtans boot loada, MGM heave Proqronm (tata 00 ORDA Bors rasa d a bic ke, @ eccart /roackino Cyclo —As budsiorod gonial ‘ sy Post CRSP Rast part lntordeco. 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Ee Ado, £0 locy Store Unix (c.200), — Compara A high + loro roaxde, - Apcate TR 03 Contac] 44 CTO) Hes Regis r8To) ond Hsensition Raguten Crh) — Helps 7° do Urterbi type. brea Ze “0 yuck Hors colth ere eaee Oo_caty DMdhicare Scanned with CamScanner E = AA WA te mss R20C s4x ARCHITECTURE. ——— A oD . ————— C&4%x Otfeu 7 date addressing mortar, O Trmediaa Ad Lacing mode, ~Fixad daje Valic AH In gtenction, “Fixed addvat in tho. In Setrecwan, (Accuntater Adhereing mola —-A fas farm may eddrocc dor dae I 4O Hho instruction CODiace+ addresting moda eps As - — Date Poimor Aetask. Poi atoy Adee =p tows Sows, bee He IA ethan. Prd ixce--- addrascing moadto_ u lary AagittAL Cro col +o relator “the PARroa\y acdidrore Miarmoxry roapped ~ogisteny Od An cet iag mabe, mapped acgittms Co Utesf a7 , OPpmands adhrascieg rola, to Akh on rove daw Lath Shack. Scanned with CamScanner —All Csan clevies have. Comma 0 Ay, bur Kitten, Onchip periplowt:, — 24 may incl ha GPTO pins, Shs pa@rckl waht Gere. DensratoZ feb) Fook ntehing bag Clecle GAencrs¥or timer, “Dry Controller, et somal port, TDM Sc! pont, Buttraad sorial Part CASPY ~2 GPlo Pins Aco harttien by Sh Contre, t. Bfo- fienenal inper, t.pon chith Cenrcltional Inutrepione Can bo. Saroe, °.xXf_ Lxtowfal tlag Oo-pu, Bricen L=/Aigé trnder Mo Contqes). — Used fo fend shaking Zhu Hee, ~ Sora. Often GPIO pins Qualbtte on selected heviccs, Scanned with CamScanner F~ Time, wan EG bix Heoing Cimete Lotth ee A hip Pacsealoy, Be oT Sevier Cousrax le hammerice ey = NOM, CLkour Cycle, } I ts . ; — ble, COMAZO, timer interrupe t Benorapof BVime Can be. Sopped / ao. ate aosot/Atablod 4y Specific S+atiast “Clock Gererato, Bits. ea Lateran! asc llerar» 1. ~ 02 options Se pap, Cine gen ed oboe PLye —- Aeclucos POM Consumpyta Dinos Mermay Becass Sopolle, — Alto Uiacer Arye fronsder , esWhouws- CPU lohan on, Scanned with CamScanner atid, Scanned with CamScanner System contol ieface »\ « Progam acess generation bogie PAGER) FC PTRARC BRC, RSA REA Dau adie bop (DAGEN) BRAD ARAUT ARDART AAD-BK.DP.SP Merry |) and aterm ine ] KD iam se A Atcumter A 8 Accumatr 8 CCB tabs D 6 dtabes € EB daw bs WIC unt P FB progam ba 5 Bar ser TT mpi AW Ly Barel shite NSWASW select Scanned with CamScanner

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