Course 13

S.Motogna - FL&CD
 Structure of compiler
Source program
analysis
scanning

parsing
Sequence of
tokens

semantic analysis
Parse tree

generate intermediary
Adnotated syntax code synthesis
tree
optimize
Intermediary intermediary code
code
Optimized generate object Object
code program
intermediary
code
S. Motogna - LFTC
Generate object code
= translate intermediary code statements into statements of object
code (machine language)

- Depend on “machine”: architecture and OS

S. Motogna - LFTC
Computer with accumulator
• A stack machine consists of:
• a stack for storing and manipulating values (store subexpressions and
results)
• Accumulator – to execute operation
• 2 types of statements:
• move and copy values in and from head of stack to accumulator
• Operations on stack head, functioning as follows: operands are popped from
stack, execute operation and then put the result in stack

S. Motogna - LFTC
Example: 4 * (5+1)
Code acc stack
acc ← 4 4 <>
push acc 4 <4>
acc ← 5 5 <4>
push acc 5 <5,4>
acc ← 1 1 <5,4>
acc ← acc + head 6 <5,4>
pop 6 <4>
acc ← acc * head 24 <4>
pop 24 <>
S.Motogna - FL&CD
Computer with registers
• Registers +
• Memory

• Instructions:
• LOAD v,R – load value v in register R
• STORE R,v – put value v from register R in memory
• ADD R1,R2 – add to the value from register R1, value from register R2 and
store the result in R1 (initial value is lost!)

S. Motogna - LFTC
2 aspects:
• Register allocation – way in which variable are stored and
manipulated;

• Instruction selection – way and order in which the intermediary code

S. Motogna - LFTC
Remarks:
1. A register can be available or occupied =>
VAR(R) = set of variables whose values are stored in register R

2. For every variable, the place (register, stack or memory) in which the
current value of the value exists=>
MEM(x)= set of locations in which the value of variable x exists (will
be stored in Symbol Table)

S. Motogna - LFTC
Example: F := A ∗ B − (C + B) ∗ (A * B)
Intermediary code Object code VAR MEM
VAR(R0) = {}
VAR(R1) = {}
(1) T1 = A * B
(2) T2 = C + B
(3) T3 = T2 * T1
(4) F:= T1 – T3

S.Motogna - FL&CD
Example: F := A ∗ B − (C + B) ∗ (A * B)
Intermediary code Object code VAR MEM
VAR(R0) = {}
VAR(R1) = {}
(1) T1 = A * B LOAD A, R0 VAR(R0) = {A} MEM(T1) = {R0}
MUL R0, B VAR(R0) = {T1}
(2) T2 = C + B
(3) T3 = T2 * T1
(4) F:= T1 – T3

S.Motogna - FL&CD
Example: F := A ∗ B − (C + B) ∗ (A * B)
Intermediary code Object code VAR MEM
VAR(R0) = {}
VAR(R1) = {}
(1) T1 = A * B LOAD A, R0 VAR(R0) = {T1} MEM(T1) = {R0}
MUL R0, B
(2) T2 = C + B LOAD C, R1 VAR(R1) = {T2} MEM(T2) = {R1}
ADD R1, B
(3) T3 = T2 * T1
(4) F:= T1 – T3

S.Motogna - FL&CD
Example: F := A ∗ B − (C + B) ∗ (A * B)
Intermediary code Object code VAR MEM
VAR(R0) = {}
VAR(R1) = {}
(1) T1 = A * B LOAD A, R0 VAR(R0) = {T1} MEM(T1) = {R0}
MUL R0, B
(2) T2 = C + B LOAD C, R1 VAR(R1) = {T2} MEM(T2) = {R1}
ADD R1, B
(3) T3 = T2 * T1 MUL R1,R0 VAR(R1) = {T3} MEM(T2) = {}
MEM(T3) = {R1}
(4) F:= T1 – T3

S.Motogna - FL&CD
Example: F := A ∗ B − (C + B) ∗ (A * B)
Intermediary code Object code VAR MEM
VAR(R0) = {}
VAR(R1) = {}
(1) T1 = A * B LOAD A, R0 VAR(R0) = {T1} MEM(T1) = {R0}
MUL R0, B
(2) T2 = C + B LOAD C, R1 VAR(R1) = {T2} MEM(T2) = {R1}
ADD R1, B
(3) T3 = T2 * T1 MUL R1,R0 VAR(R1) = {T3} MEM(T2) = {}
MEM(T3) = {R1}
(4) F:= T1 – T3 SUB R0,R1 VAR(R0) = {F} MEM(T1) = {}
STORE RO, F VAR(R1) = {} MEM(F) = {R0, F}

S.Motogna - FL&CD
More about Register Allocation
• Registers – limited resource
• Registers – perform operations / computations
• Variables much more than registers

IDEA: assigning a large number of variables to a reduced number of

S.Motogna - FL&CD
Live variables
• Determine the number of variables that are live (used)
op op1 op2 rez
Example: 1 + b c a
2 + a e d
a=b+c
3 + a c e
d=a+e
1 2 3
e=a+c a x x x
b x
c x x x
d x
e x x
S.Motogna - FL&CD
Graph coloring allocation (Chaitin a.o. 1982)
• Graph:
• nodes = live variables that should be allocated to registers
• edges = live ranges simultaneously live

Register allocation = graph coloring: colors (registers) are assigned to

S.Motogna - FL&CD
Linear scan allocation (Poletto a.o., 1999)
• determine all live range, represented as an interval
• intervals are traversed chronologically
• greedy algorithm

Advantage: speed – code is generated faster (speed in code

S.Motogna - FL&CD
Instruction selection
Example: F := A ∗ B − (C + B) ∗ (A * B)
Intermediary code Object code VAR MEM
VAR(R0) = {}
VAR(R1) = {}
(1) T1 = A * B LOAD A, R0 VAR(R0) = {T1} MEM(T1) = {R0}
MUL R0, B
(2) T2 = C + B LOAD C, R1 VAR(R1) = {T2} MEM(T2) = {R1}
ADD R1, B STORE R0,T1
(3) T3 = T2 * T1 MUL R1,R0 MUL R0,R1 VAR(R1) = {T3} MEM(T2) = {}
MEM(T3) = {R1}
(4) F:= T1 – T3 LOAD T1,R1

Decide which register to use for an instruction

S.Motogna - LFTC
Alan Turing

• Enigma (criptography)
• Turing test
• Turing machine (1937)

S.Motogna - LFTC
Turing Machine
• Mathematical model for computation
• Abstract machine
• Can simulate any algorithm

S.Motogna - LFTC
Turing Machine
• Input band (infinite)
• Reading head
• Control Unit: states
• Transitions / moves

S.Motogna - LFTC
Turing machine – definition
7-tuple M = (Q, 𝞒,b,𝞢,𝞭,q0, F) where:
• Q – finite set of states
• 𝞒 - alphabet (finite set of band symbols)
• b ∈ 𝞒 - blank (symbol)
• 𝞢 ⊆ 𝞒 \{b} – input alphabet L = left
• 𝞭 : (Q\F) x 𝞒 →Q x 𝞒 x {L,R} –transition function R = right
• q0 ∈Q – initial state
• F ⊆Q – set of final states

S.Motogna - LFTC
Example – palindrome over {0,1}
• 001100, 00100, 101101 a.s.o. accepted
• 00110, 1011 a.s.o. not accepted

001100

S.Motogna - LFTC
Example – palindrome over {0,1}
Delete 0 in left side;
0 1 b search 0 in right side
q0 (p1,b,R) (p2,b,R) (qf,b,R)
Delete 1 in left side;
p1 (p1,0,R) (p1,1,R) (q1,b,L) search 1 in right side
On right is 0 or 1?
p2 (p2,0,R) (p2,1,R) (q2,b,L)
Shift right
q1 (qr,b,L) (qf,b,R)
q2 (qr,b,L) (qf,b,R)
q1 and q2 – process 0 and
qr (qr,0,L) (qr,1,L) (q0,b,R) 1 on the right

qf
qf –final state
S.Motogna - LFTC
0110
0 1 1 0
1 1
1 1 0
1 1
1 1 0
1 1
1 1 0

1 1 0 1 1

1 1 0 1

1 1 ...
S.Motogna - LFTC
 0 1 b
q0 (p1,b,R) (p2,b,R) (qf,b,R)

p1 (p1,0,R) (p1,1,R) (q1,b,L)

(q0,0110) |- (p1, 110) |- (p1, 110) p2 (p2,0,R) (p2,1,R) (q2,b,L)

q1 (qr,b,L) (qf,b,R)
q2 (qr,b,L) (qf,b,R)
|- (p1, 110) |- (p1, 110b) |- (q1, 110) qr (qr,0,L) (qr,1,L) (q0,b,R)

qf
|- (qr, 11) |- (qr, 11) |- (qr, b11)

|- (q0, 11) |- . . .

S.Motogna - LFTC
https://turingmachinesimulator.com

S.Motogna - LFTC