Computer Organization and

Architecture: Arithmetic
Ashok Kumar Turuk
Addition and Subtraction of Signed Numbers
 Full adder (FA) logic circuit:
 adds two bits of the same weight, along with a carry-in bit, and produces a sum bit and a
carry-out bit
 Ripple-carry adder:
 a chain of n FA stages, linked by carry bits, can add two n-bit numbers

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Addition and Subtraction of Signed Numbers

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Addition and Subtraction of Signed Numbers

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Addition and Subtraction of Signed Numbers
 Assume a ripple-carry
adder is used to
implement the circuit.
Answer the following:
 How many gate
delay to produce
 all sum bits
 cn
 overflow

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Design of Fast Adders
 Two approaches can be taken to reduce delay in adders.
 The first approach is to use the fastest possible electronic technology.
 The second approach is to use a logic gate network called a carry-look ahead network

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Carry-Lookahead Addition
 A fast adder circuit must speed up the generation of the carry signals
 The logic expressions for si (sum) and ci+1 (carry-out) of stage i
 si = xi ⊕ yi ⊕ ci
 ci+1 = xiyi + xici + yici
 Factoring the second equation into
 ci+1 = xiyi + (xi + yi)ci
 we can write
 ci+1 = Gi + Pici
 where
 Gi = xiyi and Pi = xi + yi
 The expressions Gi and Pi are called the generate and propagate functions for
stage i

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Carry-Lookahead Addition
 Each bit stage contains an AND gate to form Gi , an OR gate to form Pi , and a
three-input XOR gate to form si .
 A simpler circuit can be derived by observing that an adequate propagate
function can be realized as Pi = xi ⊕ yi ,
 which differs from Pi = xi + yi only when xi = yi = 1. But, in this case Gi = 1, so it
does not matter whether Pi is 0 or 1.
 ci+1 = Gi + PiGi−1 + PiPi−1ci−1
 ci+1 = Gi + PiGi−1 + PiPi−1Gi−2 +・ ・ ・+PiPi−1 ・ ・ ・ P1G0 + PiPi−1 ・ ・ ・ P0c0

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Carry-Lookahead Addition
 Delay reduction: produce carry signals in parallel using carry-lookahead circuits

 First, form generate and propagate functions in each stage i

Gi = xiyi Pi = xi + yi

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Carry-Lookahead Addition

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Carry-Lookahead Addition
 A 4-bit adder has four carry-out signals:

c1 = G0 + P0c0

c2 = G1 + P1G0 + P1P0c0

c3 = G2 + P2G1 + P2P1G0 + P2P1P0c0

c4 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0c0

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 Carry-Lookahead Addition

How many gate delay

to add n-bit?
Compare with ripple-
carry adder

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Carry-Lookahead Addition
 For longer operands, gate fan-in is a constraints.
 Last AND gate and the OR gate in carry-lookahead logic requires a fan-in of i + 2 in
generating ci+1.
 A fan-in of 5 is required for c4 in the 4-bit adder. (practical limitation to gates fan-
in).
 Therefore, higher-level generate/propagate functions are used to produce carry
bits in parallel for 4-bit and 16-bit adder blocks

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Carry-Lookahead Addition

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Assignment-01
 Solve problem 6.10 (5th Ed.) or 9.7(6th Ed.) of Hamacher

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Multiplication of Unsigned Numbers
 Two, n-bit, unsigned numbers produce a 2n-bit product when they are multiplied

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Array Multiplier
 Binary multiplication of unsigned operands can be implemented in a
combinational, two dimensional, logic array
 The main component in each cell is a full adder, FA.
 The AND gate in each cell determines whether a multiplicand bit, mj , is added to
the incoming partial-product bit, based on the value of the multiplier bit, qi .
 Each row i, where 0 ≤ i ≤ 3, adds the multiplicand (appropriately shifted) to the
incoming partial product, PPi, to generate the outgoing partial product, PP(i + 1),
if qi = 1.
 If qi = 0, PPi is passed vertically downward unchanged.
 PP0 is all 0s, and PP4 is the desired product.
 The multiplicand is shifted left one position per row by the diagonal signal path.

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Array Multiplier

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Array Multiplier
 The worst-case signal propagation delay path is from the upper right corner of
the array to the high-order product bit output at the bottom left corner of the
array
 This critical path consists of the staircase pattern that includes the two cells at the
right end of each row, followed by all the cells in the bottom row.
 Assuming that there are two gate delays from the inputs to the outputs of a full-
adder block, FA, the critical path has a total of 6(n − 1) − 1 gate delays, including
the initial AND gate delay in all cells, for an n × n array.

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Sequential Circuit Multiplier
 The combinational array multiplier uses a large number of logic gates for
multiplying numbers of practical size, such as 32- or 64-bit numbers.
 Multiplication of two n-bit numbers can also be performed in a sequential circuit
that uses a single n-bit adder.
 Sequential circuit multiplier is composed of three n-bit registers, an n-bit adder,
and a control sequencer
 A sequence of n addition cycles generates a 2n-bit product
 Delay = n x (adder + control delays)
 For n = 32, delay is approximately 32 x 14, or 448 gate delays, assuming a carry-lookahead
adder – more than twice the delay of the corresponding array multiplier

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Sequential Circuit Multiplier

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Sequential Circuit Multiplier

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Figure 11.9
Flowchart for Unsigned Binary
Multiplication START

C, A 0
M Multiplicand
Q Multiplier
Count n

No Yes
Q0 = 1?

C, A A + M

Shift right C, A, Q
Count Count – 1

No Yes
Count = 0? END Product
in A, Q

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 Figure 11.10
Multiplication of Two Unsigned 4-Bit
Integers Yielding an 8-Bit Result

1011
´1101
00001011 1011 ´ 1 ´ 20
00000000 1011 ´ 0 ´ 21
00101100 1011 ´ 1 ´ 22
01011000 1011 ´ 1 ´ 23
10001111

Figure 11.10 Multiplication of Two Unsigned 4-Bit Integers Yielding an 8-Bit

Result

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Multiplication of Signed Numbers

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The Booth Algorithm
 The Booth algorithm generates a 2n-bit product and treats both
positive and negative 2’scomplement n-bit operands uniformly.
 Consider a multiplication operation in which the multiplier is positive
and has a single block of 1s, for example, 0011110 (30)
0100000 (32)
─ 0000010 (2)
 The product can be generated by adding 25 times the multiplicand to
the 2’s-complement of 21 times the multiplicand

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The Booth Algorithm
 We can describe the sequence of required operations by recoding the
preceding multiplier (0011110 ) as 0 +1 0 0 0 −1 0

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The Booth Algorithm

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The Booth Algorithm

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Figure 11.12
Booth’s Algorithm for Twos Complement
Multiplication START

A 0, Q-1 0
M Multiplicand
Q Multiplier
Count n

= 10 Q0 , Q-1 = 01

= 11
= 00
A A–M A A+M

Arithmetic Shift
Right: A, Q, Q -1
Count Count – 1

No Yes
Count = 0? END

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Figure 11.13
Example of Booth’s Algorithm (7 × 3)
A Q Q-1 M
0000 0011 0 0111 Initial Values

1001 0011 0 0111 A A - M First

1100 1001 1 0111 Shift Cycle
Second
1110 0100 1 0111 Shift Cycle

0101 0100 1 0111 A A + M Third

0010 1010 0 0111 Shift Cycle

Fourth
0001 0101 0 0111 Shift
Cycle

Copyright © 2019, 2016, 2013 Pearson Education, Inc. All Rights Reserved
Figure 11.14
Examples Using Booth’s Algorithm
0111 0111
´0011 (0) ´1101 (0)
11111001 1–0 11111001 1–0
0000000 1–1 0000111 0–1
000111 0–1 111001 1–0
00010101 (21) 11101011 (–21)
(a) (7) ´ (3) = (21) (b) (7) ´ (–3) = (–21)

1001 1001
´0011 (0) ´1101 (0)
00000111 1–0 00000111 1–0
0000000 1–1 1111001 0–1
111001 0–1 000111 1–0
11101011 (–21) 00010101 (21)
(c) (–7) ´ (3) = (–21) (d) (–7) ´ (–3) = (21)

Figure 11.14 Examples Using©Booth's

Copyright Algorithm
2019, 2016, 2013 Pearson Education, Inc. All Rights Reserved
Copyright © 2019, 2016, 2013 Pearson Education, Inc. All Rights Reserved
The Booth Algorithm

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The Booth Algorithm

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The Booth Algorithm
 Booth algorithm has two attractive features.
 First, it handles both positive and negative multipliers uniformly.
 Second, it achieves some efficiency in the number of additions required when
the multiplier has a few large blocks of 1s.

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Fast Multiplication
 Neither the combinational array nor the sequential circuit multiplier
are fast enough for high-performance processors

 Two approaches are used for higher speed:

1. Reduce the number of summands

 maximum number of summands (versions of the multiplicand)
that must be added is n/2 for n-bit operands
2. Use more parallelism in adding them
 adding the summands in parallel.

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Bit-Pair Recoding of Multipliers
 bit-pair recoding of the multiplier results in using at most one
summand for each pair of bits in the multiplier.
 Group the Booth-recoded multiplier bits in pairs
 The pair (+1 −1) is equivalent to the pair (0 +1).
 (+1 0) is equivalent to (0 +2),
 (−1 +1) is equivalent to (0 −1)
 If the Booth-recoded multiplier is examined two bits at a time,
starting from the right, it can be rewritten in a form that requires at
most one version of the multiplicand to be added to the partial
product for each pair of multiplier bits.

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Bit-Pair Recoding of Multipliers

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Bit-Pair Recoding of Multipliers

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Bit-Pair Recoding of
Multipliers

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Carry-Save Addition of Summands

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