DSDV Lab (BEC302)

1)To simplify given Boolean expression and realize using Verilog

program
(i) Y= a’b’ + ab
(ii) Y=a’b + ab’

(i) module express(a,b,y);

input a, b;
output y;
assign y= ((~a) & (~b)) | ( a & b);
endmodule

(ii) module express(a,b,y);

input a, b;
output y;

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assign y= ((~a) & (b)) | ( a & (~b));

endmodule

2) To realize Adder/Subtractor (Full/Half)

circuits using data flow description.

a)Verilog code for Half adder

module halfadd(a,b,sum,carry);
input a,b;
output sum,carry;
assign sum= a ^ b;
assign carry = a & b;
endmodule

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 ii. Verilog code for Full adder
module fulladd(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
assign sum= a ^ b ^ c;
assign carry = (a & b)| (b & c) | (c & a);
endmodule

(iii) Verilog code for half subtractor

module halfsub(a,b,diff,borr);
input a, b;
output diff,borr;
assign diff= a ^ b;
assign borr= ((~a) & b);
endmodule

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 (iv) Verilog program for full subtractor

module fullsub(a,b,c,diff,borr);
input a,b,c;
output diff,borr;
assign diff= a ^ b ^ c;
assign borr= ((~a)&b) | ((~a) &c) | (b & c);
endmodule

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3) Verilog code for 4 bit ALU using behavioral description

module alu(a,b, opcode,enable,result);

Input signed [3:0] a,b;------ a3 a2 a1 a0
Input [2:0] opcode;
Input enable;
Output [4:0] result;
reg [4:0] result;
always @ (opcode,a,b,enable)
begin
If (enable==0)
begin
result=4’bX;
end
else

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begin
Case (opcode)
3’b000:result=a +b;
3’b001:result=a-b;
3’b010:result=a+1;
3’b011:result=a-1;
3’b100:result=!a;
3’b101:result=~a;
3’b110:result=a|b;
3’b111:result=a & b;
endcase
result[4]=1’b1;
end
endmodule

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4) Verilog code for 3:8 Decoder using behavioral
description
module decoder(a, en, d);
input [2:0] a;
input en;
output [7:0] d;
reg [7:0] d;
always @(en, a)
begin
if (en==0)
d<=8'b00000000;
else
case (a)
3'b000:d<=8'b00000001;

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3'b001:d<=8'b00000010;
3'b010:d<=8'b00000100;
3'b011:d<=8'b00001000;
3'b100:d<=8'b00010000;
3'b101:d<=8'b00100000;
3'b110:d<=8'b01000000;
3'b111:d<=8'b10000000;
default:d<=8'b00000000;
endcase
end
endmodule

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4) Verilog code for 8:3 Encoder without priority
module encoder(i,y);
input [7:0] i;
Output [2:0] y;
reg [2:0] y;
always @ (i)
begin
Case (i)
8’b00000001:y=3’b000;
8’b00000010:y=3’b001;
8’b00000100:y=3’b010;
8’b00001000:y=3’b011;
8’b00010000:y=3’b100;
8’b00100000:y=3’b101;

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8’b01000000:y=3’b110;
8’b10000000:y=3’b111;
default:y=3’bXXX;
endcase
end
endmodule

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6) Verilog code for 8:3 encoder with priority
module encoepr(i,y);
input [7:0] i;
output [2:0] y;
reg [2:0] y;
always @ (i)
begin
if (i[7]==1)
y=3'b111;
else if (i[6]==1)
y=3'b110;
else if (i[5]==1)

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y=3'b101;
else if (i[4]==1)
y=3'b100;
else if (i[3]==1)
y=3'b011;
else if (i[2]==1)
y=3'b010;
else if (i[1]==1)
y=3'b001;
else
y=3'b000;
end
endmodule

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6)(i) Verilog code for 8:1 multiplexer using case
statement
module mux(i,s,y);
input [7:0] i;
input [2:0] s;
output y;
reg y;
always@ (i,s)
begin
case (s)
3’b000:y=i[0];
3’b001:y=i[1];
3’b010:y=i[2];
3’b011:y=i[3];

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3’b100:y=i[4];
3’b101:y=i[5];
3’b110:y=i[6];
3’b111:y=i[7];
endcase
end
endmodule

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7) Write a verilog code for the following flip flops:
I) D flip flop
ii) JK flip flop
iii)SR flip flop
iv) T flip flop
Verilog code for D flip flop:
module DFF(d,clk,q,qb);
input d,clk;
output q,qb;
reg q,qb;
always @(posedge clk)
begin
q=d;
qb=~q;

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end
endmodule

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(ii)Verilog code for JK Flip flop:
module JKFF(JK,clk,q,qb);
input clk;
input [1:0] JK;
output q,qb;
reg q,qb;
always @(posedge clk)
begin
case (JK)
2’b00:q=q;
2’b01:q=0;
2’b10:q=1;
2’b11:q=~q;
endcase

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qb=~q;
end
endmodule

9) Verilog code for 4 bit BCD counter

module bcdcounter (clk,rst,q);

input clk,rst;
output [3:0] q;

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reg [3:0] q;
always @(posedge clk)
begin
if (rst)
q=4’b0000;
else if (q<4’b1001)
begin
q=q+1;
end
else if (q==4’b1001)
begin
q=4’b0000;
end
end

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endmodule

10) Verilog code for 4 bit binary counter

Module bincounter(clk,rst,q);
input rst,clk;
output [3:0] q;
reg [3:0] q;
always @(posedge clk)
begin

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if (rst==1’b1)
begin
q=4’b0000;
end
else if (clk)
begin
q=q+1;
end
end
endmodule

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11) Verilog code for T-flip flop
module TFF(t,rst,clk,q,qb);
input t,rst,clk;
output q,qb;
reg q,qb;
always @(posedge clk)

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begin
if (rst)
q=0;
else if (t==0)
q=q;
else if (t==1)
begin
q=~q;
qb=~q;
end
end
endmodule

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6)(ii)Verilog code for 1:8 demultiplexer
module demux(i, s,y);
input i;
input [2:0] s;
output [7:0] y;
reg [7:0] y;
always @( i,s)
begin
case (s)
3’b000:y[0]=i;
3’b001:y[1]=i;
3’b010:y[2]=i;

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3’b011:y[3]=i;
3’b100:y[4]=i ;
3’b101:y[5]= i;
3’b110:y[6]=i;
3’b111:y[7]=i;
default: y=8’bZZZZZZZZ;
endcase
end
endmodule
Program: Write a verilog code for 4 bit binary to
gray code converter
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1

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0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0 1 1 1 1
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1 1 0 0 0

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module bintogray(B,G);
input [3:0] B;
output [3:0] G;
assign G[3]=B[3];
assign G[2]=B[3] ^ B[2];
assign G[1]=B[2] ^ B[1];
assign G[0]=B[1] ^ B[0];
endmodule

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Program: Write a verilog code for 4 bit binary to
Excess-3 converter
B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0

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1 0 1 1
1 1 0 0 1 1 1 1

case (b)
4’b0000:e=4’b0011;
6) Verilog program for 2 bit magnitude comparator
module comp (a b, lt, gt, et);
input [1:0] a;
input [1:0]b;
output lt, gt, et;

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 reg lt, gt, et;
always @ (a,b)
begin
if (a <b)
lt=1'b1;
else
lt=1'b0;
if (a>b )
gt=1'b1;
else
gt=1'b0;
if (a ==b)
et =1'b1;
else

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 et =1'b0;

end
endmodule

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