VLSI TESTING AND TESTABILITY LAB REPORT

MVLD506P

Prepared by
Akhilendra Shilpi
22MVD1044
M.TECH VLSI DESIGN

Under the guidance Of

Dr. G.Umadevi
Associate Professor
SENSE-VIT CHENNAI
 LIST OF EXPERIMENTS
Experiment Experiment Name Date
Number
1. Fault Simulation and Test pattern generation for a
combinational circuit
2. Fault Simulation of Bench Mark Circuit with
collapsing – C17 circuit
3.(A) ATPG generation for combinational circuits C17
(Atalanta, FSim, Hope)
3.(B) ATPG generation for combinational circuits MUX
(Atalanta, FSim, Hope)
4. DFT SYNTHESIS
Experiment1: Fault Simulation and Test pattern generation for a
combinational circuit
Aim: To find the test patterns for the stuck at 0 (SA0) or stuck at 1 (SA1) fault
injected in the combinational circuit.
EDA Tools Used: ModelSim
Description: A stuck-at fault is a particular fault model used by fault simulators
and automatic test pattern generation (ATPG) tools to mimic a manufacturing
defect within an integrated circuit. Individual signals and pins are assumed to
be stuck at Logical '1', '0' and 'X'. Here, the wires w7, w5 and w2 are tied to a
logical 0 state during test generation to assure that a manufacturing defect
(stuck-at 0 – SA0 fault) with that type of behavior can be found with a specific
test pattern. Likewise, the wires w8, w5 and w2 are tied to a logical 1 to model
the behavior of a defective circuit (stuck-at 1 – SA1 fault) that cannot switch its
output pin. When the output of fault-free circuit and that of fault injected
circuit varies, it implies the respective stuck-at fault can be detected by the
corresponding test pattern.
Combinational Circuit Diagram:
Verilog Codes:
//Verilog code of combinational circuit with no faults
module faultfree(y1,y2,a,b,c,d);
input a,b,c,d;
output y1,y2;
wire w1,w2,w3,w4,w5,w6,w7,w8;
not I1(w1,b);
and A1(w2,w1,a);
or O1(w3,c,d);
and A2(w4,w2,a);
nand N1(w5,w3,w2);
or O2(w6,w3,d);
nand N2(w7,w5,w4);
nor E1(w8,w6,w2,w5);
or A3(y1,w7,d);
nand A4(y2,a,w8);
endmodule

//Verilog code of combinational circuit with fault-1 SA--0 at wire w7

module f1_sa0(y1_f1,y2_f1,a,b,c,d);
input a,b,c,d;
output y1_f1,y2_f1;
wire w1,w2,w3,w4,w5,w6,w7,w8,f1;
not I1(w1,b);
and A1(w2,w1,a);
or O1(w3,c,d);
and A2(w4,w2,a);
nand N1(w5,w3,w2);
or O2(w6,w3,d);
nand N2(w7,w5,w4);
and Fault(f1,w7,1'b0);
nor E1(w8,w6,w2,w5);
or A3(y1_f1,f1,d);
nand A4(y2_f1,a,w8);
endmodule

//Verilog code of combinational circuit with fault-2 SA-0 at wire w5

module f2_sa0(y1_f2,y2_f2,a,b,c,d);
input a,b,c,d;
output y1_f2,y2_f2;
wire w1,w2,w3,w4,w5,w6,w7,w8,f2;
not I1(w1,b);
and A1(w2,w1,a);
or O1(w3,c,d);
and A2(w4,w2,a);
nand N1(w5,w3,w2);
or O2(w6,w3,d);
and fault(f2,w5,1'b0);
nand N2(w7,f2,w4);
nor E1(w8,w6,f2,w2);
or A3(y1_f2,w7,d);
nand A4(y2_f2,a,w8);
endmodule

//Verilog code of combinational circuit with fault-3 SA-0 at wire w2

module f3_sa0(y1_f3,y2_f3,a,b,c,d);
input a,b,c,d;
output y1_f3,y2_f3;
wire w1,w2,w3,w4,w5,w6,w7,w8,f3;
not I1(w1,b);
and A1(w2,w1,a);
and Fault(f3,w2,1'b0);
or O1(w3,c,d);
and A2(w4,f3,a);
nand N1(w5,w3,f3);
or O2(w6,w3,d);
nand N2(w7,w5,w4);
nor E1(w8,w6,f3,w5);
or A3(y1_f3,w7,d);
nand A4(y2_f3,a,w8);
endmodule

//Verilog code of combinational circuit with fault-4 SA-1 at wire w8

module f4_sa_1(y1_f4,y2_f4,a,b,c,d);
input a,b,c,d;
output y1_f4,y2_f4;
wire w1,w2,w3,w4,w5,w6,w7,w8,f4;
not I1(w1,b);
and A1(w2,w1,a);
or O1(w3,c,d);
and A2(w4,w2,a);
nand N1(w5,w3,w2);
or O2(w6,w3,d);
nand N2(w7,w5,w4);
nor E1(w8,w6,w2,w5);
or fault(f4,w8,1'b1);
or A3(y1_f4,w7,d);
nand A4(y2_f4,a,f4);
endmodule

//Verilog code of combinational circuit with fault5 SA-1 at wire w5

module f5_sa_1(y1_f5,y2_f5,a,b,c,d);
input a,b,c,d;
output y1_f5,y2_f5;
wire w1,w2,w3,w4,w5,w6,w7,w8,f5;
not I1(w1,b);
and A1(w2,w1,a);
or O1(w3,c,d);
and A2(w4,w2,a);
nand N1(w5,w3,w2);
or O2(w6,w3,d);
or fault(f5,w5,1'b1);
nand N2(w7,f5,w4);
nor E1(w8,w6,w2,f5);
or A3(y1_f5,w7,d);
nand A4(y2_f5,a,w8);
endmodule

//Verilog code of combinational circuit with fault-6 SA-1 at wire w2

module f6_sa_1(y1_f6,y2_f6,a,b,c,d);
input a,b,c,d;
output y1_f6,y2_f6;
wire w1,w2,w3,w4,w5,w6,w7,w8,f6;
not I1(w1,b);
and A1(w2,w1,a);
or O1(w3,c,d);
or fault(f6,w2,1'b1);
and A2(w4,f6,a);
nand N1(w5,w3,f6);
or O2(w6,w3,d);
nand N2(w7,w5,w4);
nor E1(w8,w6,f6,w5);
or A3(y1_f6,w7,d);
nand A4(y2_f6,a,w8);
endmodule

// Test Bench
module tb;
reg a,b,c,d;
wire y1,y2;
wire y1_f1,y2_f1;
faultfree dut2(y1,y2,a,b,c,d);
f1_sa0 dut1(y1_f1,y2_f1,a,b,c,d);
integer i;
initial
begin
{a,b,c,d}=0;
$monitor("a b c d=%b%b%b%b \t y1 y2=%b%b \t y1_f1 y2_f1=%b
%b",a,b,c,d,y1,y2,y1_f1,y2_f1);
for(i=0;i<=15;i=i+1)
begin
#5 {a,b,c,d}={a,b,c,d}+1;
if((y1!=y1_f1)||(y2!=y2_f1))
$display("Fault is Detected\n");
end
#50 $finish;
end
endmodule
Simulation Results:
FAULT -1 SA-0
a b c d=0000 y1 y2=11 y1_f1 y2_f1=01
a b c d=0010 y1 y2=11 y1_f1 y2_f1=01
a b c d=0100 y1 y2=11 y1_f1 y2_f1=01
a b c d=0110 y1 y2=11 y1_f1 y2_f1=01
a b c d=1010 y1 y2=11 y1_f1 y2_f1=01
a b c d=1100 y1 y2=11 y1_f1 y2_f1=01
a b c d=1110 y1 y2=11 y1_f1 y2_f1=01
FAULT -2 SA-0
a b c d=1000 y1 y2=01 y1_f2 y2_f2=11
a b c d=1100 y1 y2=11 y1_f2 y2_f2=10
FAULT -3 SA-0
a b c d=1000 y1 y2=01 y1_f3 y2_f3=11
FAULT -4 SA-1
a b c d=1000 y1 y2=01 y1_f4 y2_f4=00
a b c d=1001 y1 y2=11 y1_f4 y2_f4=10
a b c d=1010 y1 y2=11 y1_f4 y2_f4=10
a b c d=1011 y1 y2=11 y1_f4 y2_f4=10
a b c d=1100 y1 y2=11 y1_f4 y2_f4=10
a b c d=1101 y1 y2=11 y1_f4 y2_f4=10
a b c d=1110 y1 y2=11 y1_f4 y2_f4=10
a b c d=1111 y1 y2=11 y1_f4 y2_f4=10
FAULT -5 SA-1
a b c d=1010 y1 y2=11 y1_f5 y2_f5=01
FAULT -6 SA-1
a b c d=1100 y1 y2=11 y1_f6 y2_f6=01

Simulation Observations:
Simulation Waveforms:
FAULT -1 SA-0

FAULT -2 SA-0
FAULT -3 SA-0

FAULT -4 SA-1
FAULT -5 SA-1
FAULT -6 SA-1

Inference: In the above output waveform, the faults are detected whenever y1
and y2 are not equal to the corresponding outputs during the presence of fault.
Result: Hence the test patterns have been found out for the stuck at 0 (SA0) or
stuck at 1 (SA1) fault injected in the combinational circuit
Experiment2: Fault Simulation of benchmark circuit with collapsing
– C17 circuit
Aim: To find the test patterns for the stuck at 0 (SA0) or stuck at 1 (SA1) fault
injected in the combinational circuit by Fault collapsing.
EDA Tools Used: ModelSim
Description:
A stuck-at fault is a particular fault model used by fault simulators and
automatic test pattern generation (ATPG) tools to mimic a manufacturing
defect within an integrated circuit. Individual signals and pins are assumed
to be stuck at Logical '1', '0' and 'X'. The wires tied to a logical 0 state during
test generation to assure that a manufacturing defect (stuck-at 0 – SA0 fault)
with that type of behaviour can be found with a specific test pattern.
Likewise, the wires tied to a logical 1 to model the behaviour of a defective
circuit (stuck-at 1 – SA1 fault) that cannot switch its output pin. Here, total
17 wires have 34 stuck-at faults and by applying Equivalence and Dominance
collapsing, it is reduced to 22 collapsed set of faults. When the output of
fault-free circuit and that of fault injected circuit varies, it implies the
respective stuck-at fault can be detected by the corresponding test pattern.
 Combinational Circuit Diagram:
TASK-1 TASK-2

TASK-ONE 34 Faults
Verilog Codes:
//Verilog code of combinational circuit with no faults (fault free)
module expt_two(a,b,c,d,e,o22,o23);//fault free

input a,b,c,d,e;

output o22,o23;

wire i10,i11,i16,i19;

nand a1(i10,a,c);

nand a2(i11,c,d);

nand a3(i16,b,i11);

nand a4(i19,i11,e);

nand a5(o22,i10,i16);
 nand a6(o23,i16,i19);

endmodule

module fault1_in_A_SA0(a,b,c,d,e,o22_f1,o23_f1);//fault free

input a,b,c,d,e;

output o22_f1,o23_f1;

wire i10,i11,i16,i19,in_a_sa0;

nand a1(i10,in_a_sa0,c);

nand a2(i11,c,d);

nand a3(i16,b,i11);

nand a4(i19,i11,e);

nand a5(o22_f1,i10,i16);

nand a6(o23_f1,i16,i19);

and fault1_A_SA0(in_a_sa0,a,1'b0);

endmodule

module fault2_in_A_SA1(a,b,c,d,e,o22_f2,o23_f2);//fault free

input a,b,c,d,e;

output o22_f2,o23_f2;

wire i10,i11,i16,i19,in_a_sa1;

nand a1(i10,in_a_sa1,c);
 nand a2(i11,c,d);

nand a3(i16,b,i11);

nand a4(i19,i11,e);

nand a5(o22_f2,i10,i16);

nand a6(o23_f2,i16,i19);

or fault2_A_SA1(in_a_sa1,a,1'b1);

endmodule

module fault3_in_B_SA0(a,b,c,d,e,o22_f3,o23_f3);//fault free

input a,b,c,d,e;

output o22_f3,o23_f3;

wire i10,i11,i16,i19,in_b_sa0;

nand a1(i10,a,c);

nand a2(i11,c,d);

nand a3(i16,in_b_sa0,i11);

nand a4(i19,i11,e);

nand a5(o22_f3,i10,i16);

nand a6(o23_f3,i16,i19);

and b__sa0(in_b_sa0,1'b0,b);
endmodule

module fault4_in_B_SA1(a,b,c,d,e,o22_f4,o23_f4);//fault free

input a,b,c,d,e;

output o22_f4,o23_f4;

wire i10,i11,i16,i19,in_b_sa1;

nand a1(i10,a,c);

nand a2(i11,c,d);

nand a3(i16,in_b_sa1,i11);

nand a4(i19,i11,e);

nand a5(o22_f4,i10,i16);

nand a6(o23_f4,i16,i19);

or b__sa1(in_b_sa1,1'b1,b);

endmodule

module fault5_in_C_SA0_a2(a,b,c,d,e,o22_f5,o23_f5);//fault free

input a,b,c,d,e;

output o22_f5,o23_f5;

wire i10,i11,i16,i19,in_c_sa0_a2;

nand a1(i10,a,c);

nand a2(i11,in_c_sa0_a2,d);
 nand a3(i16,b,i11);

nand a4(i19,i11,e);

nand a5(o22_f5,i10,i16);

nand a6(o23_f5,i16,i19);

and csa0(in_c_sa0_a2,c,1'b0);

endmodule

module fault6_in_C_SA1_a2(a,b,c,d,e,o22_f6,o23_f6);//fault free

input a,b,c,d,e;

output o22_f6,o23_f6;

wire i10,i11,i16,i19,in_c_sa1_a2;

nand a1(i10,a,c);

nand a2(i11,in_c_sa1_a2,d);

nand a3(i16,b,i11);

nand a4(i19,i11,e);

nand a5(o22_f6,i10,i16);

nand a6(o23_f6,i16,i19);

or csa1(in_c_sa1_a2,c,1'b1);

endmodule

module fault7_in_C_SA0_a1(a,b,c,d,e,o22_f7,o23_f7);//fault free

input a,b,c,d,e;

output o22_f7,o23_f7;

wire i10,i11,i16,i19,in_c_sa0_a1;

nand a1(i10,a,in_c_sa0_a1);

nand a2(i11,c,d);

nand a3(i16,b,i11);

nand a4(i19,i11,e);

nand a5(o22_f7,i10,i16);

nand a6(o23_f7,i16,i19);

and csa0__a1(in_c_sa0_a1,1'b0,c);

endmodule

module fault8_in_C_SA1_a1(a,b,c,d,e,o22_f8,o23_f8);//fault free

input a,b,c,d,e;

output o22_f8,o23_f8;

wire i10,i11,i16,i19,in_c_sa1_a1;

nand a1(i10,a,in_c_sa1_a1);

nand a2(i11,c,d);

nand a3(i16,b,i11);

nand a4(i19,i11,e);

nand a5(o22_f8,i10,i16);
 nand a6(o23_f8,i16,i19);

or csa1__a1(in_c_sa1_a1,1'b1,c);

endmodule

module fault9_dsa0_a2(a,b,c,d,e,o22_f9,o23_f9);//fault free

input a,b,c,d,e;

output o22_f9,o23_f9;

wire i10,i11,i16,i19,dsa0_a2;

nand a1(i10,a,c);

nand a2(i11,c,dsa0_a2);

nand a3(i16,b,i11);

nand a4(i19,i11,e);

nand a5(o22_f9,i10,i16);

nand a6(o23_f9,i16,i19);

and dsa0__a2(dsa0_a2,1'b0,d);

endmodule

module fault10_dsa1_a2(a,b,c,d,e,o22_f10,o23_f10);//fault free

input a,b,c,d,e;

output o22_f10,o23_f10;

wire i10,i11,i16,i19,dsa1_a2;
 nand a1_1(i10,a,c);

nand a2_1(i11,c,dsa1_a2);

nand a3_1(i16,b,i11);

nand a4_1(i19,i11,e);

nand a5_1(o22_f10,i10,i16);

nand a6_1(o23_f10,i16,i19);

or dsa1___a2(dsa1_a2,1'b1,d);

endmodule

module fault11_esa0_a4(a,b,c,d,e,o22_f11,o23_f11);//fault free

input a,b,c,d,e;

output o22_f11,o23_f11;

wire i10,i11,i16,i19,esa0_a4;

nand a1_2(i10,a,c);

nand a2_2(i11,c,d);

nand a3_2(i16,b,i11);

nand a4_2(i19,i11,esa0_a4);

nand a5_2(o22_f11,i10,i16);

nand a6_2(o23_f11,i16,i19);

and esa0__a4(esa0_a4,1'b0,e);
endmodule

module fault12_esa1_a4(a,b,c,d,e,o22_f12,o23_f12);//fault free

input a,b,c,d,e;

output o22_f12,o23_f12;

wire i10,i11,i16,i19,esa1_a4;

nand a1(i10,a,c);

nand a2(i11,c,d);

nand a3(i16,b,i11);

nand a4(i19,i11,esa1_a4);

nand a5(o22_f12,i10,i16);

nand a6(o23_f12,i16,i19);

or esa1__a4(esa1_a4,1'b1,d);

endmodule

module fault13_i11_sa0_a4(a,b,c,d,e,o22_f13,o23_f13); //fault free

input a,b,c,d,e;

output o22_f13,o23_f13;

wire i10,i11,i16,i19,i11_sa0_a4;

nand a122(i10,a,c);

nand a222(i11,c,d);
 nand a322(i16,b,i11);

nand a422(i19,i11_sa0_a4,e);

nand a522(o22_f13,i10,i16);

nand a622(o23_f13,i16,i19);

and i11___sa0_a4(i11_sa0_a4,1'b0,i11);

endmodule

module fault14_i11_sa1_a4(a,b,c,d,e,o22_f14,o23_f14);//fault free

input a,b,c,d,e;

output o22_f14,o23_f14;

wire i10,i11,i16,i19,i11_sa1_a4;

nand a133(i10,a,c);

nand a233(i11,c,d);

nand a333(i16,b,i11);

nand a433(i19,i11_sa1_a4,e);

nand a533(o22_f14,i10,i16);

nand a633(o23_f14,i16,i19);

or i11__sa1_a4(i11_sa1_a4,1'b1,i11);

endmodule

module fault15_i11_sa0_a3(a,b,c,d,e,o22_f15,o23_f15);//fault free

input a,b,c,d,e;

output o22_f15,o23_f15;

wire i10,i11,i16,i19,i11_sa0_a3;

nand a144(i10,a,c);

nand a244(i11,c,d);

nand a344(i16,b,i11_sa0_a3);

nand a444(i19,i11,e);

nand a544(o22_f15,i10,i16);

nand a644(o23_f15,i16,i19);

and i11__sa0_a3(i11_sa0_a3,1'b0,i11);

endmodule

module fault16_i11_sa1_a3(a,b,c,d,e,o22_f16,o23_f16);//fault free

input a,b,c,d,e;

output o22_f16,o23_f16;

wire i10,i11,i16,i19,i11_sa1_a3;

nand a155(i10,a,c);

nand a255(i11,c,d);

nand a355(i16,b,i11_sa1_a3);

nand a455(i19,i11,e);

nand a555(o22_f16,i10,i16);
 nand a655(o23_f16,i16,i19);

or i11__sa1_a3(i11_sa1_a3,1'b1,i11);

endmodule

module fault17_i10_sa0_a5(a,b,c,d,e,o22_f17,o23_f17);//fault free

input a,b,c,d,e;

output o22_f17,o23_f17;

wire i10,i11,i16,i19,i10_sa0_a5;

nand a166(i10,a,c);

nand a266(i11,c,d);

nand a366(i16,b,i11);

nand a466(i19,i11,e);

nand a566(o22_f17,i10_sa0_a5,i16);

nand a666(o23_f17,i16,i19);

and i10__sa0_a5(i10_sa0_a5,1'b0,i10);

endmodule

module fault18_i10_sa1_a5(a,b,c,d,e,o22_f18,o23_f18);//fault free

input a,b,c,d,e;

output o22_f18,o23_f18;

wire i10,i11,i16,i19,i10_sa1_a5;
 nand a177(i10,a,c);

nand a277(i11,c,d);

nand a377(i16,b,i11);

nand a477(i19,i11,e);

nand a577(o22_f18,i10_sa1_a5,i16);

nand a677(o23_f18,i16,i19);

or i10__sa1_a5(i10_sa1_a5,1'b1,i10);

endmodule

module fault19_i16_sa0_a5(a,b,c,d,e,o22_f19,o23_f19);//fault free

input a,b,c,d,e;

output o22_f19,o23_f19;

wire i10,i11,i16,i19,i16_sa0_a5;

nand a188(i10,a,c);

nand a288(i11,c,d);

nand a388(i16,b,i11);

nand a488(i19,i11,e);

nand a588(o22_f19,i10,i16_sa0_a5);

nand a688(o23_f19,i16,i19);

and i16__sa0_a5(i16_sa0_a5,1'b0,i16);
endmodule

module fault20_i16_sa1_a5(a,b,c,d,e,o22_f20,o23_f20);//fault free

input a,b,c,d,e;

output o22_f20,o23_f20;

wire i10,i11,i16,i19,i16_sa1_a5;

nand a199(i10,a,c);

nand a299(i11,c,d);

nand a399(i16,b,i11);

nand a499(i19,i11,e);

nand a599(o22_f20,i10,i16_sa1_a5);

nand a699(o23_f20,i16,i19);

or i16__sa1_a5(i16_sa1_a5,1'b1,i16);

endmodule

module fault21_i16_sa0_a6(a,b,c,d,e,o22_f21,o23_f21);//fault free

input a,b,c,d,e;

output o22_f21,o23_f21;

wire i10,i11,i16,i19,i16_sa0_a6;

nand a100(i10,a,c);

nand a200(i11,c,d);
 nand a300(i16,b,i11);

nand a400(i19,i11,e);

nand a500(o22_f21,i10,i16);

nand a600(o23_f21,i16_sa0_a6,i19);

and i16__sa0_a6(i16_sa0_a6,1'b0,i16);

endmodule

module fault22_i16_sa1_a6(a,b,c,d,e,o22_f22,o23_f22); //fault free

input a,b,c,d,e;

output o22_f22,o23_f22;

wire i10,i11,i16,i19,i16_sa1_a6;

nand a101(i10,a,c);

nand a201(i11,c,d);

nand a301(i16,b,i11);

nand a401(i19,i11,e);

nand a501(o22_f22,i10,i16);

nand a601(o23_f22,i16_sa1_a6,i19);

or i16__sa1_a6(i16_sa1_a6,1'b1,i16);

endmodule

module fault23_i16_sa0_a3(a,b,c,d,e,o22_f14,o23_f14);//fault free

 input a,b,c,d,e;

output o22_f14,o23_f14;

wire i10,i11,i16,i19,i16_sa0_a3;

nand a102(i10,a,c);

nand a202(i11,c,d);

//nand a302(i16_sa0_a3,b,i11);

nand a402(i19,i11,e);

nand a502(o22_f14,i10,i16);

nand a602(o23_f14,i16,i19);

and i16__sa0_a3(i16_sa0_a3,1'b0,i16);

assign i16=i16_sa0_a3;

endmodule

module fault24_i16_sa1_a3(a,b,c,d,e,o22_f15,o23_f15);//fault free

input a,b,c,d,e;

output o22_f15,o23_f15;

wire i10,i11,i16,i19,i16_sa1_a3;

nand a103(i10,a,c);

nand a203(i11,c,d);

//nand a303(i16_sa1_a3,b,i11);

nand a403(i19,i11,e);
 nand a503(o22_f15,i10,i16);

nand a603(o23_f15,i16,i19);

or i16__sa1_a3(i16_sa1_a3,1'b1,i16);

assign i16=i16_sa1_a3;

endmodule

module fault25_i19_sa0_a6(a,b,c,d,e,o22_f25,o23_f25);//fault free

input a,b,c,d,e;

output o22_f25,o23_f25;

wire i10,i11,i16,i19,i19_sa0_a6;

nand a104(i10,a,c);

nand a204(i11,c,d);

nand a304(i16,b,i11);

nand a404(i19,i11,e);

nand a504(o22_f25,i10,i16);

nand a604(o23_f25,i16,i19_sa0_a6);

and i19__sa0_a6(i19_sa0_a6,1'b0,i19);

endmodule

module fault26_i19_sa1_a6(a,b,c,d,e,o22_f26,o23_f26);//fault free

input a,b,c,d,e;
 output o22_f26,o23_f26;

wire i10,i11,i16,i19,i19_sa1_a6;

nand a105(i10,a,c);

nand a205(i11,c,d);

nand a305(i16,b,i11);

nand a405(i19,i11,e);

nand a505(o22_f26,i10,i16);

nand a605(o23_f26,i16,i19_sa1_a6);

or i19__sa1_a6(i19_sa1_a6,1'b1,i19);

endmodule

module fault27_i11_sa0(a,b,c,d,e,o22_f27,o23_f27);//fault free

input a,b,c,d,e;

output o22_f27,o23_f27;

wire i10,i11,i16,i19,i11_sa0;

nand a106(i10,a,c);

nand a206(i11,c,d);

nand a306(i16,b,i11_sa0);

nand a406(i19,i11_sa0,e);

nand a506(o22_f27,i10,i16);

nand a606(o23_f27,i16,i19);

and i11__sa0(i11_sa0,i11,1'b0);
endmodule

module fault28_i11_sa1(a,b,c,d,e,o22_f28,o23_f28);//fault free

input a,b,c,d,e;

output o22_f28,o23_f28;

wire i10,i11,i16,i19,i11_sa1;

nand a17(i10,a,c);

nand a27(i11,c,d);

nand a37(i16,b,i11_sa1);

nand a47(i19,i11_sa1,e);

nand a57(o22_f28,i10,i16);

nand a67(o23_f28,i16,i19);

or i11__sa1(i11_sa1,i11,1'b1);

endmodule

module fault29_c_sa0(a,b,c,d,e,o22_f29,o23_f29);//fault free

input a,b,c,d,e;

output o22_f29,o23_f29;

wire i10,i11,i16,i19,c_sa0;

nand a18(i10,a,c_sa0);

nand a28(i11,c_sa0,d);
 nand a38(i16,b,i11);

nand a48(i19,i11,e);

nand a58(o22_f29,i10,i16);

nand a68(o23_f29,i16,i19);

and c__sa0(c_sa0,1'b0,c);

endmodule

module fault30_c_sa1(a,b,c,d,e,o22_f30,o23_f30);//fault free

input a,b,c,d,e;

output o22_f30,o23_f30;

wire i10,i11,i16,i19,c_sa1;

nand a19(i10,a,c_sa1);

nand a29(i11,c_sa1,d);

nand a39(i16,b,i11);

nand a49(i19,i11,e);

nand a59(o22_f30,i10,i16);

nand a69(o23_f30,i16,i19);

or c__sa1(c_sa1,1'b1,c);

endmodule

module faut31_o22_sa0(a,b,c,d,e,o22_f19,o23_f19);//fault free

input a,b,c,d,e;

output o22_f19,o23_f19;

wire i10,i11,i16,i19,o22_sa0;

nand a25(i10,a,c);

nand a205(i11,c,d);

nand a305(i16,b,i11);

nand a405(i19,i11,e);

// nand a505(o22_f19,i10,i16);

nand a605(o23_f19,i16,i19);

and o22__sa0(o22_sa0,1'b0,o22_f19);

assign o22_f19=o22_sa0;

endmodule

module faut32_o22_sa1(a,b,c,d,e,o22_f20,o23_f20);//fault free

input a,b,c,d,e;

output o22_f20,o23_f20;

wire i10,i11,i16,i19,o22_sa1;

nand a2006(i10,a,c);

nand a2016(i11,c,d);

nand a2026(i16,b,i11);

nand a2036(i19,i11,e);
 //nand a2046(o22_f20,i10,i16);

nand a2056(o23_f20,i16,i19);

or o22___sa1(o22_sa1,1'b1,o22_f20);

assign o22_f20=o22_sa1;

endmodule

module fault33_o23_sa0(a,b,c,d,e,o22_f21,o23_f21);//fault free

input a,b,c,d,e;

output o22_f21,o23_f21;

wire i10,i11,i16,i19,o23_sa0;

nand a307(i10,a,c);

nand a317(i11,c,d);

nand a327(i16,b,i11);

nand a427(i19,i11,e);

nand a507(o22_f21,i10,i16);

//nand a607(o23_f21,i16,i19);

and o23__sa0(o23_sa0,1'b0,o23_f21);

assign o23_f21=o23_sa0;

endmodule

module fault34_o23_sa1(a,b,c,d,e,o22_f22,o23_f22);//fault free

input a,b,c,d,e;

output o22_f22,o23_f22;

wire i10,i11,i16,i19,o23_sa1;

nand a118(i10,a,c);

nand a218(i11,c,d);

nand a318(i16,b,i11);

nand a418(i19,i11,e);

nand a518(o22_f22,i10,i16);

// nand a618(o23_f22,i16,i19);

or o23__sa1(o23_sa1,1'b1,o23_f22);

assign o23_f22=o23_sa1;

endmodule

TASK-ONE 34 Faults
Test Bench:
module tb;
reg a,b,c,d,e;
integer i;
wire
o22,o23,o22_f1,o23_f1,o22_f2,o23_f2,o22_f3,o23_f3,o22_f4,o23_f4,o22_f5,
o23_f5,o22_f6,o23_f6,o22_f7,o23_f7,o22_f8,o23_f8,o22_f9,o23_f9,o22_f10,
o23_f10,o22_f11,o23_f11,o22_f12,o23_f12,o22_f13,o23_f13,o22_f14,o23_f1
4,o22_f15,o23_f15,o22_f16,o23_f16,o22_f17,o23_f17,o22_f18,o23_f18,o22_
f19,o23_f19,o22_f20,o23_f20,o22_f21,o23_f21,o22_f22,o23_f22,o22_f23,o2
3_f23,o22_f24,o23_f24,o22_f25,o23_f25,o22_f26,o23_f26,o22_f27,o23_f27,
o22_f28,o23_f28,o22_f29,o23_f29,o22_f30,o23_f30,o22_f31,o23_f31,o22_f3
2,o23_f32,o22_f33,o23_f33,o22_f34,o23_f34;
//y1,y2,y011,y012,y111,y112,y121,y122,y021,y022,y031,y032,y131,y132;

expt_two_task1 f0(a,b,c,d,e,o22,o23);
fault1_in_A_SA0 f1(a,b,c,d,e,o22_f1,o23_f1);
fault2_in_A_SA1 f2(a,b,c,d,e,o22_f2,o23_f2);
fault3_in_B_SA0 f3(a,b,c,d,e,o22_f3,o23_f3);
fault4_in_B_SA1 f4(a,b,c,d,e,o22_f4,o23_f4);
fault5_in_C_SA0_a2 f5(a,b,c,d,e,o22_f5,o23_f5);
fault6_in_C_SA1_a2 f6(a,b,c,d,e,o22_f6,o23_f6);
fault7_in_C_SA0_a1 f7(a,b,c,d,e,o22_f7,o23_f7);
fault8_in_C_SA1_a1 f8(a,b,c,d,e,o22_f8,o23_f8);
fault9_dsa0_a2 f9(a,b,c,d,e,o22_f9,o23_f9);
fault10_dsa1_a2 f10(a,b,c,d,e,o22_f10,o23_f10);
fault11_esa0_a4 f11(a,b,c,d,e,o22_f11,o23_f11);
fault12_esa1_a4 f12(a,b,c,d,e,o22_f12,o23_f12);
fault13_i11_sa0_a4 f13(a,b,c,d,e,o22_f13,o23_f13);
fault14_i11_sa1_a4 f14(a,b,c,d,e,o22_f14,o23_f14);
fault15_i11_sa0_a3 f15(a,b,c,d,e,o22_f15,o23_f15);
fault16_i11_sa1_a3 f16(a,b,c,d,e,o22_f16,o23_f16);
fault17_i10_sa0_a5 f17(a,b,c,d,e,o22_f17,o23_f17);
fault18_i10_sa1_a5 f18(a,b,c,d,e,o22_f18,o23_f18);
fault19_i16_sa0_a5 f19(a,b,c,d,e,o22_f19,o23_f19);
fault20_i16_sa1_a5 f20(a,b,c,d,e,o22_f20,o23_f20);
fault21_i16_sa0_a6 f21(a,b,c,d,e,o22_f21,o23_f21);
fault22_i16_sa1_a6 f22(a,b,c,d,e,o22_f22,o23_f22);
fault23_i16_sa0_a3 f23(a,b,c,d,e,o22_f23,o23_f23);
fault24_i16_sa1_a3 f24(a,b,c,d,e,o22_f24,o23_f24);
fault25_i19_sa0_a6 f25(a,b,c,d,e,o22_f25,o23_f25);
fault26_i19_sa1_a6 f26(a,b,c,d,e,o22_f26,o23_f26);
fault27_i11_sa0 f27(a,b,c,d,e,o22_f27,o23_f27);
fault28_i11_sa1 f28(a,b,c,d,e,o22_f28,o23_f28);
fault29_c_sa0 f29(a,b,c,d,e,o22_f29,o23_f29);
fault30_c_sa1 f30(a,b,c,d,e,o22_f30,o23_f30);
faut31_o22_sa0 f31(a,b,c,d,e,o22_f31,o23_f31);
faut32_o22_sa1 f32(a,b,c,d,e,o22_f32,o23_f32);
fault33_o23_sa0 f33(a,b,c,d,e,o22_f33,o23_f33);
fault34_o23_sa1 f34(a,b,c,d,e,o22_f34,o23_f34);
initial
begin
$display(" \n\-----s_a_1 at node 7-----\n ");
$display(" Test patterns Fault free Response Fault Responses");

#10 a=0;b=0;c=0;d=0;e=0;

for (i=0;i<32;i=i+1)
begin
$monitor($time, " abcde=%b%b%b%b%b \t o22o23=%b%b \t
o22_f1o23_f1=%b%b",a,b,c,d,e,o22,o23,o22_f1,o23_f1);
#5 {a,b,c,d,e}={a,b,c,d,e}+1;

if(o22_f1!=o22)
$display("Input A, SA-0 for A1-NAND fault-1 is detected");
if(o23_f1!=o23)
$display("Input A, SA-0 for A1-NAND fault-1 is detected");

if(o22_f2!=o22)
$display("Input A, SA-1 for A1-NAND fault-2 is detected");
if(o23_f2!=o23)
$display("Input A, SA-1 for A1-NAND fault-2 is detected");

if(o22_f3!=o22)
$display("Input B, SA-0 for A3-NAND fault-3 is detected");
if(o23_f3!=o23)
$display("Input A, SA-0 for A3-NAND fault-3 is detected");
if(o22_f4!=o22)
$display("Input B, SA-1 for A3-NAND fault-4 is detected");
if(o23_f4!=o23)
$display("Input B, SA-1 for A3-NAND fault-4 is detected");

if(o22_f5!=o22)
$display("Input C, SA-0 for A2-NAND fault-5 is detected");
if(o23_f5!=o23)
$display("Input C, SA-0 for A2-NAND fault-5 is detected");

if(o22_f6!=o22)
$display("Input C, SA-1 for A2-NAND fault-6 is detected");
if(o23_f6!=o23)
$display("Input C, SA-1 for A2-NAND fault-6 is detected");
 if(o22_f7!=o22)
$display("Input C, SA-0 for A1-NAND fault-7 is detected");
if(o23_f7!=o23)
$display("Input C, SA-0 for A1-NAND fault-7 is detected");

if(o22_f8!=o22)
$display("Input C, SA-1 for A1-NAND fault-8 is detected");
if(o23_f8!=o23)
$display("Input C, SA-1 for A1-NAND fault-8 is detected");
if(o22_f9!=o22)
$display("Input D, SA-0 for A2-NAND fault-9 is detected");
if(o23_f9!=o23)
$display("Input D, SA-0 for A2-NAND fault-9 is detected");

if(o22_f10!=o22)
$display("Input D, SA-1 for A2-NAND fault-10 is detected");
if(o23_f10!=o23)
$display("Input D, SA-1 for A2-NAND fault-10 is detected");

if(o22_f11!=o22)
$display("Input E, SA-0 for A4-NAND fault-11 is detected");
if(o23_f11!=o23)
$display("Input E, SA-0 for A4-NAND fault-11 is detected");

if(o22_f12!=o22)
 $display("Input E, SA-1 for A4-NAND fault-12 is detected");
if(o23_f12!=o23)
$display("Input E, SA-1 for A4-NAND fault-12 is detected");

if(o22_f13!=o22)
$display("Input i11, SA-0 for A4-NAND fault-13 is detected");
if(o23_f13!=o23)
$display("Input i11, SA-0 for A4-NAND fault-13 is detected");

if(o22_f14!=o22)
$display("Input i11, SA-1 for A4-NAND fault-14 is detected");
if(o23_f14!=o23)
$display("Input i11, SA-1 for A4-NAND fault-14 is detected");

if(o22_f15!=o22)
$display("Input i11, SA-0 for A3-NAND fault-15 is detected");
if(o23_f15!=o23)
$display("Input i11, SA-0 for A3-NAND fault-15 is detected");

if(o22_f16!=o22)
$display("Input i11, SA-1 for A3-NAND fault-16 is detected");
if(o23_f16!=o23)
$display("Input i11, SA-1 for A3-NAND fault-16 is detected");

if(o22_f17!=o22)
$display("Input i10, SA-0 for A5-NAND fault-17 is detected");
if(o23_f17!=o23)
$display("Input i10, SA-0 for A5-NAND fault-17 is detected");

if(o22_f18!=o22)
$display("Input i10, SA-1 for A5-NAND fault-18 is detected");
if(o23_f18!=o23)
$display("Input i10, SA-1 for A5-NAND fault-18 is detected");

if(o22_f19!=o22)
$display("Input i16, SA-0 for A5-NAND fault-19 is detected");
if(o23_f19!=o23)
$display("Input i16, SA-0 for A5-NAND fault-19 is detected");
if(o22_f20!=o22)
$display("Input i16, SA-1 for A5-NAND fault-20 is detected");
if(o23_f20!=o23)
$display("Input i16, SA-1 for A5-NAND fault-20 is detected");

if(o22_f21!=o22)
$display("Input i16, SA-0 for A6-NAND fault-21 is detected");
if(o23_f21!=o23)
$display("Input i16, SA-0 for A6-NAND fault-21 is detected");

if(o22_f22!=o22)
$display("Input i16, SA-1 for A6-NAND fault-22 is detected");
if(o23_f22!=o23)
$display("Input i16, SA-1 for A6-NAND fault-22 is detected");
if(o22_f23!=o22)
$display("Input i16, SA-0 for A3-NAND fault-23 is detected");
if(o23_f23!=o23)
$display("Input i16, SA-0 for A3-NAND fault-23 is detected");

if(o22_f24!=o22)
$display("Input i16, SA-1 for A3-NAND fault-24 is detected");
if(o23_f24!=o23)
$display("Input i16, SA-1 for A3-NAND fault-24 is detected");

if(o22_f25!=o22)
$display("Input i19, SA-0 for A6-NAND fault-25 is detected");
if(o23_f25!=o23)
$display("Input i19, SA-0 for A6-NAND fault-25 is detected");

if(o22_f26!=o22)
$display("Input i19, SA-1 for A6-NAND fault-26 is detected");
if(o23_f26!=o23)
$display("Input i19, SA-1 for A6-NAND fault-26 is detected");

if(o22_f27!=o22)
$display("Input i11, SA-0 for A2-NAND fault-27 is detected");
if(o23_f27!=o23)
$display("Input i11, SA-0 for A2-NAND fault-27 is detected");
 if(o22_f28!=o22)
$display("Input i11, SA-1 for A2-NAND fault-28 is detected");
if(o23_f28!=o23)
$display("Input i11, SA-1 for A2-NAND fault-28 is detected");

if(o22_f29!=o22)
$display("Input c, SA-0 for fault-29 is detected");
if(o23_f29!=o23)
$display("Input c, SA-0 for fault-29 is detected");

if(o22_f30!=o22)
$display("Input c, SA-0 for fault-30 is detected");
if(o23_f30!=o23)
$display("Input c, SA-0 for fault-30 is detected");

if(1'b0!=o22) //faut31_o22_sa0
$display("Output o22, SA-0 for a5 fault-31 is detected");
if(o23_f31!=o23)
$display("Output o22, SA-0 for a5 fault-31 is detected");

if(1'b1!=o22) //faut32 o22_sa1

$display("Output o22, SA-1 for a5 fault-32 is detected");
if(o23_f32!=o23)
$display("Output o22, SA-1 for a5 fault-32 is detected");
 if(o22_f33!=o22) //faut33_o22_sa0
$display("Output o23, SA-0 for a6 fault-33 is detected");
if(1'b0!=o23)
$display("Output o23, SA-0 for a6 fault-33 is detected");

if(o22_f34!=o22) //faut32_o22_sa0
$display("Output o23, SA-1 for a6 fault-34 is detected");
if(1'b1!=o23)
$display("Output o23, SA-1 for a6 fault-34 is detected");
end
end
endmodule
TASK-Two 22 Faults
Verilog Code
module expt_two_task_two(a,b,c,d,e,o22,o23);//fault free
input a,b,c,d,e;
output o22,o23;
wire i10,i11,i16,i19;
nand a1(i10,a,c);
nand a2(i11,c,d);
nand a3(i16,b,i11);
nand a4(i19,i11,e);
nand a5(o22,i10,i16);
nand a6(o23,i16,i19);
endmodule
module fault1_in_A_SA1(a,b,c,d,e,o22_f1,o23_f1);
input a,b,c,d,e;
output o22_f1,o23_f1;
wire i10,i11,i16,i19,in_a_sa1;
nand a1(i10,in_a_sa1,c);
nand a2(i11,c,d);
nand a3(i16,b,i11);
nand a4(i19,i11,e);
nand a5(o22_f1,i10,i16);
nand a6(o23_f1,i16,i19);
or fault2_A_SA1(in_a_sa1,a,1'b1);
endmodule
module fault2_in_C_SA1_a1(a,b,c,d,e,o22_f2,o23_f2);
input a,b,c,d,e;
output o22_f2,o23_f2;
wire i10,i11,i16,i19,in_c_sa1_a1;
nand a1(i10,a,in_c_sa1_a1);
nand a2(i11,c,d);
nand a3(i16,b,i11);
nand a4(i19,i11,e);
nand a5(o22_f2,i10,i16);
nand a6(o23_f2,i16,i19);
or csa1__a1(in_c_sa1_a1,1'b1,c);
endmodule

module fault3_c_sa0(a,b,c,d,e,o22_f3,o23_f3);
 input a,b,c,d,e;
output o22_f3,o23_f3;
wire i10,i11,i16,i19,c_sa0;
nand a18(i10,a,c_sa0);
nand a28(i11,c_sa0,d);
nand a38(i16,b,i11);
nand a48(i19,i11,e);
nand a58(o22_f3,i10,i16);
nand a68(o23_f3,i16,i19);
and c__sa0(c_sa0,1'b0,c);
endmodule

module fault4_c_sa1(a,b,c,d,e,o22_f4,o23_f4);//fault free

input a,b,c,d,e;
output o22_f4,o23_f4;
wire i10,i11,i16,i19,c_sa1;
nand a19(i10,a,c_sa1);
nand a29(i11,c_sa1,d);
nand a39(i16,b,i11);
nand a49(i19,i11,e);
nand a59(o22_f4,i10,i16);
nand a69(o23_f4,i16,i19);
or c__sa1(c_sa1,1'b1,c);
endmodule

module fault5_in_C_SA1_a2(a,b,c,d,e,o22_f5,o23_f5);//fault free

input a,b,c,d,e;
output o22_f5,o23_f5;
wire i10,i11,i16,i19,in_c_sa1_a2;
nand a1(i10,a,c);
nand a2(i11,in_c_sa1_a2,d);
nand a3(i16,b,i11);
nand a4(i19,i11,e);
nand a5(o22_f5,i10,i16);
nand a6(o23_f5,i16,i19);
or csa1(in_c_sa1_a2,c,1'b1);
endmodule

module fault6_dsa1_a2(a,b,c,d,e,o22_f6,o23_f6);//fault free

input a,b,c,d,e;
output o22_f6,o23_f6;
wire i10,i11,i16,i19,dsa1_a2;
nand a1_1(i10,a,c);
nand a2_1(i11,c,dsa1_a2);
nand a3_1(i16,b,i11);
nand a4_1(i19,i11,e);
nand a5_1(o22_f6,i10,i16);
nand a6_1(o23_f6,i16,i19);
or dsa1___a2(dsa1_a2,1'b1,d);
endmodule

module fault7_esa1_a4(a,b,c,d,e,o22_f7,o23_f7);//fault free

input a,b,c,d,e;
output o22_f7,o23_f7;
wire i10,i11,i16,i19,esa1_a4;
nand a1(i10,a,c);
nand a2(i11,c,d);
nand a3(i16,b,i11);
nand a4(i19,i11,esa1_a4);
nand a5(o22_f7,i10,i16);
nand a6(o23_f7,i16,i19);
or esa1__a4(esa1_a4,1'b1,d);
endmodule

module fault8_i10_sa1_a5(a,b,c,d,e,o22_f8,o23_f8);//fault free

input a,b,c,d,e;
output o22_f8,o23_f8;
wire i10,i11,i16,i19,i10_sa1_a5;
nand a177(i10,a,c);
nand a277(i11,c,d);
nand a377(i16,b,i11);
nand a477(i19,i11,e);
nand a577(o22_f8,i10_sa1_a5,i16);
nand a677(o23_f8,i16,i19);
or i10__sa1_a5(i10_sa1_a5,1'b1,i10);
endmodule

module fault9_in_B_SA1(a,b,c,d,e,o22_f9,o23_f9);//fault free

 input a,b,c,d,e;
output o22_f9,o23_f9;
wire i10,i11,i16,i19,in_b_sa1;
nand a1(i10,a,c);
nand a2(i11,c,d);
nand a3(i16,in_b_sa1,i11);
nand a4(i19,i11,e);
nand a5(o22_f9,i10,i16);
nand a6(o23_f9,i16,i19);
or b__sa1(in_b_sa1,1'b1,b);
endmodule

module fault10_i11_sa1_a3(a,b,c,d,e,o22_f10,o23_f10);//fault free

input a,b,c,d,e;
output o22_f10,o23_f10;
wire i10,i11,i16,i19,i11_sa1_a3;
nand a155(i10,a,c);
nand a255(i11,c,d);
nand a355(i16,b,i11_sa1_a3);
nand a455(i19,i11,e);
nand a555(o22_f10,i10,i16);
nand a655(o23_f10,i16,i19);
or i11__sa1_a3(i11_sa1_a3,1'b1,i11);
endmodule

module fault11_i11_sa0(a,b,c,d,e,o22_f11,o23_f11);//fault free

 input a,b,c,d,e;
output o22_f11,o23_f11;
wire i10,i11,i16,i19,i11_sa0;
nand a106(i10,a,c);
nand a206(i11,c,d);
nand a306(i16,b,i11_sa0);
nand a406(i19,i11_sa0,e);
nand a506(o22_f11,i10,i16);
nand a606(o23_f11,i16,i19);
and i11__sa0(i11_sa0,i11,1'b0);
endmodule

module fault12_i11_sa1(a,b,c,d,e,o22_f12,o23_f12);//fault free

input a,b,c,d,e;
output o22_f12,o23_f12;
wire i10,i11,i16,i19,i11_sa1;
nand a17(i10,a,c);
nand a27(i11,c,d);
nand a37(i16,b,i11_sa1);
nand a47(i19,i11_sa1,e);
nand a57(o22_f12,i10,i16);
nand a67(o23_f12,i16,i19);
or i11__sa1(i11_sa1,i11,1'b1);
endmodule

module fault13_i11_sa1_a4(a,b,c,d,e,o22_f13,o23_f13);//fault free

 input a,b,c,d,e;
output o22_f13,o23_f13;
wire i10,i11,i16,i19,i11_sa1_a4;
nand a133(i10,a,c);
nand a233(i11,c,d);
nand a333(i16,b,i11);
nand a433(i19,i11_sa1_a4,e);
nand a533(o22_f13,i10,i16);
nand a633(o23_f13,i16,i19);
or i11__sa1_a4(i11_sa1_a4,1'b1,i11);
endmodule

module fault14_i16_sa0_a3(a,b,c,d,e,o22_f14,o23_f14);//fault free

input a,b,c,d,e;
output o22_f14,o23_f14;
wire i10,i11,i16,i19,i16_sa0_a3;
nand a102(i10,a,c);
nand a202(i11,c,d);
//nand a302(i16_sa0_a3,b,i11);
nand a402(i19,i11,e);
nand a502(o22_f14,i10,i16);
nand a602(o23_f14,i16,i19);
and i16__sa0_a3(i16_sa0_a3,1'b0,i16);
assign i16=i16_sa0_a3;
endmodule
module fault15_i16_sa1_a3(a,b,c,d,e,o22_f15,o23_f15);//fault free
input a,b,c,d,e;
output o22_f15,o23_f15;
wire i10,i11,i16,i19,i16_sa1_a3;
nand a103(i10,a,c);
nand a203(i11,c,d);
//nand a303(i16_sa1_a3,b,i11);
nand a403(i19,i11,e);
nand a503(o22_f15,i10,i16);
nand a603(o23_f15,i16,i19);
or i16__sa1_a3(i16_sa1_a3,1'b1,i16);
assign i16=i16_sa1_a3;
endmodule

module fault16_i16_sa1_a5(a,b,c,d,e,o22_f16,o23_f16);//fault free

input a,b,c,d,e;
output o22_f16,o23_f16;
wire i10,i11,i16,i19,i16_sa1_a5;
nand a199(i10,a,c);
nand a299(i11,c,d);
nand a399(i16,b,i11);
nand a499(i19,i11,e);
nand a599(o22_f16,i10,i16_sa1_a5);
nand a699(o23_f16,i16,i19);
or i16__sa1_a5(i16_sa1_a5,1'b1,i16);
endmodule
module fault17_i16_sa1_a6(a,b,c,d,e,o22_f17,o23_f17); //fault free
input a,b,c,d,e;
output o22_f17,o23_f17;
wire i10,i11,i16,i19,i16_sa1_a6;
nand a101(i10,a,c);
nand a201(i11,c,d);
nand a301(i16,b,i11);
nand a401(i19,i11,e);
nand a501(o22_f17,i10,i16);
nand a601(o23_f17,i16_sa1_a6,i19);
or i16__sa1_a6(i16_sa1_a6,1'b1,i16);
endmodule

module fault18_i19_sa1_a6(a,b,c,d,e,o22_f18,o23_f18);//fault free

input a,b,c,d,e;
output o22_f18,o23_f18;
wire i10,i11,i16,i19,i19_sa1_a6;
nand a105(i10,a,c);
nand a205(i11,c,d);
nand a305(i16,b,i11);
nand a405(i19,i11,e);
nand a505(o22_f18,i10,i16);
nand a605(o23_f18,i16,i19_sa1_a6);
or i19__sa1_a6(i19_sa1_a6,1'b1,i19);
endmodule
module faut19_o22_sa0(a,b,c,d,e,o22_f19,o23_f19);//fault free
input a,b,c,d,e;
output o22_f19,o23_f19;
wire i10,i11,i16,i19,o22_sa0;
nand a25(i10,a,c);
nand a205(i11,c,d);
nand a305(i16,b,i11);
nand a405(i19,i11,e);
// nand a505(o22_f19,i10,i16);
nand a605(o23_f19,i16,i19);
and o22__sa0(o22_sa0,1'b0,o22_f19);
assign o22_f19=o22_sa0;
endmodule

module faut20_o22_sa1(a,b,c,d,e,o22_f20,o23_f20);//fault free

input a,b,c,d,e;
output o22_f20,o23_f20;
wire i10,i11,i16,i19,o22_sa1;
nand a2006(i10,a,c);
nand a2016(i11,c,d);
nand a2026(i16,b,i11);
nand a2036(i19,i11,e);
//nand a2046(o22_f20,i10,i16);
nand a2056(o23_f20,i16,i19);
or o22___sa1(o22_sa1,1'b1,o22_f20);
 assign o22_f20=o22_sa1;
endmodule

module fault21_o23_sa0(a,b,c,d,e,o22_f21,o23_f21);//fault free

input a,b,c,d,e;
output o22_f21,o23_f21;
wire i10,i11,i16,i19,o23_sa0;
nand a307(i10,a,c);
nand a317(i11,c,d);
nand a327(i16,b,i11);
nand a427(i19,i11,e);
nand a507(o22_f21,i10,i16);
//nand a607(o23_f21,i16,i19);
and o23__sa0(o23_sa0,1'b0,o23_f21);
assign o23_f21=o23_sa0;
endmodule

module fault22_o23_sa1(a,b,c,d,e,o22_f22,o23_f22);//fault free

input a,b,c,d,e;
output o22_f22,o23_f22;
wire i10,i11,i16,i19,o23_sa1;
nand a118(i10,a,c);
nand a218(i11,c,d);
nand a318(i16,b,i11);
nand a418(i19,i11,e);
nand a518(o22_f22,i10,i16);
 // nand a618(o23_f22,i16,i19);
or o23__sa1(o23_sa1,1'b1,o23_f22);
assign o23_f22=o23_sa1;
endmodule

TASK-TWO 22 Faults
Test Bench
module tb;
reg a,b,c,d,e;
integer i;
wire
o22,o23,o22_f1,o23_f1,o22_f2,o23_f2,o22_f3,o23_f3,o22_f4,o23_f4,o22_f5,o
23_f5,o22_f6,o23_f6,o22_f7,o23_f7,o22_f8,o23_f8,o22_f9,o23_f9,o22_f10,o2
3_f10,o22_f11,o23_f11,o22_f12,o23_f12,o22_f13,o23_f13,o22_f14,o23_f14,o
22_f15,o23_f15,o22_f16,o23_f16,o22_f17,o23_f17,o22_f18,o23_f18,o22_f19,
o23_f19,o22_f20,o23_f20,o22_f21,o23_f21,o22_f22,o23_f22;

expt_two_task_two uut(a,b,c,d,e,o22,o23);
fault1_in_A_SA1 uut1(a,b,c,d,e,o22_f1,o23_f1);
fault2_in_C_SA1_a1 uut2(a,b,c,d,e,o22_f2,o23_f2);
fault3_c_sa0 uut3(a,b,c,d,e,o22_f3,o23_f3);
fault4_c_sa1 uut4(a,b,c,d,e,o22_f4,o23_f4);
fault5_in_C_SA1_a2 uut5(a,b,c,d,e,o22_f5,o23_f5);
fault6_dsa1_a2 uut6(a,b,c,d,e,o22_f6,o23_f6);
fault7_esa1_a4 uut7(a,b,c,d,e,o22_f7,o23_f7);
fault8_i10_sa1_a5 uut8(a,b,c,d,e,o22_f8,o23_f8);
fault9_in_B_SA1 uut9(a,b,c,d,e,o22_f9,o23_f9);
fault10_i11_sa1_a3 uut10(a,b,c,d,e,o22_f10,o23_f10);
fault11_i11_sa0 uut11(a,b,c,d,e,o22_f11,o23_f11);
fault12_i11_sa1 uut12(a,b,c,d,e,o22_f12,o23_f12);
fault13_i11_sa1_a4 uut13(a,b,c,d,e,o22_f13,o23_f13);
fault14_i16_sa0_a3 uut14(a,b,c,d,e,o22_f14,o23_f14);
fault15_i16_sa1_a3 uut15(a,b,c,d,e,o22_f15,o23_f15);
fault16_i16_sa1_a5 uut16(a,b,c,d,e,o22_f16,o23_f16);
fault17_i16_sa1_a6 uut17(a,b,c,d,e,o22_f17,o23_f17);
fault18_i19_sa1_a6 uut18(a,b,c,d,e,o22_f18,o23_f18);
faut19_o22_sa0 uut19(a,b,c,d,e,o22_f19,o23_f19);
faut20_o22_sa1 uut20(a,b,c,d,e,o22_f20,o23_f20);
fault21_o23_sa0 uut21(a,b,c,d,e,o22_f21,o23_f21);
fault22_o23_sa1 uut22(a,b,c,d,e,o22_f22,o23_f22);
initial
begin
$display(" \n\-----s_a_1 at node 7-----\n ");
$display(" Test patterns Fault free Response Fault Responses");

#10 a=0;b=0;c=0;d=0;e=0;
for (i=0;i<32;i=i+1)
begin
$monitor($time, " abcde=%b%b%b%b%b \t o22o23=%b%b \t
o22_f1o23_f1=%b%b",a,b,c,d,e,o22,o23,o22_f1,o23_f1);
#5 {a,b,c,d,e}={a,b,c,d,e}+1;

if(o22_f1!=o22)
$display("f1 s_a_1 fault is detected");
if(o23_f1!=o23)
 $display("f1 s_a_1 fault is detected");

if(o22_f2!=o22)
$display("f1 s_a_2 fault is detected");
if(o23_f2!=o23)
$display("f1 s_a_2 fault is detected");

if(o22_f3!=o22)
$display("f1 s_a_3 fault is detected");
if(o23_f3!=o23)
$display("f1 s_a_3 fault is detected");

if(o22_f4!=o22)
$display("f1 s_a_4 fault is detected");
if(o23_f4!=o23)
$display("f1 s_a_4 fault is detected");

if(o22_f5!=o22)
$display("f1 s_a_5 fault is detected");
if(o23_f5!=o23)
$display("f1 s_a_5 fault is detected");

if(o22_f6!=o22)
$display("f1 s_a_6 fault is detected");
if(o23_f6!=o23)
$display("f1 s_a_6 fault is detected");
 if(o22_f7!=o22)
$display("f1 s_a_7 fault is detected");
if(o23_f7!=o23)
$display("f1 s_a_7 fault is detected");

if(o22_f8!=o22)
$display("f1 s_a_8 fault is detected");
if(o23_f8!=o23)
$display("f1 s_a_8 fault is detected");

if(o22_f9!=o22)
$display("f1 s_a_9 fault is detected");
if(o23_f9!=o23)
$display("f1 s_a_9 fault is detected");

if(o22_f10!=o22)
$display("f1 s_a_10 fault is detected");
if(o23_f10!=o23)
$display("f1 s_a_10 fault is detected");

if(o22_f11!=o22)
$display("f1 s_a_11 fault is detected");
if(o23_f11!=o23)
$display("f1 s_a_11 fault is detected");
if(o22_f12!=o22)
$display("f1 s_a_12 fault is detected");
if(o23_f12!=o23)
$display("f1 s_a_12 fault is detected");

if(o22_f13!=o22)
$display("f1 s_a_13 fault is detected");
if(o23_f13!=o23)
$display("f1 s_a_13 fault is detected");

if(o22_f14!=o22)
$display("f1 s_a_14 fault is detected");
if(o23_f14!=o23)
$display("f1 s_a_14 fault is detected");

if(o22_f15!=o22)
$display("f1 s_a_15 fault is detected");
if(o23_f15!=o23)
$display("f1 s_a_15 fault is detected");

if(o22_f16!=o22)
$display("f1 s_a_16 fault is detected");
if(o23_f16!=o23)
$display("f1 s_a_16 fault is detected");

if(o22_f17!=o22)
 $display("f1 s_a_17 fault is detected");
if(o23_f17!=o23)
$display("f1 s_a_17 fault is detected");

if(o22_f18!=o22)
$display("f1 s_a_18 fault is detected");
if(o23_f18!=o23)
$display("f1 s_a_18 fault is detected");

if(o22_f19!=o22)
$display("f1 s_a_19 fault is detected");
if(o23_f19!=o23)
$display("f1 s_a_19 fault is detected");

if(o22_f20!=o22)
$display("f1 s_a_20 fault is detected");
if(o23_f20!=o23)
$display("f1 s_a_20 fault is detected");

if(o22_f21!=o22)
$display("f1 s_a_21 fault is detected");
if(o23_f21!=o23)
$display("f1 s_a_21 fault is detected");

if(o22_f22!=o22)
$display("f1 s_a_22 fault is detected");
if(o23_f22!=o23)
$display("f1 s_a_22 fault is detected");
end
end
endmodule

Simulation Observations:
Console Output:TASK-1
Test patterns Fault free Response Fault Responses
# 10 abcde=00000 o22o23=00 o22_f1o23_f1=00
# Input B, SA-1 for A3-NAND fault-4 is detected
# Input B, SA-1 for A3-NAND fault-4 is detected
# Input E, SA-1 for A4-NAND fault-12 is detected
# Input i10, SA-0 for A5-NAND fault-17 is detected
# Input i16, SA-0 for A5-NAND fault-19 is detected
# Input i16, SA-0 for A6-NAND fault-21 is detected
# Input i19, SA-0 for A6-NAND fault-25 is detected
# Output o22, SA-1 for a5 fault-32 is detected
# Output o23, SA-1 for a6 fault-34 is detected
# 15 abcde=00001 o22o23=01 o22_f1o23_f1=01
# Input B, SA-1 for A3-NAND fault-4 is detected
# Input E, SA-0 for A4-NAND fault-11 is detected
# Input i11, SA-0 for A4-NAND fault-13 is detected
# Input i10, SA-0 for A5-NAND fault-17 is detected
# Input i16, SA-0 for A5-NAND fault-19 is detected
# Input i19, SA-1 for A6-NAND fault-26 is detected
# Input i11, SA-0 for A2-NAND fault-27 is detected
# Output o22, SA-1 for a5 fault-32 is detected
# Output o23, SA-0 for a6 fault-33 is detected
# 20 abcde=00010 o22o23=00 o22_f1o23_f1=00
# Input B, SA-1 for A3-NAND fault-4 is detected
# Input B, SA-1 for A3-NAND fault-4 is detected
# Input E, SA-1 for A4-NAND fault-12 is detected
# Input i10, SA-0 for A5-NAND fault-17 is detected
# Input i16, SA-0 for A5-NAND fault-19 is detected
# Input i16, SA-0 for A6-NAND fault-21 is detected
# Input i19, SA-0 for A6-NAND fault-25 is detected
# Output o22, SA-1 for a5 fault-32 is detected
# Output o23, SA-1 for a6 fault-34 is detected
# 25 abcde=00011 o22o23=01 o22_f1o23_f1=01
# Input B, SA-1 for A3-NAND fault-4 is detected
# Input C, SA-1 for A2-NAND fault-6 is detected
# Input E, SA-0 for A4-NAND fault-11 is detected
# Input i11, SA-0 for A4-NAND fault-13 is detected
# Input i10, SA-0 for A5-NAND fault-17 is detected
# Input i16, SA-0 for A5-NAND fault-19 is detected
# Input i19, SA-1 for A6-NAND fault-26 is detected
# Input i11, SA-0 for A2-NAND fault-27 is detected
# Input c, SA-0 for fault-30 is detected
# Output o22, SA-1 for a5 fault-32 is detected
# Output o23, SA-0 for a6 fault-33 is detected
# 30 abcde=00100 o22o23=00 o22_f1o23_f1=00
# Input A, SA-1 for A1-NAND fault-2 is detected
# Input B, SA-1 for A3-NAND fault-4 is detected
# Input B, SA-1 for A3-NAND fault-4 is detected
# Input E, SA-1 for A4-NAND fault-12 is detected
# Input i10, SA-0 for A5-NAND fault-17 is detected
# Input i16, SA-0 for A5-NAND fault-19 is detected
# Input i16, SA-0 for A6-NAND fault-21 is detected
# Input i19, SA-0 for A6-NAND fault-25 is detected
# Output o22, SA-1 for a5 fault-32 is detected
# Output o23, SA-1 for a6 fault-34 is detected
# 35 abcde=00101 o22o23=01 o22_f1o23_f1=01
# Input A, SA-1 for A1-NAND fault-2 is detected
# Input B, SA-1 for A3-NAND fault-4 is detected
# Input D, SA-1 for A2-NAND fault-10 is detected
# Input E, SA-0 for A4-NAND fault-11 is detected
# Input i11, SA-0 for A4-NAND fault-13 is detected
# Input i10, SA-0 for A5-NAND fault-17 is detected
# Input i16, SA-0 for A5-NAND fault-19 is detected
# Input i19, SA-1 for A6-NAND fault-26 is detected
# Input i11, SA-0 for A2-NAND fault-27 is detected
# Output o22, SA-1 for a5 fault-32 is detected
# Output o23, SA-0 for a6 fault-33 is detected
# 40 abcde=00110 o22o23=00 o22_f1o23_f1=00
# Input A, SA-1 for A1-NAND fault-2 is detected
# Input i10, SA-0 for A5-NAND fault-17 is detected
# Input i16, SA-0 for A5-NAND fault-19 is detected
# Input i16, SA-0 for A6-NAND fault-21 is detected
# Input i19, SA-0 for A6-NAND fault-25 is detected
# Output o22, SA-1 for a5 fault-32 is detected
# Output o23, SA-1 for a6 fault-34 is detected
# 45 abcde=00111 o22o23=00 o22_f1o23_f1=00
# Input A, SA-1 for A1-NAND fault-2 is detected
# Input C, SA-0 for A2-NAND fault-5 is detected
# Input D, SA-0 for A2-NAND fault-9 is detected
# Input i11, SA-1 for A4-NAND fault-14 is detected
# Input i10, SA-0 for A5-NAND fault-17 is detected
# Input i16, SA-0 for A5-NAND fault-19 is detected
# Input i16, SA-0 for A6-NAND fault-21 is detected
# Input i19, SA-0 for A6-NAND fault-25 is detected
# Input i11, SA-1 for A2-NAND fault-28 is detected
# Input c, SA-0 for fault-29 is detected
# Output o22, SA-1 for a5 fault-32 is detected
# Output o23, SA-1 for a6 fault-34 is detected
# 50 abcde=01000 o22o23=11 o22_f1o23_f1=11
# Input B, SA-0 for A3-NAND fault-3 is detected
# Input A, SA-0 for A3-NAND fault-3 is detected
# Input i11, SA-0 for A3-NAND fault-15 is detected
# Input i11, SA-0 for A3-NAND fault-15 is detected
# Input i16, SA-1 for A5-NAND fault-20 is detected
# Input i16, SA-1 for A6-NAND fault-22 is detected
# Input i11, SA-0 for A2-NAND fault-27 is detected
# Input i11, SA-0 for A2-NAND fault-27 is detected
# Output o22, SA-0 for a5 fault-31 is detected
# Output o23, SA-0 for a6 fault-33 is detected
# 55 abcde=01001 o22o23=11 o22_f1o23_f1=11
# Input B, SA-0 for A3-NAND fault-3 is detected
# Input i11, SA-0 for A3-NAND fault-15 is detected
# Input i16, SA-1 for A5-NAND fault-20 is detected
# Input i11, SA-0 for A2-NAND fault-27 is detected
# Input i11, SA-0 for A2-NAND fault-27 is detected
# Output o22, SA-0 for a5 fault-31 is detected
# Output o23, SA-0 for a6 fault-33 is detected
# 60 abcde=01010 o22o23=11 o22_f1o23_f1=11
# Input B, SA-0 for A3-NAND fault-3 is detected
# Input A, SA-0 for A3-NAND fault-3 is detected
# Input C, SA-1 for A2-NAND fault-6 is detected
# Input C, SA-1 for A2-NAND fault-6 is detected
# Input i11, SA-0 for A3-NAND fault-15 is detected
# Input i11, SA-0 for A3-NAND fault-15 is detected
# Input i16, SA-1 for A5-NAND fault-20 is detected
# Input i16, SA-1 for A6-NAND fault-22 is detected
# Input i11, SA-0 for A2-NAND fault-27 is detected
# Input i11, SA-0 for A2-NAND fault-27 is detected
# Input c, SA-0 for fault-30 is detected
# Input c, SA-0 for fault-30 is detected
# Output o22, SA-0 for a5 fault-31 is detected
# Output o23, SA-0 for a6 fault-33 is detected
# 65 abcde=01011 o22o23=11 o22_f1o23_f1=11
# Input B, SA-0 for A3-NAND fault-3 is detected
# Input C, SA-1 for A2-NAND fault-6 is detected
# Input C, SA-1 for A2-NAND fault-6 is detected
# Input i11, SA-0 for A3-NAND fault-15 is detected
# Input i16, SA-1 for A5-NAND fault-20 is detected
# Input i11, SA-0 for A2-NAND fault-27 is detected
# Input i11, SA-0 for A2-NAND fault-27 is detected
# Input c, SA-0 for fault-30 is detected
# Input c, SA-0 for fault-30 is detected
# Output o22, SA-0 for a5 fault-31 is detected
# Output o23, SA-0 for a6 fault-33 is detected
# 70 abcde=01100 o22o23=11 o22_f1o23_f1=11
# Input B, SA-0 for A3-NAND fault-3 is detected
# Input A, SA-0 for A3-NAND fault-3 is detected
# Input D, SA-1 for A2-NAND fault-10 is detected
# Input D, SA-1 for A2-NAND fault-10 is detected
# Input i11, SA-0 for A3-NAND fault-15 is detected
# Input i11, SA-0 for A3-NAND fault-15 is detected
# Input i16, SA-1 for A5-NAND fault-20 is detected
# Input i16, SA-1 for A6-NAND fault-22 is detected
# Input i11, SA-0 for A2-NAND fault-27 is detected
# Input i11, SA-0 for A2-NAND fault-27 is detected
# Output o22, SA-0 for a5 fault-31 is detected
# Output o23, SA-0 for a6 fault-33 is detected
# 75 abcde=01101 o22o23=11 o22_f1o23_f1=11
# Input B, SA-0 for A3-NAND fault-3 is detected
# Input D, SA-1 for A2-NAND fault-10 is detected
# Input D, SA-1 for A2-NAND fault-10 is detected
# Input i11, SA-0 for A3-NAND fault-15 is detected
# Input i16, SA-1 for A5-NAND fault-20 is detected
# Input i11, SA-0 for A2-NAND fault-27 is detected
# Input i11, SA-0 for A2-NAND fault-27 is detected
# Output o22, SA-0 for a5 fault-31 is detected
# Output o23, SA-0 for a6 fault-33 is detected
# 80 abcde=01110 o22o23=00 o22_f1o23_f1=00
# Input A, SA-1 for A1-NAND fault-2 is detected
# Input C, SA-0 for A2-NAND fault-5 is detected
# Input C, SA-0 for A2-NAND fault-5 is detected
# Input D, SA-0 for A2-NAND fault-9 is detected
# Input D, SA-0 for A2-NAND fault-9 is detected
# Input i11, SA-1 for A3-NAND fault-16 is detected
# Input i11, SA-1 for A3-NAND fault-16 is detected
# Input i10, SA-0 for A5-NAND fault-17 is detected
# Input i16, SA-0 for A5-NAND fault-19 is detected
# Input i16, SA-0 for A6-NAND fault-21 is detected
# Input i19, SA-0 for A6-NAND fault-25 is detected
# Input i11, SA-1 for A2-NAND fault-28 is detected
# Input i11, SA-1 for A2-NAND fault-28 is detected
# Input c, SA-0 for fault-29 is detected
# Input c, SA-0 for fault-29 is detected
# Output o22, SA-1 for a5 fault-32 is detected
# Output o23, SA-1 for a6 fault-34 is detected
# 85 abcde=01111 o22o23=00 o22_f1o23_f1=00
# Input A, SA-1 for A1-NAND fault-2 is detected
# Input C, SA-0 for A2-NAND fault-5 is detected
# Input C, SA-0 for A2-NAND fault-5 is detected
# Input D, SA-0 for A2-NAND fault-9 is detected
# Input D, SA-0 for A2-NAND fault-9 is detected
# Input i11, SA-1 for A4-NAND fault-14 is detected
# Input i11, SA-1 for A3-NAND fault-16 is detected
# Input i11, SA-1 for A3-NAND fault-16 is detected
# Input i10, SA-0 for A5-NAND fault-17 is detected
# Input i16, SA-0 for A5-NAND fault-19 is detected
# Input i16, SA-0 for A6-NAND fault-21 is detected
# Input i19, SA-0 for A6-NAND fault-25 is detected
# Input i11, SA-1 for A2-NAND fault-28 is detected
# Input i11, SA-1 for A2-NAND fault-28 is detected
# Input c, SA-0 for fault-29 is detected
# Input c, SA-0 for fault-29 is detected
# Output o22, SA-1 for a5 fault-32 is detected
# Output o23, SA-1 for a6 fault-34 is detected
# 90 abcde=10000 o22o23=00 o22_f1o23_f1=00
# Input B, SA-1 for A3-NAND fault-4 is detected
# Input B, SA-1 for A3-NAND fault-4 is detected
# Input C, SA-1 for A1-NAND fault-8 is detected
# Input E, SA-1 for A4-NAND fault-12 is detected
# Input i10, SA-0 for A5-NAND fault-17 is detected
# Input i16, SA-0 for A5-NAND fault-19 is detected
# Input i16, SA-0 for A6-NAND fault-21 is detected
# Input i19, SA-0 for A6-NAND fault-25 is detected
# Input c, SA-0 for fault-30 is detected
# Output o22, SA-1 for a5 fault-32 is detected
# Output o23, SA-1 for a6 fault-34 is detected
# 95 abcde=10001 o22o23=01 o22_f1o23_f1=01
# Input B, SA-1 for A3-NAND fault-4 is detected
# Input C, SA-1 for A1-NAND fault-8 is detected
# Input E, SA-0 for A4-NAND fault-11 is detected
# Input i11, SA-0 for A4-NAND fault-13 is detected
# Input i10, SA-0 for A5-NAND fault-17 is detected
# Input i16, SA-0 for A5-NAND fault-19 is detected
# Input i19, SA-1 for A6-NAND fault-26 is detected
# Input i11, SA-0 for A2-NAND fault-27 is detected
# Input c, SA-0 for fault-30 is detected
# Output o22, SA-1 for a5 fault-32 is detected
# Output o23, SA-0 for a6 fault-33 is detected
run
# 100 abcde=10010 o22o23=00 o22_f1o23_f1=00
# Input B, SA-1 for A3-NAND fault-4 is detected
# Input B, SA-1 for A3-NAND fault-4 is detected
# Input C, SA-1 for A1-NAND fault-8 is detected
# Input E, SA-1 for A4-NAND fault-12 is detected
# Input i10, SA-0 for A5-NAND fault-17 is detected
# Input i16, SA-0 for A5-NAND fault-19 is detected
# Input i16, SA-0 for A6-NAND fault-21 is detected
# Input i19, SA-0 for A6-NAND fault-25 is detected
# Input c, SA-0 for fault-30 is detected
# Output o22, SA-1 for a5 fault-32 is detected
# Output o23, SA-1 for a6 fault-34 is detected
# 105 abcde=10011 o22o23=01 o22_f1o23_f1=01
# Input B, SA-1 for A3-NAND fault-4 is detected
# Input C, SA-1 for A2-NAND fault-6 is detected
# Input C, SA-1 for A1-NAND fault-8 is detected
# Input E, SA-0 for A4-NAND fault-11 is detected
# Input i11, SA-0 for A4-NAND fault-13 is detected
# Input i10, SA-0 for A5-NAND fault-17 is detected
# Input i16, SA-0 for A5-NAND fault-19 is detected
# Input i19, SA-1 for A6-NAND fault-26 is detected
# Input i11, SA-0 for A2-NAND fault-27 is detected
# Input c, SA-0 for fault-30 is detected
# Input c, SA-0 for fault-30 is detected
# Output o22, SA-1 for a5 fault-32 is detected
# Output o23, SA-0 for a6 fault-33 is detected
# 110 abcde=10100 o22o23=10 o22_f1o23_f1=00
# Input A, SA-0 for A1-NAND fault-1 is detected
# Input B, SA-1 for A3-NAND fault-4 is detected
# Input C, SA-0 for A1-NAND fault-7 is detected
# Input E, SA-1 for A4-NAND fault-12 is detected
# Input i10, SA-1 for A5-NAND fault-18 is detected
# Input i16, SA-0 for A6-NAND fault-21 is detected
# Input i19, SA-0 for A6-NAND fault-25 is detected
# Input c, SA-0 for fault-29 is detected
# Output o22, SA-0 for a5 fault-31 is detected
# Output o23, SA-1 for a6 fault-34 is detected
# 115 abcde=10101 o22o23=11 o22_f1o23_f1=01
# Input A, SA-0 for A1-NAND fault-1 is detected
# Input C, SA-0 for A1-NAND fault-7 is detected
# Input D, SA-1 for A2-NAND fault-10 is detected
# Input E, SA-0 for A4-NAND fault-11 is detected
# Input i11, SA-0 for A4-NAND fault-13 is detected
# Input i10, SA-1 for A5-NAND fault-18 is detected
# Input i19, SA-1 for A6-NAND fault-26 is detected
# Input i11, SA-0 for A2-NAND fault-27 is detected
# Input c, SA-0 for fault-29 is detected
# Output o22, SA-0 for a5 fault-31 is detected
# Output o23, SA-0 for a6 fault-33 is detected
# 120 abcde=10110 o22o23=10 o22_f1o23_f1=00
# Input A, SA-0 for A1-NAND fault-1 is detected
# Input C, SA-0 for A1-NAND fault-7 is detected
# Input i10, SA-1 for A5-NAND fault-18 is detected
# Input i16, SA-0 for A6-NAND fault-21 is detected
# Input i19, SA-0 for A6-NAND fault-25 is detected
# Input c, SA-0 for fault-29 is detected
# Output o22, SA-0 for a5 fault-31 is detected
# Output o23, SA-1 for a6 fault-34 is detected
# 125 abcde=10111 o22o23=10 o22_f1o23_f1=00
# Input A, SA-0 for A1-NAND fault-1 is detected
# Input C, SA-0 for A2-NAND fault-5 is detected
# Input C, SA-0 for A1-NAND fault-7 is detected
# Input D, SA-0 for A2-NAND fault-9 is detected
# Input i11, SA-1 for A4-NAND fault-14 is detected
# Input i10, SA-1 for A5-NAND fault-18 is detected
# Input i16, SA-0 for A6-NAND fault-21 is detected
# Input i19, SA-0 for A6-NAND fault-25 is detected
# Input i11, SA-1 for A2-NAND fault-28 is detected
# Input c, SA-0 for fault-29 is detected
# Input c, SA-0 for fault-29 is detected
# Output o22, SA-0 for a5 fault-31 is detected
# Output o23, SA-1 for a6 fault-34 is detected
# 130 abcde=11000 o22o23=11 o22_f1o23_f1=11
# Input B, SA-0 for A3-NAND fault-3 is detected
# Input A, SA-0 for A3-NAND fault-3 is detected
# Input i11, SA-0 for A3-NAND fault-15 is detected
# Input i11, SA-0 for A3-NAND fault-15 is detected
# Input i16, SA-1 for A5-NAND fault-20 is detected
# Input i16, SA-1 for A6-NAND fault-22 is detected
# Input i11, SA-0 for A2-NAND fault-27 is detected
# Input i11, SA-0 for A2-NAND fault-27 is detected
# Output o22, SA-0 for a5 fault-31 is detected
# Output o23, SA-0 for a6 fault-33 is detected
# 135 abcde=11001 o22o23=11 o22_f1o23_f1=11
# Input B, SA-0 for A3-NAND fault-3 is detected
# Input i11, SA-0 for A3-NAND fault-15 is detected
# Input i16, SA-1 for A5-NAND fault-20 is detected
# Input i11, SA-0 for A2-NAND fault-27 is detected
# Input i11, SA-0 for A2-NAND fault-27 is detected
# Output o22, SA-0 for a5 fault-31 is detected
# Output o23, SA-0 for a6 fault-33 is detected
# 140 abcde=11010 o22o23=11 o22_f1o23_f1=11
# Input B, SA-0 for A3-NAND fault-3 is detected
# Input A, SA-0 for A3-NAND fault-3 is detected
# Input C, SA-1 for A2-NAND fault-6 is detected
# Input C, SA-1 for A2-NAND fault-6 is detected
# Input i11, SA-0 for A3-NAND fault-15 is detected
# Input i11, SA-0 for A3-NAND fault-15 is detected
# Input i16, SA-1 for A5-NAND fault-20 is detected
# Input i16, SA-1 for A6-NAND fault-22 is detected
# Input i11, SA-0 for A2-NAND fault-27 is detected
# Input i11, SA-0 for A2-NAND fault-27 is detected
# Input c, SA-0 for fault-30 is detected
# Output o22, SA-0 for a5 fault-31 is detected
# Output o23, SA-0 for a6 fault-33 is detected
# 145 abcde=11011 o22o23=11 o22_f1o23_f1=11
# Input B, SA-0 for A3-NAND fault-3 is detected
# Input C, SA-1 for A2-NAND fault-6 is detected
# Input C, SA-1 for A2-NAND fault-6 is detected
# Input i11, SA-0 for A3-NAND fault-15 is detected
# Input i16, SA-1 for A5-NAND fault-20 is detected
# Input i11, SA-0 for A2-NAND fault-27 is detected
# Input i11, SA-0 for A2-NAND fault-27 is detected
# Input c, SA-0 for fault-30 is detected
# Output o22, SA-0 for a5 fault-31 is detected
# Output o23, SA-0 for a6 fault-33 is detected
# 150 abcde=11100 o22o23=11 o22_f1o23_f1=11
# Input A, SA-0 for A3-NAND fault-3 is detected
# Input D, SA-1 for A2-NAND fault-10 is detected
# Input i11, SA-0 for A3-NAND fault-15 is detected
# Input i16, SA-1 for A6-NAND fault-22 is detected
# Input i11, SA-0 for A2-NAND fault-27 is detected
# Output o22, SA-0 for a5 fault-31 is detected
# Output o23, SA-0 for a6 fault-33 is detected
# 155 abcde=11101 o22o23=11 o22_f1o23_f1=11
# Input D, SA-1 for A2-NAND fault-10 is detected
# Input i11, SA-0 for A2-NAND fault-27 is detected
# Output o22, SA-0 for a5 fault-31 is detected
# Output o23, SA-0 for a6 fault-33 is detected
# 160 abcde=11110 o22o23=10 o22_f1o23_f1=00
# Input A, SA-0 for A1-NAND fault-1 is detected
# Input C, SA-0 for A2-NAND fault-5 is detected
# Input C, SA-0 for A1-NAND fault-7 is detected
# Input D, SA-0 for A2-NAND fault-9 is detected
# Input i11, SA-1 for A3-NAND fault-16 is detected
# Input i10, SA-1 for A5-NAND fault-18 is detected
# Input i16, SA-0 for A6-NAND fault-21 is detected
# Input i19, SA-0 for A6-NAND fault-25 is detected
# Input i11, SA-1 for A2-NAND fault-28 is detected
# Input c, SA-0 for fault-29 is detected
# Output o22, SA-0 for a5 fault-31 is detected
# Output o23, SA-1 for a6 fault-34 is detected
# 165 abcde=11111 o22o23=10 o22_f1o23_f1=00
# Input A, SA-0 for A1-NAND fault-1 is detected
# Input C, SA-0 for A2-NAND fault-5 is detected
# Input C, SA-0 for A1-NAND fault-7 is detected
# Input D, SA-0 for A2-NAND fault-9 is detected
# Input i11, SA-1 for A4-NAND fault-14 is detected
# Input i11, SA-1 for A3-NAND fault-16 is detected
# Input i10, SA-1 for A5-NAND fault-18 is detected
# Input i16, SA-0 for A6-NAND fault-21 is detected
# Input i19, SA-0 for A6-NAND fault-25 is detected
# Input i11, SA-1 for A2-NAND fault-28 is detected
# Input c, SA-0 for fault-29 is detected
# Output o22, SA-0 for a5 fault-31 is detected
# Output o23, SA-1 for a6 fault-34 is detected
# 170 abcde=00000 o22o23=00 o22_f1o23_f1=00

Console Output:Task-2
Test patterns Fault free Response Fault Responses
# 10 abcde=00000 o22o23=00 o22_f1o23_f1=00
# f1 s_a_7 fault is detected
# f1 s_a_9 fault is detected
# f1 s_a_9 fault is detected
# f1 s_a_14 fault is detected
# f1 s_a_14 fault is detected
# f1 s_a_20 fault is detected
# f1 s_a_22 fault is detected
# 15 abcde=00001 o22o23=01 o22_f1o23_f1=01
# f1 s_a_9 fault is detected
# f1 s_a_11 fault is detected
# f1 s_a_14 fault is detected
# f1 s_a_18 fault is detected
# f1 s_a_20 fault is detected
# f1 s_a_21 fault is detected
# 20 abcde=00010 o22o23=00 o22_f1o23_f1=00
# f1 s_a_7 fault is detected
# f1 s_a_9 fault is detected
# f1 s_a_9 fault is detected
# f1 s_a_14 fault is detected
# f1 s_a_14 fault is detected
# f1 s_a_20 fault is detected
# f1 s_a_22 fault is detected
# 25 abcde=00011 o22o23=01 o22_f1o23_f1=01
# f1 s_a_4 fault is detected
# f1 s_a_5 fault is detected
# f1 s_a_9 fault is detected
# f1 s_a_11 fault is detected
# f1 s_a_14 fault is detected
# f1 s_a_18 fault is detected
# f1 s_a_20 fault is detected
# f1 s_a_21 fault is detected
# 30 abcde=00100 o22o23=00 o22_f1o23_f1=10
# f1 s_a_1 fault is detected
# f1 s_a_7 fault is detected
# f1 s_a_9 fault is detected
# f1 s_a_9 fault is detected
# f1 s_a_14 fault is detected
# f1 s_a_14 fault is detected
# f1 s_a_20 fault is detected
# f1 s_a_22 fault is detected
# 35 abcde=00101 o22o23=01 o22_f1o23_f1=11
# f1 s_a_1 fault is detected
# f1 s_a_6 fault is detected
# f1 s_a_9 fault is detected
# f1 s_a_11 fault is detected
# f1 s_a_14 fault is detected
# f1 s_a_18 fault is detected
# f1 s_a_20 fault is detected
# f1 s_a_21 fault is detected
# 40 abcde=00110 o22o23=00 o22_f1o23_f1=10
# f1 s_a_1 fault is detected
# f1 s_a_14 fault is detected
# f1 s_a_14 fault is detected
# f1 s_a_20 fault is detected
# f1 s_a_22 fault is detected
# 45 abcde=00111 o22o23=00 o22_f1o23_f1=10
# f1 s_a_1 fault is detected
# f1 s_a_3 fault is detected
# f1 s_a_12 fault is detected
# f1 s_a_13 fault is detected
# f1 s_a_14 fault is detected
# f1 s_a_14 fault is detected
# f1 s_a_20 fault is detected
# f1 s_a_22 fault is detected
# 50 abcde=01000 o22o23=11 o22_f1o23_f1=11
# f1 s_a_11 fault is detected
# f1 s_a_11 fault is detected
# f1 s_a_15 fault is detected
# f1 s_a_15 fault is detected
# f1 s_a_16 fault is detected
# f1 s_a_17 fault is detected
# f1 s_a_19 fault is detected
# f1 s_a_21 fault is detected
# 55 abcde=01001 o22o23=11 o22_f1o23_f1=11
# f1 s_a_11 fault is detected
# f1 s_a_11 fault is detected
# f1 s_a_15 fault is detected
# f1 s_a_16 fault is detected
# f1 s_a_19 fault is detected
# f1 s_a_21 fault is detected
# 60 abcde=01010 o22o23=11 o22_f1o23_f1=11
# f1 s_a_4 fault is detected
# f1 s_a_4 fault is detected
# f1 s_a_5 fault is detected
# f1 s_a_5 fault is detected
# f1 s_a_11 fault is detected
# f1 s_a_11 fault is detected
# f1 s_a_15 fault is detected
# f1 s_a_15 fault is detected
# f1 s_a_16 fault is detected
# f1 s_a_17 fault is detected
# f1 s_a_19 fault is detected
# f1 s_a_21 fault is detected
# 65 abcde=01011 o22o23=11 o22_f1o23_f1=11
# f1 s_a_4 fault is detected
# f1 s_a_4 fault is detected
# f1 s_a_5 fault is detected
# f1 s_a_5 fault is detected
# f1 s_a_11 fault is detected
# f1 s_a_11 fault is detected
# f1 s_a_15 fault is detected
# f1 s_a_16 fault is detected
# f1 s_a_19 fault is detected
# f1 s_a_21 fault is detected
# 70 abcde=01100 o22o23=11 o22_f1o23_f1=11
# f1 s_a_6 fault is detected
# f1 s_a_6 fault is detected
# f1 s_a_11 fault is detected
# f1 s_a_11 fault is detected
# f1 s_a_15 fault is detected
# f1 s_a_15 fault is detected
# f1 s_a_16 fault is detected
# f1 s_a_17 fault is detected
# f1 s_a_19 fault is detected
# f1 s_a_21 fault is detected
# 75 abcde=01101 o22o23=11 o22_f1o23_f1=11
# f1 s_a_6 fault is detected
# f1 s_a_6 fault is detected
# f1 s_a_11 fault is detected
# f1 s_a_11 fault is detected
# f1 s_a_15 fault is detected
# f1 s_a_16 fault is detected
# f1 s_a_19 fault is detected
# f1 s_a_21 fault is detected
# 80 abcde=01110 o22o23=00 o22_f1o23_f1=10
# f1 s_a_1 fault is detected
# f1 s_a_3 fault is detected
# f1 s_a_3 fault is detected
# f1 s_a_10 fault is detected
# f1 s_a_10 fault is detected
# f1 s_a_12 fault is detected
# f1 s_a_12 fault is detected
# f1 s_a_14 fault is detected
# f1 s_a_14 fault is detected
# f1 s_a_20 fault is detected
# f1 s_a_22 fault is detected
# 85 abcde=01111 o22o23=00 o22_f1o23_f1=10
# f1 s_a_1 fault is detected
# f1 s_a_3 fault is detected
# f1 s_a_3 fault is detected
# f1 s_a_10 fault is detected
# f1 s_a_10 fault is detected
# f1 s_a_12 fault is detected
# f1 s_a_12 fault is detected
# f1 s_a_13 fault is detected
# f1 s_a_14 fault is detected
# f1 s_a_14 fault is detected
# f1 s_a_20 fault is detected
# f1 s_a_22 fault is detected
# 90 abcde=10000 o22o23=00 o22_f1o23_f1=00
# f1 s_a_2 fault is detected
# f1 s_a_4 fault is detected
# f1 s_a_7 fault is detected
# f1 s_a_9 fault is detected
# f1 s_a_9 fault is detected
# f1 s_a_14 fault is detected
# f1 s_a_14 fault is detected
# f1 s_a_20 fault is detected
# f1 s_a_22 fault is detected
# 95 abcde=10001 o22o23=01 o22_f1o23_f1=01
# f1 s_a_2 fault is detected
# f1 s_a_4 fault is detected
# f1 s_a_9 fault is detected
# f1 s_a_11 fault is detected
# f1 s_a_14 fault is detected
# f1 s_a_18 fault is detected
# f1 s_a_20 fault is detected
# f1 s_a_21 fault is detected
run
# 100 abcde=10010 o22o23=00 o22_f1o23_f1=00
# f1 s_a_2 fault is detected
# f1 s_a_4 fault is detected
# f1 s_a_7 fault is detected
# f1 s_a_9 fault is detected
# f1 s_a_9 fault is detected
# f1 s_a_14 fault is detected
# f1 s_a_14 fault is detected
# f1 s_a_20 fault is detected
# f1 s_a_22 fault is detected
# 105 abcde=10011 o22o23=01 o22_f1o23_f1=01
# f1 s_a_2 fault is detected
# f1 s_a_4 fault is detected
# f1 s_a_4 fault is detected
# f1 s_a_5 fault is detected
# f1 s_a_9 fault is detected
# f1 s_a_11 fault is detected
# f1 s_a_14 fault is detected
# f1 s_a_18 fault is detected
# f1 s_a_20 fault is detected
# f1 s_a_21 fault is detected
# 110 abcde=10100 o22o23=10 o22_f1o23_f1=10
# f1 s_a_3 fault is detected
# f1 s_a_7 fault is detected
# f1 s_a_8 fault is detected
# f1 s_a_9 fault is detected
# f1 s_a_14 fault is detected
# f1 s_a_19 fault is detected
# f1 s_a_22 fault is detected
# 115 abcde=10101 o22o23=11 o22_f1o23_f1=11
# f1 s_a_3 fault is detected
# f1 s_a_6 fault is detected
# f1 s_a_8 fault is detected
# f1 s_a_11 fault is detected
# f1 s_a_18 fault is detected
# f1 s_a_19 fault is detected
# f1 s_a_21 fault is detected
# 120 abcde=10110 o22o23=10 o22_f1o23_f1=10
# f1 s_a_3 fault is detected
# f1 s_a_8 fault is detected
# f1 s_a_14 fault is detected
# f1 s_a_19 fault is detected
# f1 s_a_22 fault is detected
# 125 abcde=10111 o22o23=10 o22_f1o23_f1=10
# f1 s_a_3 fault is detected
# f1 s_a_3 fault is detected
# f1 s_a_8 fault is detected
# f1 s_a_12 fault is detected
# f1 s_a_13 fault is detected
# f1 s_a_14 fault is detected
# f1 s_a_19 fault is detected
# f1 s_a_22 fault is detected
# 130 abcde=11000 o22o23=11 o22_f1o23_f1=11
# f1 s_a_11 fault is detected
# f1 s_a_11 fault is detected
# f1 s_a_15 fault is detected
# f1 s_a_15 fault is detected
# f1 s_a_16 fault is detected
# f1 s_a_17 fault is detected
# f1 s_a_19 fault is detected
# f1 s_a_21 fault is detected
# 135 abcde=11001 o22o23=11 o22_f1o23_f1=11
# f1 s_a_11 fault is detected
# f1 s_a_11 fault is detected
# f1 s_a_15 fault is detected
# f1 s_a_16 fault is detected
# f1 s_a_19 fault is detected
# f1 s_a_21 fault is detected
# 140 abcde=11010 o22o23=11 o22_f1o23_f1=11
# f1 s_a_4 fault is detected
# f1 s_a_5 fault is detected
# f1 s_a_5 fault is detected
# f1 s_a_11 fault is detected
# f1 s_a_11 fault is detected
# f1 s_a_15 fault is detected
# f1 s_a_15 fault is detected
# f1 s_a_16 fault is detected
# f1 s_a_17 fault is detected
# f1 s_a_19 fault is detected
# f1 s_a_21 fault is detected
# 145 abcde=11011 o22o23=11 o22_f1o23_f1=11
# f1 s_a_4 fault is detected
# f1 s_a_5 fault is detected
# f1 s_a_5 fault is detected
# f1 s_a_11 fault is detected
# f1 s_a_11 fault is detected
# f1 s_a_15 fault is detected
# f1 s_a_16 fault is detected
# f1 s_a_19 fault is detected
# f1 s_a_21 fault is detected
# 150 abcde=11100 o22o23=11 o22_f1o23_f1=11
# f1 s_a_6 fault is detected
# f1 s_a_11 fault is detected
# f1 s_a_15 fault is detected
# f1 s_a_17 fault is detected
# f1 s_a_19 fault is detected
# f1 s_a_21 fault is detected
# 155 abcde=11101 o22o23=11 o22_f1o23_f1=11
# f1 s_a_6 fault is detected
# f1 s_a_11 fault is detected
# f1 s_a_19 fault is detected
# f1 s_a_21 fault is detected
# 160 abcde=11110 o22o23=10 o22_f1o23_f1=10
# f1 s_a_3 fault is detected
# f1 s_a_8 fault is detected
# f1 s_a_10 fault is detected
# f1 s_a_12 fault is detected
# f1 s_a_14 fault is detected
# f1 s_a_19 fault is detected
# f1 s_a_22 fault is detected
# 165 abcde=11111 o22o23=10 o22_f1o23_f1=10
# f1 s_a_3 fault is detected
# f1 s_a_8 fault is detected
# f1 s_a_10 fault is detected
# f1 s_a_12 fault is detected
# f1 s_a_13 fault is detected
# f1 s_a_14 fault is detected
# f1 s_a_19 fault is detected
# f1 s_a_22 fault is detected
# 170 abcde=00000 o22o23=00 o22_f1o23_f1=00

Simulation Waveforms:TASK-1
Simulation Waveforms:TASK-2

Inference: In the above output waveform, the faults are detected whenever
y1 and y2 are not equal to the corresponding outputs during the presence of
fault.

Result:
TASK-1
Hence the test patterns have been found out for the stuck at 0 (SA0) or
stuck at 1 (SA1) fault injected in the combinational circuit.
TASK-2
Hence the test patterns have been found out for the stuck at 0 (SA0) or
stuck at 1 (SA1) fault injected in the combinational circuit.
Experiment 3(A): ATPG generation for combinational circuits C17 (Atalanta,
FSim, Hope)
Aim: To find the test patterns for the stuck at 0 (SA0) or stuck at 1 (SA1) fault
injected in the combinational circuit.
To generate ATPG for combinational circuits using test generation tools
ATALANTA, FSIM, HOPE.
Tools Used: ATALANTA, FSIM, HOPE
Combinational Circuit Diagram :

Bench Code:
# c17
# 5 inputs
# 2 outputs
# 0 inverter
# 6 gates ( 6 NANDs )
INPUT(1)
INPUT(2)
INPUT(3)
INPUT(6)
INPUT(7)
OUTPUT(22)
OUTPUT(23)
10 = NAND(1, 3)
11 = NAND(3, 6)
16 = NAND(2, 11)
19 = NAND(11, 7)
22 = NAND(10, 16)
23 = NAND(16,19)

Automatic Test Pattern Generation (ATPG):

Automatic Test Pattern Generation (ATPG) is a widely used technique in the
semiconductor industry to generate test patterns that can detect static
faults in digital circuits. Static faults are permanent faults that occur due to
manufacturing defects, such as stuck-at faults (where a signal line is
permanently stuck at either a high or low logic level) or bridging faults
(where two or more signal lines are shorted together).

The goal of ATPG for static faults is to generate a set of test patterns that can
detect as many of these faults as possible, while minimizing the number of
patterns and test time required. This is typically done using a fault model
that describes the types of faults that can occur in the circuit, and an ATPG
tool that can automatically generate test patterns that can detect these
faults.

The most commonly used fault model for ATPG is the stuck-at fault model,
which assumes that a signal line can be stuck at either a high or low logic
level. The ATPG tool generates test patterns that toggle or change the logic
value of each signal line in the circuit, and checks if any output signals are
affected by these changes. If an output signal does not change as expected,
a fault is detected.

ATPG for static faults is an important tool for ensuring that digital circuits are
free of manufacturing defects and meet performance specifications. It is
widely used in the semiconductor industry for testing integrated circuits
(ICs), microprocessors, memory chips, and other digital devices.
Procedure:
 File explorer -> ftp://172.16.71.153/
 Copy LAB2 folder
 Desktop-> VMware Workstation
VMware Workstation Desktop:
 Desktop-> root’s Home->root
 Location: /mnt/hgfs
 Copy LAB2 and paste in VMware workstation Desktop
Invoke Atalanta tool:
 Open terminal within LAB2
Commands:
 csh
 set path = ($path /root/Desktop/LAB2/LAB2/bin)
 setenv ATALANTA_MAN /root/Desktop/LAB2/LAB2/atalanta
 setenv FSIM_MAN /root/Desktop/LAB2/LAB2/fsim
 setenv HOPE_MAN /root/Desktop/LAB2/LAB2/hope
COMMANDS: >> atalanta -t c17.test -D 2 c17.bench
 Run for C17.bench file
 Report is generated after running the command
 Atalanta derives n test patterns for each fault. In this option, all
unspecified inputs are left unknown, and fault simulation is not
performed.
 INPUT: c17.bench OUTPUT : c17.test

OUTPUT:

* Name of circuit: c17.bench

Primary Inputs: 1 2 3 6 7
Primary Output: 22 23

Test Pattern & Fault free responses

7 /1
1: x00x0 00
11->19 /1
1: xx111 x0
16->23 /1
1: x10x0 11
2: x1100 11
23 /0
1: x10xx 11
2: x110x 11
19 /1
1: x00x1 01
2: x0101 x1
23 /1
1: x0xx0 x0
2: x0111 x0
6 /1
1: 0110x 1x
11 /1
1: 0111x 0x
2: 11110 10
3->11 /1
1: x101x 1x
2: x0011 01
11 /0
1: x10xx 1x
2: 0110x 1x
2 /1
1: 000xx 0x
11->16 /1
1: x111x x0
16 /0
1: 00xxx 0x
2: 0111x 00
16 /1
1: 010xx 1x
 2: 0110x 1x
3 /1
1: 100xx 0x
3 /0
1: 101xx 1x
1 /1
1: 001xx 0x
3->10 /1
1: 100xx 0x
16->22 /1
1: 010xx 11
2: 0110x 11
22 /0
1: 1x1xx 1x
2: 110xx 11
10 /1
1: 101xx 1x
2: 1111x 10
22 /1
1: 00xxx 0x
2: 0111x 00

Note:
MODE: DTPG+TC
NUMBER OF TEST PATTERNS: 35
FAULT COVERAGE: 100%
COLLAPSED FAULT: 22
NOTES:
In real-time, we don’t need all 35 test patterns; some are replicated.
COMMAND:>>atalanta -N -t c17.test c17.bench

 How many test patterns are more than enough to cover the 100% fault
coverage.
 Generate the test patterns without test compaction.
 INPUT: c17.bench OUTPUT: c17.test
Output :
* Name of circuit: c17.bench
* Primary inputs :
12367
* Primary outputs:
22 23
* Test patterns and fault free responses:
1: 00000 00
2:00111 00
3:11010 11
4:10001 01
5:01100 11
6:11111 10
#6 test vector is able to detect the 22 Faults.
Notes:
MODE: RPT+DTPG+TC (Random Pattern Generation)
NUMBER OF TEST PATTERN: 6
FAULT COVERAGE: 100%
COLLAPSED FAULTS: 22

#After applying Compaction, still the test vectors are reduced, and Fault
Coverage 100% maintained
 There are two types of Compactions: Space Compaction and Time
Compaction
 Space Compaction is for Combinational Circuits and Time Compaction is
for Sequential circuits.
 Space Compaction: Reducing the output pins.
  Space Compaction: No effect on logic and No effect on 100% Fault
Coverage
 Space compaction works by identifying redundant test patterns that do
not provide any additional fault coverage. These patterns are eliminated
or combined with other patterns to create a more compact set of test
patterns that still provides high fault coverage.
COMMAND:>>atalanta -t c17.test c17.bench
Atalanta derives n test patterns for each fault. In this option, all unspecified
inputs are left unknown, and fault simulation is not performed.
INPUT: c17.bench OUTPUT : c172.test

Output :

* Name of circuit: c17.bench

*Primary inputs :

12367

*Primary outputs:

22 23

* Test patterns and fault free responses:

1: 00101 11
2: 11110 10
3: 10011 01
4: 00000 00
5: 00111 00
6: 10101 11
Note:
MODE: RPT+DTPG+TC
NUMBER OF TEST PATTERN BEFOR COMPACTION: 8
NUMBER OF TEST PATTERN AFTER COMPACTION: 6
FAULT COVERAGE: 100%
COMMAND:>>atalanta -f c17.flt c17.bench
 Create c17.flt file
22 /1
22 /0
23 /1
23 /0
 SA0 and SA1 at particular pin
 Generates test patterns for c17.bench, writes them to c17.test. The
complete fault list is written to c17.flt.
 INPUT: c17.bench, c17.flt OUTPUT: c17.test

OUTPUT:
1: 00000 00
2: 11000 11
Notes:
NUMBER OF TEST PATTERN BEFORE COMPACTION: 2
NUMBER OF TEST PATTERN AFTER COMPACTION: 2
FAULT COVERAGE: 100%
COLLAPSED FAULT: 8

COMMAND:>>fsim -t c17.test c17.bench

 Simulates the circuit c17.bench using the test patterns in the file
"c17.test". The fault simulation stops when all test patterns in the file
 "c17.test" are simulated or all faults are detected. The summary of the
fault simulation is reported.
 INPUT: c17.bench, c17.test OUTPUT: Terminal
 Because other test vectors are stored at c17.test
 Disadvantage: We cannot get whether all faults detected or not and the
file is not generated for same.
OUTPUT File Generated Indicating the Fault Coverage of the given input
test vectors.

OUTPUT:
1: 00000 00
2: 00011 01
3: 10110 10
Notes:
NUMBER OF TEST PATTERN APPLIED: 3
FAULT COVERAGE: 59.091%
COLLAPSED FAULTS: 22
 DETECTED FAULT: 13
UNDETECTED FAULT: 9
COMMAND:>>hope -t c17.test -D c17.bench
 To overcome the disadvantage of fsim command, hope is used.
 INPUT: c17.bench, c17.test OUTPUT: c17.log
Output File with No of Faults with additional information of which faults are
detected and the faults which are not identified.
test 1: 00000 00 5 faults detected
22 /1
16 /0
2 /1
23 /1
7 /1
test 2: 00100 00 1 faults detected
1 /1
test 3: 11110 10 5 faults detected
10 /1
22 /0
3 /0
11->16 /1
11 /1
test 4: 01000 11 5 faults detected
16->22 /1
16 /1
11 /0
23 /0
16->23 /1
test 5: 10101 11 2 faults detected
6 /1
19 /1
test 6: 10010 00 2 faults detected
3->10 /1
3 /1
test 7: 10011 01 1 faults detected
3->11 /1
test 8: 11111 10 1 faults detected
11->19 /1
*******************************************************
* *
* Welcome to HOPE (version 2.0) *
* *
* Dong S. Ha ([email protected]) *
* Web: http://www.ee.vt.edu/ha *
* Virginia Polytechnic Institute & State University *
* *
*******************************************************

****** SUMMARY OF SIMULATION RESULTS ******

1. Circuit structure

Name of circuit : c17

Number of primary inputs : 5
Number of primary outputs : 2
Number of combinational gates : 6
Number of flip-flops : 0
Level of the circuit : 3
2. Simulator input parameters
Simulation mode : file (c17.test)

3. Simulation results
Number of test patterns applied : 8
Fault coverage : 100.000 %
Number of collapsed faults : 22
Number of detected faults : 22
Number of undetected faults : 0

4. Memory used : 166920 Kbytes

5. CPU time
Initialization : 0.000 secs
Fault simulation : 0.000 secs
Total : 0.000 secs

* List of undetected faults:

INFERENCE: The above commands are used to invoke the Atalanta,fsim and
hope software to find the test pattern, stuck at faults, detected faults and
undetected faults for a combinational circuit.
RESULT: Hence the ATPG generation for combinational circuits C17(Atalanta,
FSim, Hope).
Experiment 3(B): ATPG generation for combinational circuits MUX (Atalanta,
FSim, Hope)
Aim: To find the test patterns for the stuck at 0 (SA0) or stuck at 1 (SA1) fault
injected in the combinational circuit.
To generate ATPG for combinational circuits using test generation tools
ATALANTA, FSIM, HOPE.
Tools Used: ATALANTA, FSIM, HOPE
Combinational Circuit Diagram :

Bench Code:
Bench File
# c9
# 3 inputs
# 1 outputs
# 0 inverter
# 4 gates (2 AND Gate,1-Inverter,1-OR Gate)
INPUT(1)
INPUT(2)
INPUT(3)
OUTPUT(7)
5=AND(1,4)
6=AND(2,3)
4=NOT(2)
7=OR(5,6)
Automatic Test Pattern Generation (ATPG):
Automatic Test Pattern Generation (ATPG) is a widely used technique in the
semiconductor industry to generate test patterns that can detect static faults in
digital circuits. Static faults are permanent faults that occur due to
manufacturing defects, such as stuck-at faults (where a signal line is
permanently stuck at either a high or low logic level) or bridging faults (where
two or more signal lines are shorted together).
The goal of ATPG for static faults is to generate a set of test patterns that can
detect as many of these faults as possible, while minimizing the number of
patterns and test time required. This is typically done using a fault model that
describes the types of faults that can occur in the circuit, and an ATPG tool that
can automatically generate test patterns that can detect these faults.
The most commonly used fault model for ATPG is the stuck-at fault model,
which assumes that a signal line can be stuck at either a high or low logic level.
The ATPG tool generates test patterns that toggle or change the logic value of
each signal line in the circuit, and checks if any output signals are affected by
these changes. If an output signal does not change as expected, a fault is
detected.
ATPG for static faults is an important tool for ensuring that digital circuits are
free of manufacturing defects and meet performance specifications. It is widely
used in the semiconductor industry for testing integrated circuits (ICs),
microprocessors, memory chips, and other digital devices.
Procedure:
• File explorer -> ftp://172.16.71.153/
• Copy LAB2 folder
• Desktop-> VMware Workstation
VMware Workstation Desktop:
• Desktop-> root’s Home->root
• Location: /mnt/hgfs
• Copy LAB2 and paste in VMware workstation Desktop
Invoke Atalanta tool:
• Open terminal within LAB2
Commands:
• csh
• set path = ($path /root/Desktop/LAB2/LAB2/bin)
• setenv ATALANTA_MAN /root/Desktop/LAB2/LAB2/atalanta
• setenv FSIM_MAN /root/Desktop/LAB2/LAB2/fsim
• setenv HOPE_MAN /root/Desktop/LAB2/LAB2/hope
COMMANDS: >> 1.atalanta -t c9.test -D 2 c9.bench
• Run for C9.bench file
• Report is generated after running the command
• Atalanta derives n test patterns for each fault. In this option, all unspecified
inputs are left unknown, and fault simulation is not performed.
• INPUT: c9.bench
OUTPUT : c9.test OUTPUT File Generated for the Command
* Name of circuit: c9.bench
* Primary inputs : 1 2 3
* Primary outputs: 7
* Test patterns and fault free responses:
2 /0
1: 011 1
2 /1
1: 001 0
1 /1
1: 00x 0
3 /1 1: x10 0
2->6 /1
1: 001 0
7 /1
1: 00x 0 0
2: 010 0
4 /1
1: 110 0
5 /0
1: 10x 1
6 /0
1: x11 1
7 /0
1: x11 1
COMMAND:>> 2.atalanta -N -t c9.test c9.bench
• How many test patterns are more than enough to cover the 100% fault
coverage.
• Generate the test patterns without test compaction.
• INPUT: c9.bench
OUTPUT: c9.test Output File Generated for the Command
* Name of circuit: c9.bench
* Primary inputs : 1 2 3
* Primary outputs: 7
* Test patterns and fault free responses:
1: 000 0
2: 101 1
3: 110 0
4: 011 1
5: 100 1
6: 001 0
#After applying Test Compaction, still the test vectors are reduced, and Fault
Coverage 100% maintained
• There are two types of Compactions: Space Compaction and Time
Compaction
• Space Compaction is for Combinational Circuits and Time Compaction is for
Sequential circuits.
• Space Compaction: Reducing the output pins.
• Space Compaction: No effect on logic and No effect on 100% Fault Coverage
• Space compaction works by identifying redundant test patterns that do not
provide any additional fault coverage. These patterns are eliminated or
combined with other patterns to create a more compact set of test patterns
that still provides high fault coverage. COMMAND:>> 3.atalanta -t c9.test
c9.bench
Atalanta derives “n” test patterns for each fault. In this option, all unspecified
inputs are left unknown, and fault simulation is not performed.
INPUT: c9.bench OUTPUT : c9.test
Output File Generated for the Command
* Name of circuit: c9.bench
* Primary inputs : 1 2 3
* Primary outputs: 7
* Test patterns and fault free responses:
1: 100 1
2: 001 0
3: 110 0
4: 011 1
Note:
MODE: RPT+DTPG+TC
NUMBER OF TEST PATTERN BEFORE COMPACTION: 6
NUMBER OF TEST PATTERN AFTER COMPACTION: 4
FAULT COVERAGE: 100%
COMMAND:>>4.atalanta -f c9.flt c9.bench
• Create c9.flt file where you specify the faults these file acts as an input file
and at the output in the c9.test you get test vectors which are required to
identify these faults.
7 /1
1 /0
2 /1
3 /0
• SA0 and SA1 at particular pin
• Generates test patterns for c9.bench, writes them to c9.test. The complete
fault list is written to c9.flt.
• INPUT: c9.bench, c9.flt OUTPUT: c9.test
Output:
The output file which we get in the c9.test represents the test vectors for the
faults specified in the “c9.flt” file.
Output generated in the C9.test file from the command atalanta -f c9.flt
c9.bench
* Name of circuit: c9.bench
* Primary inputs : 1 2 3
* Primary outputs: 7
* Test patterns and fault free responses:
1: 011 1
2: 000 0
3: 100 1
COMMAND:>>5.fsim -t c9.test c9.bench
• Simulates the circuit c9.bench using the test patterns in the file "c9.test". The
fault simulation stops when all test patterns in the file "c9.test" are simulated
or all faults are detected. The summary of the fault simulation is reported.
• INPUT: c9.bench, c9.test OUTPUT: Terminal
• Because other test vectors are stored at c9.test
• Disadvantage: We cannot get whether all faults detected or not and the file is
not generated for same.
OUTPUT:

COMMAND:>>6.hope -t c9.test -D c9.bench

• To overcome the disadvantage of fsim command, hope is used.
• INPUT: c9.bench, c9.test OUTPUT: c9.log
OUTPUT Log File Generated:
test 1: 011 1 3 faults detected
7 /0
6 /0
2 /0
test 2: 000 0 2 faults detected
7 /1
1 /1
test 3: 100 1 2 faults detected
5 /0
2 /1
*******************************************************
* *
* Welcome to HOPE (version 2.0) *
* *
* Dong S. Ha ([email protected]) *
* Web: http://www.ee.vt.edu/ha *
* Virginia Polytechnic Institute & State University *
* *
*******************************************************

****** SUMMARY OF SIMULATION RESULTS ******

1. Circuit structure
Name of circuit : c9
Number of primary inputs :3
Number of primary outputs : 1
Number of combinational gates : 4
Number of flip-flops : 0
Level of the circuit : 3

2. Simulator input parameters

Simulation mode : file (c9.test)

3. Simulation results
Number of test patterns applied : 3
Fault coverage : 70.000 %
Number of collapsed faults : 10
Number of detected faults : 7
Number of undetected faults : 3
4. Memory used : 136937 Kbytes

5. CPU time
Initialization : 0.000 secs
Fault simulation : 0.000 secs
Total : 0.000 secs
* List of undetected faults:
1. 4 /1
2. 2->6 /1
3. 3 /1
INFERENCE: The above commands are used to invoke the Atalanta,fsim and
hope software to find the test pattern, stuck at faults, detected faults and
undetected faults for a combinational circuit.
RESULT: Hence the ATPG generation for combinational circuits C9-
Mux(Atalanta, FSim, Hope)
 EXPERIMENT 4: DFT SYNTHESIS
Aim: Scan insertion, (DRC) DFT Rule Check and Synthesis of given circuit.

EDA Tool: Cadence Genus

Description: DFT synthesis using scan chain insertion is a common technique

employed to enhance the testability of digital circuits. The process involves
inserting scan chains into the design to facilitate the capture and observation of
internal signals during testing. Here's an overview of the steps involved in DFT
synthesis using scan chain insertion.
1. Identify Flip-Flops/Latches: The first step is to identify the flip-flops or latches
within the design. These elements serve as the storage elements for the circuit
and are crucial for capturing and launching test patterns.
2. Create Scan Chains: Scan chains are created by connecting the identified flip-
flops or latches in a serial chain configuration. This involves adding additional
inputs and outputs to each flip-flop or latch to facilitate the shifting of test
data.
3. Insert Test Points: Test points, also known as scan test points or scan pins,
are inserted at specific locations in the circuit to provide access to the internal
signals. These test points allow for the application of test patterns and the
observation of response data.
4. Reconfigure Flip-Flops/Latches: The flip-flops or latches in the design are
reconfigured to support scan mode operation. In scan mode, the flip-flops or
latches shift in and shift out test data through the scan chains, bypassing the
normal data paths.
Normal Flipflop:
Scan Flipflop:

When using scan chains in DFT synthesis, two modes are commonly employed:
the normal (functional) mode and the scan mode.
1. Normal (Functional) Mode:
In the normal mode, the circuit operates as intended during regular operation.
The scan chains are bypassed, and the flip-flops or latches function according
to their designed behavior. The circuit performs its intended logic functions,
and the scan chains do not affect the data flow.
2. Scan Mode:
In the scan mode, the scan chains are activated, allowing for the shifting of test
data into and out of the flip-flops or latches. This mode is specifically used for
testing purposes, enabling the capture and observation of internal signals for
fault detection.
In scan mode, the normal operation of the circuit is suspended, and the scan
chains take over the data path. The scan D flip-flops replace the normal flip-
flops or latches, incorporating additional inputs and outputs for scan chain
operation. The control logic is modified to ensure proper activation of the scan
mode, enabling the shifting of test patterns through the scan chains.
Working:

A muxed scan flip-flop, also known as a MUX scan flip-flop, is a type of scan
flip-flop that combines both scan and functional modes of operation within a
single flip-flop. It allows for the testing and normal operation of a circuit using a
shared set of flip-flops. Here's how a muxed scan flip-flop typically works:
1. Scan Mode:
In the scan mode, the muxed scan flip-flop behaves like a regular scan flip-flop
and enables the shifting of test data into and out of the flip-flop. The flip-flop is
connected to a scan chain, which allows for the loading of test patterns and the
observation of internal signals during testing.
2. Functional Mode:
In the functional mode, the muxed scan flip-flop operates like a regular flip-flop
and performs its intended logic function during normal circuit operation. It
behaves as a part of the sequential logic circuit, participating in data flow and
state transitions.
3. Select Input:
The key feature of a muxed scan flip-flop is the select input, also known as the
mode control input. This select input determines whether the flip-flop operates
in scan mode or functional mode. When the select input is set to the scan
mode value, the flip-flop enters the scan mode, allowing for test data shifting.
When the select input is set to the functional mode value, the flip-flop
operates in functional mode, performing its normal logic function.
4. Control Logic:
The control logic of the circuit controls the select input of the muxed scan flip-
flop based on the desired mode of operation. The control signals determine
when the flip-flop should be in scan mode or functional mode, depending on
whether the circuit is in a testing or normal operation phase.
By using muxed scan flip-flops, the same set of flip-flops can be shared
between the scan mode and functional mode, reducing the number of
dedicated scan flip-flops required in the design. This helps optimize the
utilization of flip-flops in the circuit.
It's important to note that the specific implementation and behavior of muxed
scan flip-flops can vary depending on the design and the chosen flip-flop
architecture. Different scan flip-flop designs may have variations in the control
logic, select input values, and mode switching mechanisms.
DFT Rule Check: Things to be followed:
 Large circuit should be partitioned into smaller subcircuit in chip.
 Test access point must be inserted to enhance controllability and
observability of the circuit. (SE & SI are access points)
 Circuit (FF) is easily initiable to enhance predictability.
 Test control must be provided for difficult to control signal.
 Avoid asynchronous clock.
 Monostable & self-resetting logic should be avoided.
 Redundant gates must be avoided.
 High fanin/fanout combinations must be avoided.
 Gated clock must be avoided.
Procedure:
  Computer => Filesystem => cad => DFT synthesis
 Copy and paste the DFT synthesis folder on Desktop
 DFT synthesis Folder consist of Constraint, RTL folders and two .tcl files.
 Open the terminal:
 csh
 source /cad/cshrc
 genus -legacy_ui
 source rc_script.tcl
 source rc_dft_script.tcl
 Record all the reports obtained.
Before DFT Synthesis:
1. .v file for counter:

2. RTL Design:

3. Gate report:
4. Timing Report:

5. Power Report:
6. Area Report:

7. QOR Report:

8. Netlist:
After DFT Synthesis:
 Gates count increases because of muxed D Flipflop insertion in place of
normal flipflop. Hence, leaf cells increase which in turn area and power
increases.
1. .v test file for counter:

2. RTL Design:

3. Gate Report:
4. Timing Report:

5. Power Report:

6. Area Report:
7. QOR Report: