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Exp01 CCR

The document describes an experiment to generate test patterns for detecting stuck-at faults in a combinational circuit. It involves modeling stuck-at-0 and stuck-at-1 faults in Verilog, simulating the fault-free and fault-injected circuits with different inputs, and identifying the test patterns that cause differences in outputs, thus detecting the faults. Faults were injected one by one at various wires and the corresponding detecting test patterns were logged. The output waveform from the testbench simulation verified that the faults were detected for the test patterns where the faulty and fault-free circuit outputs did not match.

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16 views16 pages

Exp01 CCR

The document describes an experiment to generate test patterns for detecting stuck-at faults in a combinational circuit. It involves modeling stuck-at-0 and stuck-at-1 faults in Verilog, simulating the fault-free and fault-injected circuits with different inputs, and identifying the test patterns that cause differences in outputs, thus detecting the faults. Faults were injected one by one at various wires and the corresponding detecting test patterns were logged. The output waveform from the testbench simulation verified that the faults were detected for the test patterns where the faulty and fault-free circuit outputs did not match.

Uploaded by

Christopher cr
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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VLSI TESTING AND TESTABILITY LAB REPORT

MVLD506P

Prepared by
CHRISTOPHER C R
23MVD1057
M.TECH VLSI DESIGN
Experiment No:01
Fault Simulation and Test pattern Generation for a Combinational Circuit

Aim: To find the test patterns for the stuck at 0 (SA0) or stuck at 1 (SA1) fault injected in the
combinational circuit.

EDA Tools Used: ModelSim

Description: A stuck-at fault is a particular fault model used by fault simulators and automatic
test pattern generation (ATPG) tools to mimic a manufacturing defect within an integrated
circuit. Individual signals and pins are assumed to be stuck at Logical '1', '0' and 'X'. Here, the
wires w7, w5 and w2 are tied to a logical 0 state during test generation to assure that a
manufacturing defect (stuck-at 0 – SA0 fault) with that type of behavior can be found with a
specific test pattern. Likewise, the wires w8, w5 and w2 are tied to a logical 1 to model the
behavior of a defective circuit (stuck-at 1 – SA1 fault) that cannot switch its output pin. When
the output of fault-free circuit and that of fault injected circuit varies, it implies the respective
stuck-at fault can be detected by the corresponding test pattern.

Combinational Circuit Diagram:


Manual Calculation and Observation:
Verilog Code for Fault Free:

module fault_free(a,b,c,d,y1,y2);

input a,b,c,d;

output y1,y2;

wire w1,w2,w3,w4,w5,w6,w7,w8;

not i1(w1,b);

and a1(w2,a,w1);

or o1(w3,c,d);

and a2(w4,a,w2);

nand n1(w5,w2,w3);

or o2(w6,w3,d);

nand n2(w7,w5,w4);

nor e1(w8,w2,w5,w6);

or a3(y1,d,w7);

nand a4(y2,a,w8);

endmodule

Verilog Code for Fault 1:

module fault1(a,b,c,d,y1,y2);

input a,b,c,d;

output y1,y2;

wire w1,w2,w3,w4,w5,w6,w7,w8;

wire f1;

not i1(w1,b);

and a1(w2,w1,a);

or o1(w3,c,d);
and a2(w4,a,w2);

nand n1(w5,w2,w3);

or o2(w6,w3,d);

nand n2(w7,w4,w5);

and a5(f1,1'b0,w7);

nor e1(w8,w5,w2,w6);

or a3(y1,f1,d);

nand a4(y2,a,w8);

endmodule

Verilog Code for Fault 2:

module fault2(a,b,c,d,y1,y2);

input a,b,c,d;

output y1,y2;

wire w1,w2,w3,w4,w5,w6,w7,w8;

wire f2;

not i1(w1,b);

and a1(w2,w1,a);

or o1(w3,c,d);

and a2(w4,a,w2);

nand n1(w5,w2,w3);

and a5(f2,1'b0,w5);

or o2(w6,w3,d);

nand n2(w7,w4,f2);

nor e1(w8,f2,w2,w6);

or a3(y1,w7,d);
nand a4(y2,a,w8);

endmodule

Verilog Code for Fault 3:

module fault3(a,b,c,d,y1,y2);

input a,b,c,d;

output y1,y2;

wire w1,w2,w3,w4,w5,w6,w7,w8;

wire f3;

not i1(w1,b);

and a1(w2,w1,a);

and a5(f3,w2,1'b0);

or o1(w3,c,d);

and a2(w4,a,f3);

nand n1(w5,f3,w3);

or o2(w6,w3,d);

nand n2(w7,w4,w5);

nor e1(w8,w5,f3,w6);

or a3(y1,w7,d);

nand a4(y2,a,w8);

endmodule

Verilog Code for Fault 4:

module fault4(a,b,c,d,y1,y2);

input a,b,c,d;

output y1,y2;

wire w1,w2,w3,w4,w5,w6,w7,w8,f4;
not i1(w1,b);

and a1(w2,w1,a);

or o1(w3,c,d);

and a2(w4,a,w2);

nand n1(w5,w2,w3);

or o2(w6,w3,d);

nand n2(w7,w4,w5);

nor e1(w8,w5,w2,w6);

or a5(f4,w8,1'b1);

or a3(y1,w7,d);

nand a4(y2,a,f4);

endmodule

Verilog Code for Fault 5:

module fault5(a,b,c,d,y1,y2);

input a,b,c,d;

output y1,y2;

wire w1,w2,w3,w4,w5,w6,w7,w8,f5;

not i1(w1,b);

and a1(w2,w1,a);

or o1(w3,c,d);

and a2(w4,a,w2);

nand n1(w5,w2,w3);

or o3(f5,1'b1,w5);

or o2(w6,w3,d);
nand n2(w7,w4,f5);

nor e1(w8,f5,w2,w6);

or a3(y1,w7,d);

nand a4(y2,a,w8);

endmodule

Verilog Code for Fault 6:

module fault6(a,b,c,d,y1,y2);

input a,b,c,d;

output y1,y2;

wire w1,w2,w3,w4,w5,w6,w7,w8,f6;

not i1(w1,b);

and a1(w2,w1,a);

or o3(f6,1'b1,w2);

or o1(w3,c,d);

and a2(w4,a,f6);

nand n1(w5,f6,w3);

or o2(w6,w3,d);

nand n2(w7,w4,w5);

nor e1(w8,w5,f6,w6);

or a3(y1,w7,d);

nand a4(y2,a,w8);

endmodule

Verilog Test for all Cases:

module fault_tb();
reg a,b,c,d;

wire y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12,y13,y14;

fault_free dut(a,b,c,d,y1,y2);

fault1 dut1(a,b,c,d,y3,y4);

fault2 dut2(a,b,c,d,y5,y6);

fault3 dut3(a,b,c,d,y7,y8);

fault4 dut4(a,b,c,d,y9,y10);

fault5 dut5(a,b,c,d,y11,y12);

fault6 dut6(a,b,c,d,y13,y14);

initial

begin

a=1'b0;b=1'b0;c=1'b0;d=1'b0;

#10 a=1'b0;b=1'b0;c=1'b0;d=1'b0;

#10 a=1'b0;b=1'b0;c=1'b0;d=1'b1;

#10 a=1'b0;b=1'b0;c=1'b1;d=1'b0;

#10 a=1'b0;b=1'b0;c=1'b1;d=1'b1;

#10 a=1'b0;b=1'b1;c=1'b0;d=1'b0;

#10 a=1'b0;b=1'b1;c=1'b0;d=1'b1;

#10 a=1'b0;b=1'b1;c=1'b1;d=1'b0;

#10 a=1'b0;b=1'b1;c=1'b1;d=1'b1;

#10 a=1'b1;b=1'b0;c=1'b0;d=1'b0;

#10 a=1'b1;b=1'b0;c=1'b0;d=1'b1;

#10 a=1'b1;b=1'b0;c=1'b1;d=1'b0;
#10 a=1'b1;b=1'b0;c=1'b1;d=1'b1;

#10 a=1'b1;b=1'b1;c=1'b0;d=1'b0;

#10 a=1'b1;b=1'b1;c=1'b0;d=1'b1;

#10 a=1'b1;b=1'b1;c=1'b1;d=1'b0;

#10 a=1'b1;b=1'b1;c=1'b1;d=1'b1;

end

always@(a or b or c or d)

begin

$display("Test Patterns \t\t Response from faultfree \t\t response from fault");

$display(" abcd=%b%b%b%b \t\t y1y2=%b%b \t\t y1_f1 y2_f1=%b%b",a,b,c,d,y1,y2,y3,y4);

$display(" abcd=%b%b%b%b \t\t y1y2=%b%b \t\t y1_f2 y2_f2=%b%b",a,b,c,d,y1,y2,y5,y6);

$display(" abcd=%b%b%b%b \t\t y1y2=%b%b \t\t y1_f3 y2_f3=%b%b",a,b,c,d,y1,y2,y7,y8);

$display(" abcd=%b%b%b%b \t\t y1y2=%b%b \t\t y1_f4 y2_f4=%b%b",a,b,c,d,y1,y2,y9,y10);

$display(" abcd=%b%b%b%b \t\t y1y2=%b%b \t\t y1_f5 y2_f5=%b%b",a,b,c,d,y1,y2,y11,y12);

$display(" abcd=%b%b%b%b \t\t y1y2=%b%b \t\t y1_f6 y2_f6=%b%b",a,b,c,d,y1,y2,y13,y14);

if(y1!=y3 || y2!=y4);

$display("a=%b,b=%b,c=%b,d=%b,stuck at 0 fault at w7",a,b,c,d);

if(y1!=y5 || y2!=y6);

$display("a=%b,b=%b,c=%b,d=%b,stuck at 0 fault at w5",a,b,c,d);

if(y1!=y7 || y2!=y8);

$display("a=%b,b=%b,c=%b,d=%b,stuck at 0 fault at w2",a,b,c,d);

if(y1!=y9 || y2!=y10);

$display("a=%b,b=%b,c=%b,d=%b,stuck at 1 fault at w8",a,b,c,d);

if(y1!=y11 || y2!=y12);

$display("a=%b,b=%b,c=%b,d=%b,stuck at 1 fault at w5",a,b,c,d);


if(y1!=y13 || y2!=y14);

$display("a=%b,b=%b,c=%b,d=%b,stuck at 1 fault at w2",a,b,c,d);

end

endmodule

Output Waveform from Testbench Simulation:

Transcript:
Inference: In the above output waveform, the faults are detected whenever y1 and y2 are not
equal to the corresponding outputs during the presence of fault.

Result: Hence the test patterns have been found out for the stuck at 0 (SA0) or stuck at 1 (SA1)
fault injected in the combinational circuit

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