Code No: R2032043 R20 SET -1

III B. Tech II Semester Regular Examinations, July -2023

DIGITAL SIGNAL PROCESSING
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 70
Answer any FIVE Questions ONE Question from Each unit
All Questions Carry Equal Marks
*****
UNIT-I
1. a) Find the linear, invariance and casuality property of given system represented by : [7M]
y(n) = x(n) – ax(n - 1).
b) Find the convolution of the signals x(n) = i) (a)nu(n) and h(n) = (b)nu(n). [7M]
(OR)
2. a) Write the properties of ROC of X(z). [7M]
b) Find the magnitude and phase response for the system characterized by the difference [7M]
equation .
UNIT-II
3. a) State and prove the following properties of DFT [7M]
i) circular frequency shift ii)Parseval’s Theorem.
b) Develop a DIF FFT algorithm and draw its flow diagram. [7M]
(OR)
4. a) Find the DFT of i) x*(n) ii) x*(-n) iii) Re{x(n)} iv) Im {x(n)} [7M]
b) Find the IDFT of the sequence using DIF algorithm Y (k) = {10, -2-j2, -2, -2+j2} [7M]
UNIT-III
5. a) Determine the digital filter Transformation from the following analog T.F [7M]
Ha(s)= 1 / (s+0.5)(s2+0.5s+2) using Impulse Invariant Method .Assume Ts= 1
sec.
b) With an example explain the design procedure for Butterworth filter [7M]
(OR)
6. a) Design a digital Butterworth filter that satisfies the following specifications : [7M]
0.9< |H(jw)| ≤ 1, for 0 ≤ w ≤ π /2
|(H(jw)|< 0.2 , for ¾ π ≤w≤ π using BLT .Assume Ts= 1 sec
b) Explain basic structures and Transposed forms of IIR systems with suitable [7M]
examples.
UNIT-IV
7. a) Design a 7-tap linear FIR Digital filter with a cut-off frequency of ±3 π/4 rad [7M]
using hamming window.
b) Obtain the parallel realization of the system described by the difference equation [7M]

(OR)
8. a) Explain the need for the use of window sequence in the design of FIR filter. Describe [7M]
the window sequence generally used and compare the properties.
b) Determine the lattice filter representation for the following FIR filter: [7M]
H(z) = 1+ 7/8 z-1 + 11/16 z-2 + ¼ z-3

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 Code No: R2032043 R20 SET -1

UNIT-V
9. a) Discuss the salient features and special addressing modes of Digital signal [7M]
processors.
b) Explain briefly the following for TMS320C5X: i) Flags available in status register ii) [7M]
Parallel Logic Unit.
(OR)
10. a) Explain in detail the architecture of TMS320C5X processor. [7M]
b) With neat block diagram, explain about the pipelining in DSP processors. [7M]

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 Code No: R2032043
R2031011
R2031351
R203135A
R203147A
R203147C
R203105O
P2031051 R20 SET
SET
RA--22

III B. Tech II Semester Regular Examinations, July -2023

DIGITAL SIGNAL PROCESSING
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 70
Answer any FIVE Questions ONE Question from Each unit
All Questions Carry Equal Marks
*****
UNIT-I
1. a) Determine the Inverse Z-Transform of: X(Z)=1/(1-Z -1 )(1-Z -1 )2 . [7M]
b) Defne Disrete time systems ,explain the classification with suitable exampls [7M]
(OR)
2. a) Find the frequency response H(ejw) of the linear time-invariant system whose [7M]
input and output satisfy the difference equation:

b) A causal LTI system is defined by the difference equation: [7M]

2y(n)-y(n-2)=x(n1)+3x(n-2)+2x(n-3). Find the frequency response H (e jw),
magnitude response and phase response.
UNIT-II
3. a) Define DFT and then state and prove properties of DFT. [7M]
b) Given X(K) = { 36,-4+j9.565, -4+j4,-4+j1.656,-4,-4-j1.656,-4-j4,-4-j9.656} [7M]
find x(n) using FFT algorithm
(OR)
4. a) Show how the complexity of computing DFT can be reduced by Radix-2 DIF [7M]
algorithm with suitable diagrams.
b) [7M]
Determine the 8 point DFT of the sequence
UNIT-III
5. a) For the analog transfer function H(s) = 2/ {(s+2) (s+3)}. Determine H (z) using [7M]
impulse invariance method. Assume T = 1 sec
b) Determine the order and poles of type-I chebyshev low pass filter for the given [7M]
specifications:
αp = 1 dB, αs = 40 dB, Ωp= 1000Π rad/sec Ωs = 2000 Π rad/ sec.
(OR)
6. a) Design a digital second order Low-Pass Butterworth filter with cut-off [7M]
frequency 2.2KHz using Bilinear Transformation. Sampling rate 8 KHz
b) Compare Impulse invariant and bilinear transformation methods. [7M]
UNIT-IV
7. a) Design an FIR low pass filter satisfying the following specifications [7M]

b) Given a 3-stage lattice FIR filter with coefficients, k1=(1/4); k2=(1/2); k3=(1/3); [7M]
Determine the FIR filter coefficients for the direct form structure.
(OR)
8. a) Design a low pass filter using Hanning window with a cutoff frequency of 0.9 [7M]
radians/sec and N=6. Draw the filter structure and plot its spectrum.
b) Find the structural representation in direct and transposed form for system [7M]
described by the difference equation.
y(n) = x(n) – 0.3 x(n - 1) - 0.7 x(n - 2) + 0.6 y(n - 1) + 0.8 y(n - 2)
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 Code No: R2032043 R20 SET - 2

UNIT-V
9. a) Explain in brief memory access schemes in DSP processors. [7M]
b) Draw the pipelined MAC configuration to perform convolution operation and [7M]
Explain with neat timing diagrams.
(OR)
10. a) Explain how the VLIW architecture is improving the performance of DSP [7M]
processor.
b) What is meant by bit reversed addressing mode? What is the application for [7M]
which this addressing mode is preferred?

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 Code No: R2032043
R2031011
R2031351
R203135A
R203147A
R203147C
R203105O
P2031051 R20 SET
SET
RA--32

III B. Tech II Semester Regular Examinations, July -2023

DIGITAL SIGNAL PROCESSING
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 70
Answer any FIVE Questions ONE Question from Each unit
All Questions Carry Equal Marks
*****

UNIT-I
1. a) Define an LTI System and show that the output of an LTI system is given by the [7M]
convolution of Input sequence and impulse response.
b) Check the following filter for time invariant, causal and linear [7M]
i) y (n) = (n-1) (n+1) ii) y(n) = x (n-2)
(OR)
2. a) Explain the concept of stability and causality with examples. [7M]
b) An LTI system is described by the equation y(n)=x(n)+0.81x(n-1)-0.81x(n2)-0.45y(n- [7M]
2). Determine the transfer function of the system. Sketch the poles and zeroes on the
Z-plane
UNIT-II
3. a) Perform i) Linear Convolution ii) Circular Convolution for the following [7M]
sequence
x(n)= 1, n=0 h(n) = 0.5, n= 0
= 0.5, n=1 = 1, n= 1
= 0, otherwise = 0, otherwise
And Show when they are equal.

b) Develop a radix-2 DIT FFT algorithm for evaluating the DFT for N = 8. [7M]
(OR)
4. a) Explain how DFT provides an alternative approach to time domain convolution [7M]
through linear filtering.
b) Find the DFT of the given sequence by using DIF FFT. [5+5] x(n) = {0.5, 1.5, -0.5, - [7M]
0.5}
UNIT-III
5. a) Design an analog filter for the following specifications: [7M]

-1< |H(jΩ)|db ≤ 0, for 0 ≤ Ω ≤1404π rad/s

|(H(jΩ)|db< -60 , for Ω ≥ 8268π rad/s
b) Discuss the impulse invariant method and also explain its limitations. [7M]
(OR)
6. a) Explain the procedure for designing Analog filters using the Chebyshev [7M]
approximation.
b) Using Bilinear transformation, design a high pass filter, monotonic in pass band with [7M]
cutoff frequency of 1000 Hz and down 10dB at 350 Hz. The sampling frequency is
5000 Hz.
UNIT-IV
7. a) Explain the canonical form of digital filter realization with suitable examples. [7M]
b) Design a FIR digital low-pass filter with a cutoff frequency of 1 kHz and a sampling [7M]
rate of 4 kHz with 7 samples using Fourier series method.
(OR)
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 Code No: R2032043 R20 SET -3

8. a) Using a Hanning window technique, design a low pass filter with pass band gain of [7M]
unity, cut-off frequency of 1000Hz and working at a sampling frequency of 5 KHz.
The length of the impulse response should be 7
b) [7M]
Realize the system function by linear phase FIR structure.
UNIT-V
9. a) Write about the architectural features of TMS320C5X DSP processor. [7M]
b) How much memory can be Interfaced to TMS320C5X? Explain in detail its [7M]
Memory mapping.
(OR)
10. a) Explain the special addressing modes of DSP with suitable examples. [7M]
b) Explain the i) Bus Structure ii) On-chip peripherals in a TMS320C5X DSP [7M]
processor.

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 Code No: R2032043
R2031011
R2031351
R203135A
R203147A
R203147C
R203105O
P2031051 R20 SET
SET
RA--42

III B. Tech II Semester Regular Examinations, July -2023

DIGITAL SIGNAL PROCESSING
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 70
Answer any FIVE Questions ONE Question from Each unit
All Questions Carry Equal Marks
*****

UNIT-I
1. a) Determine the impulse response h(n) for the system described by the second order [7M]
difference equation y (n) – 4 y (n-1) + 4 y (n-2) = x (n-1)
b) Establish the relation between DFT and Z-transform. [7M]
(OR)
2. a) Determine the stability of the following systems using Z-transform: [7M]
i) h(n) = 2n u(n) ii) h(n) = 5n u(3-n)
b) Determine the causal signal x(n) having the Z-transform [7M]
X(Z) = (Z2+Z )/[ (Z- ½)2 (Z-¼) ]
UNIT-II
3. a) Find the DFT of a sequence y[n)= { 1,2,3,4,4,3,2,1} using: [7M]
i) DIT algorithm ii) DIF algorithm.
b) Let x(n) be a real valued sequence with N-points and Let X(K) represent its DFT , [7M]
with real and imaginary parts denoted by XR(K) and XI (K) respectively. So that
X (K) = XR (K) + JXI (K). Now show that if x (n) is real, XR (K) is even and XI (K) is
odd.
(OR)
4. a) Compute 4-point DFT of a sequence x (n) = { 0,1,2,3} using DIT algorithm. [7M]
b) Draw the butterfly line diagram for 8 - point FFT calculation and briefly explain. Use [7M]
decimation -in-time algorithm.
UNIT-III
5. a) [7M]
Apply bilinear transformation to
b) For the given specifications design an analog Butterworth filter. [7M]

(OR)
6. a) Using the bilinear transform, design a high pass filter, monotonic in password with [7M]
cutoff frequency of 1000 Hz and down 10 dB at 350 Hz. The sampling frequency is
5000 Hz.
b) What are the steps to design an analog Chebyshev High pass filter. [7M]
UNIT-IV
7. a) Explain the design procedure of linear phase FIR filter using Fourier series method. [7M]
b) Consider a second order IIR filter with: [7M]
.
Find the effect on quantization on pole locations of the given system function in direct
form and in cascade form. Assume b=3 bits.
(OR)
8. a) Explain the type -1 FIR filter design procedure using frequency sampling method. [7M]
b) Explain how reduction of product round-off error is achieved in digital filters? [7M]
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 Code No: R2032043 R20 SET -4

UNIT-V
9. a) Discuss various interrupt types supported by TMS320C5X processor. [7M]
b) Explain the memory access schemes in P-DSP’s. [7M]
(OR)
10. a) Explain the functioning of Multiplier and Multiplier Accumulator in DSP [7M]
processor.
b) Explain the functions of on-chip peripherals in a DSP processor. [7M]

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