05 - Instruction Set Architecture I
05 - Instruction Set Architecture I
Edition
The Hardware/Software Interface
Chapter 2 | Part 1
Instructions: Language
of the Computer
§2.1 Introduction
Instruction Set
The repertoire of instructions of a
computer
Different computers have different
instruction sets
But with many aspects in common
Early computers had very simple
instruction sets
Simplified implementation
Many modern computers also have simple
instruction sets
$s3: 1000
A [0]
A [1]
...
1000 + 8x4
A [8]
Range: 0 to +2n – 1
Example
0000 0000 0000 0000 0000 0000 0000 10112
=0+ + 1×23 + 0×22 +1×21 +1×20
=0+ + 8 + 0 + 2 + 1 = 1110
Using 32 bits
0 to +4,294,967,295
x + x = 1111...1112 = −1
x + 1 = −x
Example: negate +2
+2 = 0000 0000 00102
–2 = 1111 1111 11012 + 1
= 1111 1111 11102
Instruction fields
op: operation code (opcode)
rs: first source register number
rt: second source register number
rd: destination register number
shamt: shift amount (00000 for now)
funct: function code (extends opcode)
0 17 18 8 0 32
000000100011001001000000001000002 = 0232402016
Result in $v0
main()
{ ----
----
A (3); $ao = 3
--- $ra = address X
}
int A (int n)
{ ---
B (5)
---
}
int B (int m)
{ ---
}
main()
{ ----
----
A (3); $ao = 3
--- $ra = address X
}
int A (int n)
{ ---
B (5)
--- $ao = 5
} $ra = address Y
Result in $v0
i in $s0
lui $s0, 61 0000 0000 0111 1101 0000 0000 0000 0000
ori $s0, $s0, 2304 0000 0000 0111 1101 0000 1001 0000 0000
op rs rt constant or address
6 bits 5 bits 5 bits 16 bits
PC-relative addressing
Target address = PC + offset × 4
PC already incremented by 4 by this time
Chapter 2 — Instructions: Language of the Computer — 59
Jump Addressing
Jump (j and jal) targets could be
anywhere in text segment
Encode full address in instruction
op address
6 bits 26 bits