International Journal of Innovative Research in Computer Science & Technology (IJIRCST)

ISSN (online): 2347-5552, Volume-11, Issue-2, March 2023

https://doi.org/10.55524/ijircst.2023.11.2.11
Article ID IRP1373, Pages 58-61
www.ijircst.org

Verification of UART and I2C Protocols Using System Verilog

Dr. Ch. Manohar Kumar1, Mr. G. Mahesh Babu2, Mr. A. Hemanth Chakradhar3, Mr. A.S.K.
Pranav4, Mr. D. Sudheer5, and Mr. U. Alex Prince6
1
Assistant Professor, Department of Electronics and Communication Engineering, Gayatri Vidya Parishad College for Degree
and PG Courses(A), Visakhapatnam, Andhra Pradesh, India
2,3,4,5,6
Student, Department of Electronics and Communication Engineering, Gayatri Vidya Parishad College for Degree
andPG Courses(A), Visakhapatnam, Andhra Pradesh, India
Correspondence should be addressed to Dr. Ch. Manohar Kumar; [email protected]
Copyright © 2023 Made Dr. Ch. Manohar Kumar et al. This is an open access article distributed under the Creative Commons Attribution
License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

ABSTRACT- Design Verification in VLSI is the most KEYWORDS- Verification, Protocols, UART, I2C,
important step in the product development process. It aims System Verilog.
toconfirm that the system designed meets with the standards
andrequirements of the system. Verification is the process I. INTRODUCTION
ofchecking whether the designed system performs all the
required functionality specified in the design by writing the A. Verification in VLSI is Done in Two Stages
test bench or verification environment that contains group Verification is the Predictive analysis that is done to make
ofclasses and modules which generates input stimulus to sure the design will carry out the specified input output
the system and the output from that design is compared function when manufactured [1].
with the expected output. Test: A production phase that verifies there are no
A communication system has set of roles those are called manufacturing defects in the actual product that was
protocols. UART is a serial communication protocol that created from the synthesized design.
is used when only two devices are needed to communicate System Verilog has special features like randomization,
and it uses peer to peer topology. I2C stands for Inter functional coverage, assertions and use OOP features in
Integrated Circuit used for communication between master test bench construction.
and slave in which more than one slave devices or memory Test bench is a group of classes or components where each
can be connected to a master device. System Verilog has component is responsible for performing a specific
been primarily used for the verification purposes in VLSI operation.
because it has the features of Hardware Description i.e. generating stimulus, driving to the DUT, monitoring,
Languages such as Verilog and VHDL, C and C++ and comparing and scheduling different events like reset, main
functional coverage, assertion coverage, constrained tasks etc. and those classes will be named based on the
randomization and supports OOPs concepts. operation[9,10].

Figure 1: Block Diagram of System Verilog Test Bench

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 International Journal of Innovative Research in Computer Science & Technology (IJIRCST)

indicates that there is no data transmission. When the

II. UART PROTOCOL device wants to start the communication, it pulls the
Generally, there are two types of UARTS one is transmitting line to low in order to notify that the
transmitting UART and other is entering UART and the transmitting transmitter wants to send the data there is a
commerce between these two can be done directly [4, 5, stop bit which is an active high signal which acknowledges
6]. For this, simply two lines are needed to communicate the receiver about the end of transmission. The rate of
between two UARTs. The inflow of data will be from both transmission of data is dependent on the baud rate
the transmitting(Tx) & receiving(Rx) legs of the UARTs. between the UART transmitter and receiver.
In this protocol the Communication from Tx UART to Rx A. Results
UART can be done without timepiece. In UART the data
transmission can be done like a microcontroller, memory, The parameters that are displayed in the output are:
CPU[7]. The entered UART data packet contains three bits  Type of operation being done.
like launch, stop and equality in addition to entered data. It  The data which is being transmitted.
reads the data packet bit by bit and converts the entered  The data present at the transmitter and receiver outputs.
data into the resemblant form to exclude the three bits of  Acknowledgment signals which notify whether the
the data packet. The data packet entered by the UART particular operation is done or not.
transfers in resemblant to the entering end by data
machine. B. Output
 KERNEL: [DRV] : RESET DONE
 KERNEL: [GEN] : oper : write send : 0 TX_DATA :
01011000 RX_IN : 0 TX_OUT : 0 RX_OUT : 00000000
DONE_TX : 0 DONE_RX : 0
 KERNEL: [DRV]: Data Sent : 88
 KERNEL: [MON] : DATA SEND on UART TX 88 #
KERNEL: [SCO] : DRV : 88 MON : 88
 KERNEL: DATA MATCHED
 KERNEL: [GEN] : oper : read send : 0 TX_DATA :
00001010 RX_IN : 0 TX_OUT : 0 RX_OUT : 00000000
Figure 2: UART communication DONE_TX : 0 DONE_RX : 0
 KERNEL: [DRV]: Data RCVD : 98
UART has 10-bit data frame including start and stop bits,  KERNEL: [MON] : DATA RCVD RX 98 # KERNEL:
when the parity is added then data becomes 11 bits. [SCO] : DRV : 98 MON : 98
 KERNEL: DATA MATCHED
 # KERNEL: [GEN] : oper : write send : 0 TX_DATA :
11001110 RX_IN : 0 TX_OUT : 0 RX_OUT : 00000000
DONE_TX : 0 DONE_RX : 0
 KERNEL: [DRV]: Data Sent : 206
 KERNEL: [MON] : DATA SEND on UART TX 206
Figure 3: UART data frame
 KERNEL: [SCO] : DRV : 206 MON : 206 # KERNEL:
DATA MATCHED
Initially the transmitting and receiving lines are high which

Figure 4: Output of UART protocol

III. I2C PROTOCOL communication protocol means that we can attach multiple
IC at a time with the same machine[2]. In the I2C protocol,
I2C is a multi-master and multi-slave periodical the master has control on motorcars and in the case of

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multi-master, only one master will control I2C machine. device with a matched address received from the master,
The data transfer and synchronization between the master responds with a confirmation to the master after which the
and slave is done by timepiece signal. In communication communication is established between both master and
master and slave partake the same timepiece, for slave devices on the data bus.
coetaneous periodical communication. The timepiece Then, the master can transmit 8-bit of data to the receiver
machine is handled by the master but in some conditions which replies with a 1-bit confirmation.
the slave is also suitable to control the timepiece[3].
C. Result
The following parameters are displayed in the Output:
 The type of operation being done.
 The data sent by the master
 The address at which the data is stored
 Read operation is completed or not.
 Acknowledgement signal to know whether a particular
operation is completed or not.
D. Output
Figure 5: I2C communication
 KERNEL: [DRV] : RESET DONE
 KERNEL: [GEN] : WR : 1 WDATA : 76 ADDR : 1
A. I2C Data Frame RDATA : 0 DONE : 0
I2C is an eight- bit communication protocol and an ACK  KERNEL: [DRV] : wr:1 wdata :76 waddr : 1 rdata : x#
or NACK bit associated with each byte. In I2C data is KERNEL: [MON] : DATA WRITE -> wdata :76
transferred in dispatches. Each communication begins with waddr : 1
a launch bit, and the trade ends with a stop bit. Master may  KERNEL: [SCO] : WR : 1 WDATA : 76 ADDR : 1
shoot another launch condition to retain control of the RDATA : 0 DONE : 0
machine. dispatches contain frames of data. Each  KERNEL: [SCO]: DATA STORED -> ADDR : 1DATA
communication has an address frame (slave address), and : 76
one or farther data frames that contain the data being  KERNEL: [GEN] : WR : 0 WDATA : 23 ADDR : 4
transmitted. The communication signal consists of rd/ wr RDATA : 0 DONE : 0
bits, 1 bit ACK/ NACK signal between each data frame.  KERNEL: [DRV] : wr:0 wdata :23 waddr : 4 rdata : 145
See the below Image[8].  KERNEL: [MON] : DATA READ -> waddr : 4 rdata
: 145
 KERNEL: [SCO] : WR : 0 WDATA : 23 ADDR : 4
RDATA : 145 DONE : 0
 KERNEL: [SCO] :DATA READ -> Data Matched #
KERNEL: [GEN] : WR : 0 WDATA : 49 ADDR : 1
RDATA : 0 DONE : 0
Figure 5: I2C data frame  KERNEL: [DRV] : wr:0 wdata :49 waddr : 1 rdata : 76
 KERNEL: [MON] : DATA READ -> waddr : 1 rdata
: 76
B. Process of Data Transmission
 KERNEL: [SCO] : WR : 0 WDATA : 49 ADDR : 1
Slave devices get acknowledged by master with the help RDATA : 76 DONE : 0
of start condition. The data transmission is done by SCL and  KERNEL: [SCO] :DATA READ -> Data Matched
SDL lines. If address matches the target device gets
selected and other slaves get disconnected. The slave

Figure 6: I2C waveforms

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[7] M. R. L. P. M. M. “Design and Implementation of UART”.

IV. COMPARISION BETWEEN UART AND I2C International Journal on Recent and Innovation Trends in
Computing and Communication, vol. 3, no. 6,June 2015, pp.
UART I2C
4289-91, doi:10.17762/ijritcc.v3i6.4638.
peer to peer topology Master-slave method is
[8] Frederic Leens, An Introduction to I2C and SPI Protocols,
is used used
IEEE Instrumentation and Measurement magazine February
Multiple devices can be
only a single device canbe 2009.“Implementing I2C Communication Protocol in
connected to a single
connected LABVIEW FPGA”, http:/ / www.ni.com. Samir Palnitkar,
master
Verilog HDL - A guide.
The amount of data to be The amount of data that canbe [9] Comparison of VHDL, Verilog and System Verilog, by
transferred is dependent transferred by the master Stephen Bailey, www.model.com C. H. Roth, “Digital
on baud rate. is 400kbps. System Design Using VHDL", PWS
it is used for high speed it is used for low speed [10] Publishing Company, 2008.
devices devices [11] System Verilog Verification guide
the address allocation and the write operation is doneonly (https://verificationguide.com/systemverilog/systemveril
write operation takes place after the acknowledgement of og-tutorial/)
simultaneously address allocation
ABOUT THE AUTHORS
V. CONCLUSION
Dr. Ch. Manohar Kumar was
The UART and I2C protocols are designed using System born in 23-08-1987. He received his
Verilog. The reset, write and read operations of the two B. Tech (ECE) degree from St.
protocols are verified and both the protocols are compared Ann’s College of Engineering and
with each other based on the parameters such as the Technology Chirala, AP, India in
topology used, design specifications and data processing. 2008. He received his M. Tech from
Andhra University, Visakhapatnam,
AP, in the field of Radar And
VI. ABBREVIATIONS Microwave engineering in 2013.He
VLSI: Very Large-Scale Integration UART: Universal received Ph.D. In the field of
metamaterial Antennas,
Asynchronous Receiver and Transmitter I2C: Inter
Department of School of
Integrated Circuit. Engineering, Career Point
University, KOTA, Rajasthan
CONFLICTS OF INTEREST (2022). Currently, he is working as
Assistant Professor in ECE dept.,
The authors declare that they have no conflicts of interest. Gayatri vidya Parishad college for
Degree and PG Courses(A),
REFERENCES Visakhapatnam, AP. His research
fields include Metamaterial
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using System Verilog, International Journal of Engineering MIMOAntennas.
and Advanced Technology (IJEAT)ISSN: 2249 – 8958
(Online), Volume-9 Issue-5, June 2020 Guduru Mahesh Babu was born in
[2] Lakshmi Manasa Kappaganthu, Durga Prakash M, Avinash 15-11-2001. He was Studying B.
Yadlapati, I2C Protocol and its Clock Stretching Tech (ECE) in Gayatri vidya
Verification using System Verilog and UVM,International Parishad college for Degreeand PG
Conference on Inventive Communication and Courses(A), Visakhapatnam,
Computational Technologies, (ICICCT 2017) AP.,India
[3] R. K. Megalingam, J. M. Varghese and S. A. Anil, "Distance
estimation and direction finding using I2Cprotocol for an A. Hemanth Chakradhar was born
auto-navigation platform," 2016 International Conference in 01-08-2002. He was Studying B.
Tech (ECE) in Gayatri vidya
on VLSI Systems, Architectures, Technology and
Parishad college for Degreeand PG
Applications (VLSI- SATA), Bengaluru, India, 2016, pp. 1-
4, doi: 10.1109/VLSI-SATA.2016.7593061. Courses(A), Visakhapatnam, AP.,
India
[4] U. Nanda and S. K. Patnaik, "Universal Asynchronous
Receiver and Transmitter (UART)," 2016 3rd International A. Satya Krishna Pranav was born
Conference on Advanced Computing and Communication in 11-03-2002. He was Studying B.
Systems (ICACCS), Coimbatore, India,2016, pp. 1-5, doi: Tech (ECE) in Gayatri vidya
10.1109/ICACCS.2016.7586376. Parishad college for Degreeand PG
[5] Vibhu Chinmay, Shubham Sachdeva, “A Review Paperon Courses(A), Visakhapatnam, AP.,
Design and Simulation of UART for Serial India
Communication,”2014 IJIRT, Volume 1 Issue 6, SSN :
2349-6002. Duvvada Sudheer was born in 21-
[6] Bidisha Kashyap and V Ravi, “Universal Verification 03-2002. He was Studying B. Tech
Methodology Based Verification of UART Protocol”, (ECE) in Gayatri vidya Parishad
Published under licence by IOP Publishing Ltd. Journal of college for Degree and PG
Physics: Conference Series, Volume 1716, National Courses(A), Visakhapatnam, AP.,
Science, Engineering and Technology Conference India
(NCSET)2020,11-12 May 2020, Vellore Institute of
Technology, Chennai, India. Citation Bidisha Kashyap and
V Ravi 2020 J. Phys.: Conf. Ser. 1716 012040, DOI
10.1088/1742-6596/1716/1/012040

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