Question bank 2

Module 2 and 3
1) A computer uses a memory unit with 2561K words of 32 bits each. A binary instruction code
is stored in one word oi memory. The instruction has four parts: an indirect bit, an operation
code, a register code part to specify one of 64 registers, and an address part.
a. How many bits are there in the operation code, the register code part, and the
address part?
b. Draw the instruction word format and indicate the number of bits in each part.
c. How many bits are there in the data and address inputs oi the memory?
2) Give flow chart and microoperations to explain instruction cycle.
3) A computer uses a memory of 65,536 words with eight bits in each word. It has the
following registers: PC, AR, TR (16 bits each), and AC, DR, IR (eight bits each). A memory-
reference instruction consists of three words: an 8-bit operation-code (one word) and a 16-
bit address (in the next two words). All operands are eight bits. There is no indirect bit.
a. Draw a block diagram of the computer showing the memory and registers. (Do not
use a common bus).
b. Draw a diagram showing the placement in memory of a typical three-word
instruction and the corresponding 8-bit operand.
c. List the sequence of microoperations for fetching a memory reference instruction
and then placing the operand in DR. Start from timing signal To.
4) Give example to explain a subroutine with the help of block diagram.
5) Explain interrupt cycle with the help of flow chart. Give example to demonstrate the
interrupt cycle.
6) Write a subroutine to subtract two numbers. In the calling program, the BSA instruction is
followed by the subtrahend and minuend. The difference is returned to the main program in
the third location following the BSA instruction.
7) Define: (a) micro operation; (b) micro instruction; (c) micro program (d) microcode.
8) Give block diagram of bus organization for seven CPU registers. Explain control word.
9) Specify the control word that must be applied to the processor to implement the following
microoperations.
a. R 1 <-- R2 + R3
b. R4 <--R4
c. RS <-- RS - 1
d. R6 <-- shl R1
 e. R7 <-- input
10) A stack is organized such that SP always points at the next empty location on the stack. This
means that SP can be initialized to 4000 in and the first item in the stack is stored in location
4000. List the microoperations for the push and pop operations.
11) Convert the following arithmetic expressions from infix to reverse Polish notation.
a. A•B + C•D + E•F
b. A • B + A • (B • D + C • E)
c. A+ B•[C•D + E•(F + G)]
d A•[B+C • (D+E)] . f•(G + H)
12) Convert the following arithmetic expressions from reverse Polish notation to infix notation.
a. A B C D E + • - I
b. ABC D E•l - +
c. A B C•l D-E F I +
d. ABCDEF G+•+•+•
13) A first-in1 first-out (FIFO) has a memory organization that stores information in such a
manner that the item that is stored first is the first item that is retrieved. Show how a FIFO
memory operates with three counters. A write counter WC holds the address for writing into
memory. A read counter RC holds the address for reading from memory. An available
storage counter ASC indicates the number of words stored in FIFO. ASC is incremented for
every word stored and decremented for every item that is retrieved.
14) A two-word instruction is stored in memory at an address designated by the symbol W. The
address field of the instruction (stored at W + 1) is designated by the symbol Y. The operand
used during the execution of the instruction is stored at an address symbolized by Z. An
index register contains the value X. State how Z is calculated from the other addresses if the
addressing mode of the instruction is a. direct b. indirect c. relative d. indexed.
15) An instruction is stored at location 300 with its address field at location 301 . The address
field has the value 400. A processor register R 1 contains the number 200. Evaluate the
effective address if the addressing mode of the instruction is (a) direct; (b) immediate; (c)
relative; (d) register indirect; (e) index with R1 as the index register.