caDepartment of Electrical & Electronic Engineering

Bangladesh University of Engineering & Technology

EEE468 VLSI Laboratory

Laboratory Module 3
ASIC Front End Design: RTL design of a digital sub-system and System level
validation using CADENCE IUS

Synthesis with Cadence Genus(TM) Synthesis Solution

Objectives:
In the previous experiment, we have seen how a behavioral code and test bench can be used to see
output waveforms of a design. Electronic design automation (EDA) tools need Netlist to start ASIC
design flow. A netlist is a description of the connectivity of an electronic circuit which provides
nothing more than instances, nets, IO ports and perhaps some attributes. In digital circuit design,
Register-Transfer Level (RTL) is a design abstraction which models a synchronous digital circuit in
terms of the flow of digital signals (data) between hardware registers, and the logical operations
performed on those signals. RTL Logic synthesis is a process by which an abstract form of desired
circuit behavior, typically at Register Transfer Level (RTL), is turned into a design implementation
in terms of logic gates, typically by a computer program called a synthesis tool.

In this experiment, we will use Cadence Genus(TM) Synthesis Solution as a synthesis tool.

Lab 3-1.Setting up the working directory.

(1) Create a separate directory for the synthesis of the design. For this lab you will create a
directory lab3_synth under the directory /home/<group_name>/cds_digital

In the synthesis directory you will need to copy the following files from
/home/cad/VLSI2Lab/Digital/RTL_synthesis directory,

1. alu.v your behavioural code form alu.

2. alu.tcl A script to convert behavioural code to synthesized netlist (structural code)
3. alu.sdc  A synopsys design constraints file

Besides, copy home/cad/VLSI2Lab/Digital/library folder under /home/<group_name>/ directory.

cp -rf /home/cad/VLSI2Lab/Digital/library ./
In the directory, we will basically use two types of library files,
Liberty file (.lib): Liberty Files are a IEEE Standard for defining following characteristics of a cell,
 PVT (Process, Voltage, Temperature) Characterization

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  Relating Input and Output Characteristics
 Timing
 Power
 Noise
Library exchange file (.lef): A LEF file contains the following sections:
 Technology: layer, design rules, via definitions, metal capacitance
 Site: Site extension
 Macros: cell descriptions, cell dimensions, layout of pins and blockages, capacitances.

From the library folder, we will use the following files,

File Name Uses
slow_vdd1v0_basicCells.lib Standard cell library for slow corner operation (setup check)
fast_vdd1v0_basicCells.lib Standard cell library for fast corner operation (hold check)
gsclib045_tech.lef Process technology .lef file for 45nm tech node
gsclib045_macro.lef Standard cell physical information for 45nm tech node

Please do not use this library outside the VLSI lab. Now browse the above four files to get a
clear view of their contents.

For details of ASIC Library read the GSCLIB045_user_guide available for download in the same
folder. The standard cell referred to in this tech guide are provided by Cadence.

Lab 3-2 Logic Synthesis using Cadence Genus(TM) Synthesis Solution

First we need to modify rtl.tcl file according to our design environment. Now to start RTL
Compiler follow below steps
1. cd lab3_RTL_synthesis/

2. gedit alu.tcl
3. csh ; #this command will invoke machine to run synthesis tool

4. genus -legacy_ui ; # this command will invoke cadence genus synthesis license in

legacy mode
5. source alu.tcl ; # this will generate a synthesized netlist named accu_synth.vgen

which we will use for ASIC flow in the next experiment

6. gui_show; # a window like following will be popped up

7. Now from left side of the window follow following steps-

Hierarchy>accu (right click)> open in> Schematic Viewer (main)

Now the window will be appeared like this-

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 8. Now explore the File>Report tab from the window (upper left corner)

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 9. Now explore the Power>Report>Detailed Report tab from the window (upper left

corner) and examine the various power dissipation of the circuit.

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Finally, you can close the GUI by going to File -> Exit and you can now analyze the result of the
synthesis in the file accu_synth.v that you can use for simulating the netlist and for subsequent
place and route using Cadence Innovus.

Lab 3-4 Verification of the Synthesised logic using Cadence IUS

Now that your design have been synthesised you will get the structural verilog description of your
design in the file accu_synth.v generated by the Cadence Genus(TM) Synthesis Solution.
Now simulate the netlist file alu_synth.v using Cadence Incisive Unified Simulator (IUS) as done
in Lab 1 and Lab 2 and compare the two results.

Report:
1. Provide the circuit diagram and performance curves of the circuits as obtained after synthesis.
2. Compare in a table the design specifications with the simulated specifications after synthesis.
3. Discuss about the discrepancy between the design specifications and the simulated
specifications after synthesis.
4. Now synthesis your assigned project and create the verilog structural description of your
design.

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