Second Edition

MICROPROCESSORS
and
MICROCOMPUTER·BASED
SYSTEM DESIGN
MOHAMED RAFIQUZZAMAN, PH.D.
Professor
California State Polytechnic l Tniversity
Pomona, California
and
Adjunct Professor
Univers ity of Southe rn Califo rnia
Los Angeles , California

CRC Press
Boca Raton New York London Tokyo
Library of Congress Cataloging-in-Publication Data

Rafiquzzaman, Mohamed.
Microprocessors and microcomputer-based system design I Mohamed RaJiquzzaman.- 2nd ed.
p. em.
Includes bibliographical references and index.
ISBN 0-8493-4475-1
I. Microprocessors . 2. Intel 80xx series microprocessors. 3. Motorola 68000 series microprocessors.
4. Microcomputers. I. Title.
QA 76 5 R27848 1995
004. 16--dc20 95-7374
CIP

This book contains information obtained from authentic and highly regarded sources. Reprinted material is quoted
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© 1995 by CRC Press, Inc.

No claim to original U.S. Government works

International Standard Book Number 0-84Q3-4475-I
Library of Congress Card Number 95-7374
Preface

This book is based on the fundamental concepts associated with typical 8-, 16-, and 32-bit
microprocessors and microcomputers. These concepts are related in detail to the Intel 8085/
8086/80386/80486/80960 and Motorola 68000/68020/68030/88100. A brief coverage of Intel
Pentium, Motorola 68040, Motorola/IBM/Apple PowerPC, and DEC's Alpha is also included.
With the growing popularity of both Intel and Motorola 32-bit microprocessors, it is now
necessary to cover these processors at the undergraduate and graduate levels. Therefore, a
thorough coverage of these processors is provided.
A detailed treatment of Intel 80386 and Motorola 68020/68030 along with more examples
and system design concepts is included. Programming and system design concepts associated
with other popular 32-bit microprocessors such as Intel80486/80960 and Motorola 68040 are
also covered in this book. Finally, an overview of Intel Pentium microprocessor is provided.
Since the fundamental concept of 8-bit microprocessors, along with the Intel8085, has proved
its worth many times over in the intervening years, the 8085 has been retained in this edition.
This book is divided into ten chapters. Chapter 1 contains the basics of microprocessors, as
in the first edition. New topics such as floating-point arithmetic, Program Array Logic (PAL)
used for address decoding for 32-bit microprocessors, flash memories and an overview of
various 32-bit microprocessors is also included.
Chapter 2 covers details of the 8085 microprocessor.
Chapters 3 through 8 provide detailed descriptions of the architectures, addressing modes,
instruction sets, 1/0 and system design concepts of Intel's 8086, 80386, 80486, and 80960 and
Motorola's 68000, 68020, 68030, 68040, and 88100 microprocessors. An overview of Intel
80186, 80286, Pentium and PowerPC microprocessors are also included.
Chapter 9 contains fundamentals of peripheral interfacing.
Chapter 10 includes system design concepts along with the applications of design principles
covered in the preceding chapters. Three system design examples using the 8085, 8086, and
68000 are included in detail.
The appendices include materials on the HP 64000 microcomputer development systems,
data sheets on various microprocessors and support chips, and a glossary.
The audience of this book can be college students or practicing microprocessor system
designers in the industry. It can be used as an undergraduate or graduate text in electrical
engineering, computer engineering or computer science. Practitioners of microprocessor
system design in the industry will find greater detail and comparison considerations than are
found in manufacturers' manuals. The book assumes a familiarity with digital logic and topics
such as Boolean Algebra and K-maps.
The author wishes to express his sincere appreciation to his student Frank Lee for making
constructive suggestions and typing the manuscript. The author is also grateful to Dr. W .C.
Miller of University of Windsor, Canada, and others for their support throughout the writing
effort.

Mohamed Rafiquzzaman
Pomona, California
The Author

Mohamed Rafiquzzaman obtained his Ph.D. in Electrical Engineering in Canada in 1974. He

worked for Esso/Exxon and BeU Northern Research for approximately 5 years. Dr. Rafiquzzaman
is presently a professor of eledrical and computer engineering at California State Polytechnic
University, Pomona. He was Chair of the department there from 1984 to 1985. Dr. Rafiquzzaman
is also an adjunct professor of electrical engineering systems at the University of Southern
California, Los Angeles. He consulted for ARCO, Rockwell, Los Angeles County, and Parsons
Corporation in the areas of computer applications. He has published six books on computers,
which have been translated into Russian, Chinese and Spanish, and has published numerous
papers on computers.
Dr. Rafiquzzaman is the founder ofRafi Systems, Inc. a manufadurer ofbiomedical devices
and computer systems consulting firm in California. In 1984, he managed the Olympic
Swimming, Diving and Synchronized Swimming teams. He has also managed Swiss timing,
scorekeeping, and computer systems.
From 1984 to 1989, he was the instructor for Motorola in Southern California teaching
short courses on 68000, 68020, and 68030 for local industries.
Dr. Rafiquzzaman was an advisor to the President of Bangladesh o n computers from 1988
to 1990. He is currently involved in research activities in both hardware and software aspects
of typical 16- and 32-bit microprocessor-based applications. These activities include image
processing, robotics control, and OCR (Optical Character Recognition) .
 To my parents,
my wife Kusum, son Tito,
and brother Elan

In memory of my brother, Dr. M. Kaisaruzzaman

Table of Contents

Chapter I Introduction to Microprocessors and Microcomputer-Based Applications

1.1 Evolution of the Microprocessor .......................................... ................ .. .. ....... 2
1.2 Microprocesso r Data Types .................................................. ...... ............... ...... 3
1.2.1 Unsigned and Signed Binary Integers .............................................. 3
1.2.2 BCD (Binary Coded Decimal) Numbers ......................................... 3
1.2.3 ASCII ...................................................................................... ...... ...... 4
1.2.4 Floating-Point Numbers ........................................................ ........... 4
1.3 Microcomputer Hardware ................. ................................................... ........... 6
1.3.1 The System Bus ............ .. ...................... .... .... .. .................. .......... ........ 6
1.3.2 The Microprocessor ........................................ .................................. . 7
1.3.3 Memory Organization ................................................. .................... 10
1.3 .3.a Introduction ...... ............................ .... ............................ . 10
1.3.3.b Main Memory Array Design .. ....................................... 13
1..3.3.c Memory Management Concepts ................................... 17
1.3.3.d Cache Memory Organization ........................................ 22
!.3.4 Input/O utput (1/0) .............. .............. .......... ............ .................. ..... 24
I .3.4 .a Programmed 1/0 .............................................. .... .. ........ 25
1.3.4 .b Standard l/0 Versus Memory-Mapped l/0 ................ 26
1.3.4 .c Unconditional and Conditional Programmed 1/0 .. ... 27
I .3 .4 .d Typical Microcomputer Output Circuit ............ .......... 27
1.3.4.e Interrupt Driven 1/0 ...................................................... 29
l.3.4.f Direct Memory Access (DMA) ...................... .... ........... 31
l.3.4.g Summary of Microcomputer 1/0 Methods ................. 32
1.3 .4 .h Coprocessors .............................................................. ..... 32
1.4 Microcomputer System Software and Programming Concepts ............ ..... 34
1.4. J System Software .......................................................................... ..... 34
1.4.2 Programming Concepts ........................................................... ....... 35
l.4 .2.a Assembly Language Programming ............................... 35
1.4.2 .b High-Level Language Programming ............................. 35
1.4.2.c Which Programming Language to Choose? ................ 36
1.5 Typical Microcomputer Addressing Modes and Instructions .................... 36
1.5. 1 Introduction ................................ .. .......... ...... .. ............ .... ................. 36
1.5.2 Addressing Modes ........................ .... .. .. .......... .......................... .... ... 36
1.5 .3 Instruction Types ................................................ ............... ... .. .. ....... 37
1.6 Basic Features of Microcomputer Development Systems ........................... 38
1.7 System Development Flowchart .................................................................... 44
1.7.1 Software Development .................................................................... 44
1.7.2 Hardware Development ......................................................... ........ . 46
1.8 Typical Microprocessors .. ................ ......................................................... ..... 46
1.9 Typical Practical Applications ............................................................ ........... 4 7
1.9.1 Personal Workstations .................................................................... 47
1.9.2 Fault-Tolerant Systems ........................... .. ....................................... 47
1.9.3 Real-Time Controllers ..................................................................... 49
1.9.4 Robotics ........... ............................................ .......... .. ....... ... .. .. .... ....... 49
1.9.5 Embedded Control .......................... ............................................ .... 49
Questions and Problems ..... ........... ........................................................... .. ... ...... ......... ... 50
Chapter 2 Intel 8085
2.1 Introduction .................................................................................................... 53
2.2 Register Architecture ......................................................... ............................. 53
2.3 Memory Addressing ....................................................... ....... ......................... 55
2.4 8085 Addressing Modes .................................. .......................... ..................... 56
2.5 8085 Instruction Set .. ....................................... ... ................. ..... .... ................. 57
2.6 Timing Methods ............ .................................................. ............. ..... .. .. ......... 75
2.7 8085 Pins and Signals .................... .................... ............................................. 77
2.8 8085 Instruction Timing and Execution ........... .......................... .................. 81
2.8.1 Basic System Timing ........................................................... .......... .. 82
2.8.2 8085 Memory READ (IO/M = 0, RD = 0) and
1/0 READ (10/M = I, RD = 0) ....... ............... .. ..... ...... .................. 82
2.8.3 8085 Memory WRITE (10/M = 0, WR = O) and
1/0 WRITE (10/M = 1, WR = 0) .................................................. 84
2.9 8085 Input/Output (1/0) ............................................................................... 84
2.9.1 8085 Programmed I/0 .................................................................... 84
2.9.1.a 8355/8755 1/0 Ports ....................................................... 86
2.9.1.b 8155/8156 I/0 Ports ........................................... ............ 88
2.9.2 8085 Interrupt System ..................................................................... 93
2.9.3 8085 DMA .............................................. .... ...................................... 97
2.9.4 8085 SID and SOD Lines .......................... ...................................... 98
2. 10 8085- Based System Design .......................... ................................................. 103
Questions and Problems .................................. .... .. .......... ......... ..................................... I OS

Chapter 3 Intel 8086

3.1 Introduction .............. .. .......................... ..... ...... ....... ...................................... Ill
3.2 8086 Architecture .......................................................................................... 113
3.3 8086 Addressing Modes .............. .......................................... .......... ...... ....... 117
3.3.1 Addressing Modes for Accessing Immediate and
Register Data (Register and Immediate Modes) ......................... 117
3.3.l.a Register Addressing Mode .. ......................................... 117
3.3.l.b Immediate Addressing Mode ...................................... 117
3.3.2 Addressing Modes for Accessing Data in Memory
(Memory Modes) .............................................................. ............. 117
3.3.2.a Direct Addressing Mode .................. ............................ 118
3.3.2.b Register Indirect Addressing Mode ............................ 118
3.3.2.c Based Addressing Mode .......... ............ ......................... 118
3.3.2.d Indexed Addressing Mode ................ ........................... 120
3.3.2.e Based Indexed Addressing Mode ................................ 121
3.3.2.f String Addressing Mode .. ................ ............................ 121
3.3.3 Addressing Modes for Accessing 1/0 Ports (110 Modes) .......... 122
3.3.4 Relative Addressing Mode ............................................................. 123
3.3.5 Implied Addressing Mode .................. .......................... ................. 123
3.4 8086 Instruction Set .......... ........................................................................... 123
3.5 8086 Assembler-Dependent Instructions .......... ................ .... .... .................. 140
3.6 ASM-86 Assembler Directives ............................................ .......... ............... 140
3.6.1 SEGMENT and ENDS Directives ......................................... ........ 141
3.6.2 Assume Directive .... ................ .............................. ...... .. .......... .. ..... 141
3.6.3 DUP Directive ................................................................................ 142
 3.7 System Design Using the 8086 ................................... .................. ............... 155
3.7.1 Pins and SignaJs ......................... .............. ........... .............. ....... ...... 155
3.7.2 8086 Basic System Concepts .......................... ... ..... ....................... 160
3.7.2.a 8086 Bus Cycle .................................... .. ....................... 160
3.7.2.b 8086 Address and Data Bus Concepts .......... .............. 161
3.7.3 Interfacing with Memories .............. .............. ............ .................... 163
3.7. 3.a ROM and EPROM ..... .............................. .................... 163
3.7.3.b Static RAMs ...................................... ............. ............... 164
3.7.3.c Dynamic RAMs ..................... .. .. ... ... .... ... .. .................... 164
3.7.4 8086 Programmed 110 ........ .......................................................... 164
3.8 8086-Based Microcomputer .................................................................... ..... 165
3.9 8086 Interrupt System .......... ..... ...................... ...... ....... ......... ... .......... .......... 173
3.9.1 Predefined Interrupts (0 to 4) ........... ......... ......... ......................... 174
3.9.2 User-Defined Software Interrupts ... .......... ..... ..... ......................... 175
3.9.3 User-Defined Hardware (Maskable Interrupts,
Type Codes 32 10 - 255 10 ) ••••• • • . .•••••••••••••••• •• • • ••••••••••••• • •• • •••• • ••• • • •••• 175
3. 10 8086 DMA .............................................. ........ ..... ............ .............................. 181
Questions and Problems ................................... .... ............................... ......... .... ........... .. 181

Chapter 4 Intel 80186/80286/80386

4.1 Intel 80186 and 80286 ............................. ..................................................... 187
4.1.1 Intel80186 ................................................ ...................................... 187
4. I .2 Intel 80286 ................................................... ........... ............. ........... 192
4.1.2.a 80286 Memory Management .................... ...... ........ .... 195
4. 1.2.b Protection ................ .................................. ................... 198
4.1 .2.c 80286 Exceptions ....... ........................................ ........... 204
4.2 Intel 80386 ........... ............................... ................................ ............... ..... .... ... 204
4.2.1 Basic 80386 Programming Model ................. ............ ........... ........ 206
4.2. 1.a Memory Organization and Segmentatio n .................. 208
4.2.1.b Data Types ............................................ .......... .............. 208
4.2. 1.c 80386 Registers .............................. ..... .... .... ........... ....... 208
4.2. l.d 80386 Addressing Modes ............................................. 211
4.2.2 80386 Instruction Set ........... .. ... ... .... ..... .. .............. .................... .... 213
4.2.2.a Arithmetic Instructions ....................................... ..... ... 22 1
4.2.2.b Bit Manipulation Instructions .............. ... ...... ........ ...... 221
4.2.2.c Byte-Set-On Condition Instruction s ............. ........ ..... 223
4.2.2.d Conditional Jumps and Loops ... ............... ..... ............. 223
4.2.2.e Data Transfer ................................ ............. ................... 224
4.2.2.f Flag Control ................................................... .... ........... 225
4.2.2.g Logical .................................... ........................ ............ ... 225
4.2.2.h String ....................................... ..... ...... ................ ........... 226
4.2.2.i Table Look-Up Translation Instruction ..................... 227
4.2.2.j High-Level Language Instructions .......... ........ ............ 227
4.2.3 Memory Organization ................................ .......... ..... .. .................. 234
4.2.4 1/0 Space .................................................. ................ ....... ..... .......... 235
4.2.5 80386 Interrupts .............................. .............. .......... ......... ............. 235
4.2 .6 80386 Reset and Initialization .............. ....... ...................... ........... 237
4.2 .7 Testabi.lity ......................................................... ....... ............. .......... 238
4.2.8 Debugging ..... ................... ............................... ............................... 238
4.2.9 80386 Pins and Signals ......................... ......................................... 238
4.2.1 0 80386 Bus Transfer Technique ..... .. .... ... .. ... ........... .... ................... 244
 4.2.11 80386 Read and Write Cycles ....................................................... 244
4.2.12 80386 Modes .................................................................................. 246
4.2.12.a 80386 Real Mode .......................................................... 246
4.2.12.b Protected Mode ............................................................ 247
4.2.1 2.c Virtual 8086 Mode ....................................................... 25 1
4.3 80386 System Design .................................................................................... 25 1
4.3.1 80386 Memory Interface ............................................................... 253
4.3.2 80386 I/0 ························································································ 257
4.4 Coprocessor Interface ................................................................................... 264
4.4.1 Coprocessor Hardware Concepts ................................................. 264
4.4 .2 Coprocessor Registers .................................................................... 267
4.4.3 80387 Instructions ......................................................................... 269
Questions and Problem s ................................................................................................ 272

Chapter 5 Motorola MC68000

5.1 Introduction .................................................................................................. 277
5.2 68000 Programming Model ......................................................................... 278
5.3 68000 Addressing Structure ......................................................................... 280
5.4 68000 Addressing Modes ............................................................................. 28 1
5.4. 1 Register Direct Addressing ............................................................ 282
5.4.2 Address Register Indirect Addressing .......................................... 282
5.4.3 Absolute Add ressing ...................................................................... 283
5.4.4 Program Counter Relative Add ressing ........................................ 284
5.4.5 Immediate Data Addressi ng Mode .............................................. 284
5.4.6 Implied Addressing ........................................................................ 284
5.5 68000 Instructio n Set ................................................................................... 285
5.5. 1 Data Movement Instructions ........................................................ 291
5.5.l.a MOVE Instructio ns ...................................................... 291
5.5.l.b EXG and SWAP Instructions ...................................... 292
5.5.l.c LEA and PEA Instructions .......................................... 293
5.5.l.d LI N K and UNLK Instructions .................................... 293
5.5.2 Arithmetic Instructions ................................................................. 294
5.5.2.a Additio n and Subtraction Instructions ...................... 294
5.5.2.b Mult iplication and Division Instructions ................... 294
5.5.2.c Compare, Clear, and Negate Instructions .................. 296
5.5.2.d Extend ed Arithmetic Instructio ns ............................... 296
5.5.2.e Test Instructions ........................................................... 297
5.5.2.f Test and Set Instructio n .............................................. 297
5.5.3 Logical Instructio ns ....................................................................... 298
5.5.4 Shift and Rotate Instructions ........................................................ 298
5.5.5 Bit Manipulation Instructions ...................................................... 300
5.5.6 Binary-Coded Decimal Instructions ............................................ 301
5.5.7 Program Cont rol Instructions ...................................................... 301
5.5.8 System Control Instructions ......................................................... 305
5.6 68000 Stacks .................................................................................................. 307
5.7 68000 Pins and Signals ................................................................................. 314
5.7.1 Synchronous and Asynchronous Control Lines ......................... 3 15
5.7.2 System Cont rol Lines .................................................................... 318
5.7.3 Interru pt Control Lines ................................................................. 323
5.7.4 DMA Control Lines ....................................................................... 323
5.7.5 Status Lines .................................................................................... 323
 5.8 68000 System Diagram .................................. ............................. ..... ... ... ....... 324
5.9 Timing Diagrams .......................................... ..... ... ... ...... .... ........................... 324
5.10 68000 Memory Interface ...... ................ ........ ...... ... .............. ......................... 326
5.11 68000 Programmed I/0 ........................ .. .......................................... .. ... ...... 329
5.11.1 68000-68230 Interface .............. ............ ....................................... .. 329
5.11.2 Motorola 68000-6821 Interface .................................................... 333
5.12 68000/2716/6116/6821-Based Microcomputer .. ......................................... 335
5.13 68000 Interrupt 110 .. ................. ....... .... ..... .. ....... ... ..................... ... ........ ....... 341
5. 13. 1 External Interrupts ......... ..... .......... ................ ........... ....... .... ....... ... 341
5.13 .2 Internal Interrupts .. ......... .............................. ......................... ....... 343
5.13.3 68000 Exception Map ........ .... .. ............ ......... ............................... .. 343
5.13.4 68000 Interrupt Address Vector ................................................... 344
5.13.5 An Example of Autovector and Nonautovector Interrupts ....... 344
5.14 68000 DMA .......................................................................................... ......... 344
5.15 68000 Exception Handling ........................ .................................... ....... .. ...... 345
5.16 Multiprocessing with the 68000 Using theTAS Instruction and
AS (Address Strobe) Signal .......................................................................... 347
Questions and Problems ....... ......... .... ...... ........... ... ... ....................................... .... .. .... .... 351

Chapter 6 Motorola MC68020

6.1 Introduction .. .. ................................................................................ ... ........... 359
6.2 Programming Model ................. ........... ...... .................................... ..... ..... .... 362
6.3 Data Types, Organization, and CPU Space Cycle ...................... .. ..... ......... 362
6.4 MC68020 Addressing Modes ...................... ............................... ......... ......... 364
6.4.1 Address Register Indirect (ARJ) with Index and
8-Bit Displacement .... ..... ..... ................. .... .............. .... ...... ... .... .. .... 364
6.4 .2 ARJ with Index (Base Displacement, bd: Value 0 or
16 Bits or 32 Bits) ................ .... ... ............ .................. ...... ... ... ......... 368
6.4.3 Memory Indirect ................. ............................................. .............. 368
6.4.4 Memory Indirect with PC ... .. ................. ........ .. ... ............. ....... .... .. 369
6.4.4.a PC Indirect with Index (8-Bit Displacement) ...... ..... 369
6.4.4.b PC Indirect with Index (Base Displacement) ............ 369
6.4.4.c PC Indirect (Postindexed) ................................. .......... 370
6.4.4.d PC Indirect (Preindexed) ................................ .... ........ 370
6.5 68020 Instructions ...................................... ..................... ..... .. ..................... 372
6.5.1 New Privileged Move Instru ction ................................................ 373
6.5.2 Return and Delocate Instruction .............. .............................. ..... . 375
6.5.3 CHK/CHK2 and CMP/CMP2 Instructions .. ..................... .......... 375
6.5.4 Trap On Condition Instructions .. ............. .. ........................ ......... 379
6.5.5 Bit Field Instructions ................. ......... .......................... ...... ........... 380
6.5.6 Pack and Unpack Instructions ....................................... .... .. ........ 383
6.5.7 Multiplication and Division Instructions ...................... .... ... ....... 385
6.5.8 MC68000 Enhanced Instructions ......................................... ........ 388
6.6 68020 Advanced Instructions ......... ... ............... ................................... ........ 390
6.6.1 Breakpoint Instruction .. ............... ..... ............................................ 390
6.6.2 CaU Module/Return from Module Instructions .............. ...... ..... 394
6.6.3 CAS lnstuctions ........................................... ......... ...... .. ................. 395
6.6.4 Coprocessor Instructions ... ... .......................... .......... ........... ......... 400
6.7 MC68020 Cache/Pipelined Architecture and Operation .. ............. ...... ..... . 402
6.8 MC68020 Virtual Memory .......... .. ......................................... ................ ..... 405
6.9 MC68020 Coprocessor Interface ......................................... ........... .......... ... 406
 6.9.1
MC6888l Floating-Point Coprocessor ................................... ..... 408
6.9.l.a 68881 Data Movement Instructions ......... .................. 412
6.9.1.b Monadic ....................................................................... . 413
6.9.1.c Dyadic Instructions .......................... .......... ............. ..... 414
6.9 .1.d BRANCH, Set, or Trap-On Condition ..... ... ............... 415
6.9.l.e Miscellaneous Instructions .......................... ............ .... 4 I 6
6.9.2 MC68851 MMU ............................................................................ 420
6. 10 MC68020 Pins and Signals ............... ....... ... ............................................. .. .. 422
6.11 MC68020 Timing Diagrams .. ........................ ................. ... .......................... 436
6.12 Exception Processing ............. ...... .......................................... ... ........... ..... .... 44 I
6.13 MC68020 System Design .......... ... ..................... ........................................... 446
Questions and Problen1s .......................... ...................................................................... 453

Chapter 7 Motorola MC68030/MC68040, Intel 80486 and Pentium Microprocessors

7.1 Motorola MC68030 ............ ..... ... .................................................................. 461
7 .I .I M C68030 Block Diagram ........................................ ...................... 461
7.1.2 MC68030 Programming Model ............................... ................ .... 462
7.1.3 MC68030 Data Types, Addressing Modes, and Instructions ..... 463
7.1.3.a PMOVE Rn, (EA) or ( EA) , Rn .......... ............. .... .. ...... 464
7. I .3.b PTEST .............. ... ................ ............... ...................... ..... 464
7. I .3.c PLOAD ..... .. ....... .......................................... ....... ........... 465
7. I .3.d PFLUSH .. ...... ....... .... ... ......... ................ ......................... 466
7. 1.4 MC68030 Cache .................... ...... .................... .................... ......... .. 466
7.1.5 68030 Pins and Signals ........... .......... ............... .............................. 470
7.1.6 MC68030 Read and Write Timing Diagrams ............................. 47 1
7.1.7 MC68030 On- C hip Memory Management Unit ........... ........... .. 476
7.1.7.a MM U Basics ............ ..................................................... 476
7.1.7.b 68030 On-chip MMU ................ .................................. 480
7.2 MC68040 .................................. ......................... ......................................... .. . 491
7.2.1 Introduction .................... ........... ................ ........................... ....... .. 49 1
7.2.2 Register Architecture/ Address ing Modes ..... .......... .. ......... .. ...... ... 49 1
7.2.3 Instruction Set/Data Types .... ............ ..................................... .... .. 493
7.2.4 68040 Processor Block Diagram .............................. ........ ....... ...... 498
7.2.5 68040 Memory Management .... .......... ..................... ..................... 499
7.2. 6 Discussion and Conclusion ................ ...... .............................. .... ... 50 I
7.3 Intel 80486 Microprocessor .............. ................................ ....................... .... 50 1
7.3 .1 Intel 80486/80386 Comparison .................................................... 50 I
7.3.2 Special Features of the 80486 ........................................................ 503
7.3.3 80486 l\:ew Instructions Beyond Those of the 80386 ................. 504
7.4 Intel Pentium Microprocesso r ........................................... .. ............. ...... ..... 505
7.4.1 Pentium Processor Block Diagram .................... ....................... ... 507
7.4.2 Pentium Registers ........................................... ......................... .. .... 508
7.4.3 Pentium Addressing Modes and Instructions ............................. 508
7.4 .4 Pentium Vs. 80486 Basic Differences in
Registers, Paging, Stack Operations, and Exceptions ...... ........... 509
7 .4.4.a Registers of the Pentium Processo r vs.
T hose of th<.: t!U486 ........ ................ ...... ......... .. ........ ...... 509
7.4.4.b Paging ..................... ................... .... ............... ........... ...... 509
7.4.4.c Stack Operations ............... ........................................... 509
7.4.4 .d Exceptions ...................................................... ............... 510
7.4.5 Input/Output ....................... .......................................................... 5IO
 7.4.6 Applications with the Pentium ..................................................... S 10
Questions and Problems ................................................................................................ Sll

Chapter 8 RJSC Microprocessors: Intel 80960, Motorola MC88100 and PowerPC

8.1 Basics of RJSC ................................................................................... ......... ... SIS
8.2 Intel80960 ...................................................................................... ;.............. Sl6
8.2.1 Introduction ....................................................... ....................... ..... Sl6
8.2.2 Key Performance Features ............................................................ Sl6
8.2.2.a Load and Store Model .. ........ ... .................................... Sl6
8.2.2.b Large Internal Register Sets ......................................... Sl6
8.2.2.c On-Chip Code and Data Checking ............................ Sl6
8.2.2.d Overlapped Instruction Execution .............................. S17
8.2.2.e Single Clock Instructions ........ ................. ............ ........ S17
8.2.2.f Interrupt Model ........................................................ .... S17
8.2.2.g Procedure Call Mechanism ......................................... S17
8.2.2.h Instruction Set and Addressing ............ .. .......... ...... .... . Sl7
8.2.2.i Floating Point Unit
(Available with 80960SB only) .................... ................ S17
8.2.3 80960SNSB Registers ................................................ .................... S17
8.2.3.a Register Scoreboarding ................................................ S19
8.2.3.b Instruction Pointer ....................................................... S19
8.2.3.c Process Control Register .............................................. Sl9
8.2.3.d Arithmetic Control ....................................................... Sl9
8.2.4 Data Types and Addresses ............................................................ S20
8.2.4.a Data Types .................................................................... S20
8.2.4.b Literals ..................................................... ...................... S20
8.2.4.c Register Addressing .............. .......................... .. ........... . S20
8.2.4.d Memory Addressing Modes ........................................ S20
8.2.5 809690SNSB Instruction Set ..................................................... ... S21
8.2.5.a Data Movement .................. ........ ........ ...................... .... S22
8.2.S.b Conversion (Available with 80960SB only) .. ............. 524
8.2.5.c Arithmetic and Logic Operations .................. ............. S2S
8.2.5.d Comparison and Control ............................................ 531
8.2.6 80960SNSB Pins and Signals .............................. .. .................... .. . S39
8.2.6.a Basic Bus States ................................... ........ ................. 540
8.2.6.b Signals Groups .............................................................. 540
8.2.7 Basic READ and WRITE ...................................... ......................... S42
8.2.8 80960SA/SB-Based Microcomputer ............................................. 543
8.3 Motorola MC88100 RlSC Microprocessor .......................... .. .. ........ ........... S44
8.3.1 88100/88200 Interface ........................................ ............ .. ............. S45
8.3.2 88100 Registers ............................................................................... 546
8.3 .3 88100 Data Types, Addressing Modes, and Instructions .... ....... 551
8.3.4 88100 Pins and Signals .................................................................. 565
8.3.5 88100 Exception Processing ................................. ......................... 566
8.4 IBM/Motorola/Apple PowerPC 601 ................................ ............................ 567
8.4. 1 Power PC 60 I Block Diagram ....................................................... 568
8.4.l.a RTC (Real Time Clock) .............. ................................. 568
8.4. 1.b Instruction Unit ............................................ ............... 570
8.4.l.c Execution Unit ............................................................. 570
8.4.l.d Memory Management Unit (MMU) .......... .... ...... .... .. 570
8.4.1.e Cache Unit ............................................ ............ ............ 571
 8.4.l.f Memory Unit ............................. ..... .............................. 571
8.4.1.g System Interface ........................... ... ............................. 572
8.4.2 Byte and Bit Ordering ................................... .............................. .. 572
8.4.3 PowerPC Resigsters and Programming Model ........................... 572
8.4.3.a User-Level Registers ....................... .............................. 572
8.4.3.b Supervisor-Level Registers ........................................... 574
8.4.4 Power PC 601 Memory Addressing:
Effective Address (EA) Calculation ........ ... ... ................................ 575
8.4.4.a Register Indirect with Immediate Index Mode ......... 576
8.4.4.b Register Indirect with Index Mode ............................. 576
8.4.5 Power PC 60 l Typical Instructions ............................................... 577
8.4.5.a Integer Instructions .............................. .. ...... ................ 577
8.4.5.b Floating-Point Instructions ......................................... 578
8.4.5.c Load/Store Instructions ......... ...................................... 579
8.4.5.d Flow Control Instructions ................................... ........ 579
8.4.5.e Processor Control Instructions ................................... 579
8.4.6 PowerPC 601 Exception Model ............ ........................................ 579
8.4.7 601 System Interface ...................................................................... 580
8.4.7.a Memory Accesses ....................... .................................. 580
8.4.7.b I/0 Controller Interface Operations ........................... 580
8.4.7.c 601 Signals ...................................................... ... ........... 580
8.4.8 PowerPC 601 Vs. Alpha 21064 ..................................................... 581
8.5 64-Bit RISC Microprocessors ............................................. ........... .............. 582
Questions and Problems .. .................................. ..................................... ....... ... ............. 583

Chapter 9 Peripheral Interfacing

9.1 Keyboard Interface .............. .......... ... ................... ......................................... 587
9.1.1 Basics of Keyboard and Display Interface
to a Microprocessor ........................................ .... ........................... 587
9.1.2 8086 Keyboard Interface ............................................................... 590
9.1.2.a Hardware ..................................... ....... .................. .... .... 590
9.1.2.b Software ......... .. ........ ......................... .... ............... .......... 590
9.2 DMA Controllers .......................... .................................... .... .... .................... 594
9.3 Printer Interface ................................................. .. ...... .. ...... ......... .................. 599
9.3.1 LRC7040 Printer Interface Using Direct
Microcomputer Control .................... ...... ..... ...... .......... ... ... ........... 60 l
9.3.2 LRC7040 Printer Interface to a Microcomputer
Using the 8295 Printer Controller Chip .. .................................... 601
9.3.2.a 8295 Parallel Interface .................................................. 602
9.3.2.b 8295 Serial Mode .......... .......... .... .................................. 604
9.4 CRT (Cathode Ray Tube) Controller and
Graphics Controller Chips ........................................................................... 605
9.4.1 CRT Fundamentals ........................................................................ 605
9.4 .2 Intel 8275 CRT Controller .................... ... ...... ............................... 607
9.4 .3 Intel 82786 Graphics ControUer ................................................... 608
9.5 Coprocessors ...... .... ......... ................................................. .. ........................... 610
9.5.1 Intel 8087 .................. .. .......... .............................. .... ...... ................. 610
9.5.2 Intel 80287 .. ........ .. .... ...... ........ .. ........ ..... ................. .............. ...... .... 611
9.5.3 Intel 80387 ....................................................... ................ ............... 611
Questions and Problems ............. ...... ............... .... .......................................................... 612
Chapter 10 Design Problems
10.1 Design Problem No. 1 .................................................................................. 615
10.1.1 Problem Statement ........................................................................ 615
10.1.2 Objective ......................................................................................... 615
10.1.3 Operation ....................................................................................... 615
10.1.4 Hardware ........................................................................................ 615
10. 1.5 Software .......................................................................................... 617
10.2 Design Problem No. 2 .................................................................................. 621
10.2.1 Display Scroller Using the Intel 8086 .......................................... 621
10.2.l.a Introduction and Problem Statement ........................ 621
10.2.1.b Hardware Description .................................................. 622
10.2.l.c Software Development ................................................. 626
10.3 Design Problem No. 3 .................................................................................. 628
I 0.3.1 Problem Statement ........................................................................ 628
10.3.2 Solution No. 1 ................................................................................ 628
10.3.2.a Hardware ...................................................................... 628
10.3.2.b Microcomputer Development System ........................ 630
10.3.2.c Software ......................................................................... 632
10.3.3 Solution No. 2 ................................................................................ 637
10.3.3.a Hardware ...................................................................... 637
10.3.3.b Software ......................................................................... 637
Questions and Problems ................................................................................................ 648

Appendix A: The Hewlett-Packard (HP) 64000 ........................................................... 653

Appendix B: Moto rola MC68000 and Support Chips - Data Sheets ....................... 683
Appendix C: Intel 8085, 8086, and Support Chips- Data Sheets ............................ 695
Appendix D: MC68000 Instruction Execution Times .................................................. 713
Appendix E: 8086 Instruction Set Reference Data ....................................................... 723
Appendix F: Glossary/ASCII Codes .............................................................................. 741
Bibliography ....................................................................................................................... 753
Credits ................................................................................................................................. 757
Index ................................................................................................................................... 759
 1
INTRODUCTION TO
MICROPROCESSORS
AND MICROCOMPUTER-
BASED APPLICATIONS

This chapter provides a brief summary of the features of microprocessors and microcomputer-
based applications.
The basic elements of a computer are the Central Processing Unit (CPU), the Memory, and
Input/Output (I/0) units. The CPU translates instructions, performs arithmetic or logic
operations, and temporarily stores instructions and data in its internal high-speed registers .
The memory stores programs and data. The I/0 unit interfaces the computer with external
devices such as keyboard and display.
With the advent of semiconductor technology, it is possible to integrate the CPU in a single
chip. The result is the microprocessor. Metal Oxide Semiconductor (MOS) technology is
typically used to fabricate the standard off-the-shelf microprocessors such as those manufac-
tured by Intel and Motorola . Appropriate memory and I/0 chips are interfaced to the micro-
processor to design a microcomputer. Single-chip microcomputers are also available in which
the microprocessor, memory, and 1/0 are all fabricated in the same chip. These single-chip
microcomputers offer limited capabilities. However, they are ideal for certain applications
such as peripheral controllers.
Single chip microcomputers are also referred to as "microcontrollers". The microcontrollers
are typically used for dedicated applications such as automotive systems, home appliances and
home entertainment systems. Typical microcontrollers, therefore, include on-chip timers, N
D (Analog to Digital) and D/ A Digital
( to Analog) converters. Two popular microcontrollers
are Intel 8751 (8-bit )/8096 (16-bit) and Motorola HCll (8-bit)/HC16 (16-bit) . The 16-bit
microcontrollers include more on-chip ROM , RAM, and 1/0 compared to the 8-bit
microcontroiJers .
The efficient development of microprocessor-based systems necessitates the use of a micro-
computer development system. The microcomputer development system is used for the
design, debugging, and sometimes the documentation of a microprocessor-based system.
This chapter first covers the evolution of 8-, 16-, and 32-bit microprocessors along with an
overview of programming languages, microcomputer hardware, and software. The attributes
of typical microcomputer development systems features as well as some specific microproces-
sor applications are also included.
 2 Microprocessors and Microcomputer-Based System Design, 2nd Edition

1.1 Evolution of the Microprocessor

Intel Corporation introduced the first microprocessor, the 4004 (4-bit), in 197 I. The 4004
evolved from a development effort while designing a calculator chip set.
Soon after the 4004 appeared in the commercial market, three other microprocessors were
introduced. These were the Rockwell International 4-bit PPS-4, the Intel 8-bit 8008, and the
National Semiconductor 16-bit IMP-16.
The microprocessors introduced between 1971 and 1973 were the first-generation systems.
They were designed using the PMOS (P-type MOS) technology. This technology provided low
cost, slow speed, and low output currents and was not compatible \vith TTL (Transistor
Transistor Logic).
After 1973, second-generation microprocessors such as MOS Technology 6502, Motorola
6800 and 6809, Intel8085, and Zilog Z80 evolved. These 8-bit processors were fabricated using
the NMOS (N-type MOS) technology. The NMOS process offers faster speed and higher
density than PMOS and is TTL-compatible.
After 1978, the third-generation microprocessors were introduced. These processors are 16
bits wide (16-bit ALU) and include typical processors such as Intel 8086/80186/80286 and
Motorola 68000/68010. These microprocessors were designed using the HMOS (high-density
MOS) technology. HMOS provides the following advantages over NMOS:
• Speed-Power-Product (SPP) of HMOS is four times better than NMOS:
NMOS = 4 Picojoules (PJ)
HMOS = 1 Picojoule (PJ)

Note that Speed-Power-Product

= speed * power
= nanosecond * milliwatt
= picojoules
Circuit densities provided by HMOS are approximately twice those of NMOS:
NMOS= 4128 gates/IJ.m 2
HMOS = 1852.5 gates/IJ.m 2
where I IJ.m (micrometer) = 10-{; meter.
Later, Intel utilized the HMOS technology to fabricate the 8085A. Thus, Intel offers a high-
speed version of the 8085A called 8085AH. The price of the 8085AH is higher than the 8085A.
In 1980, fourth-generation microprocessors evolved. Intel introduced the first commercial
32-bit microprocessor, the problematic Intel 432. This processor was eventually discontinued
by Intel. Since 1985, more 32-bit microprocessors have been introduced. These include
Motorola's MC 68020/68030/68040/PowerPC, Intel's 80386/80486 and the Intel Pentium
processor. These processors are fabricated using the low-power version of the HMOS technol-
ogy called the HCMOS.
The performance offered by the 32-bit microprocessor is more comparable to that of
superminicomputers such as Digital Equipment Corporation's VAX 11/750 and VAX 11/780.
Both Intel and Motorola introduced 32-bit RISC (Reduced Instruction Set Computer) micro-
processors, namely the Intel 80960 and Motorola MC88100/PowerPC with simplified instruc-
tion sets. Note that the purpose of RISC microprocessors is to maximize speed by reducing
clock cycles per instruction. Almost all computations can be obtained from a simple instruc-
tion set.
RJSC microprocessors have hardwired instruction sets like the non-RISC microprocessors
such as the Intel8085 and MOS 6502. This means that for every instruction, there exists actual,
physical connections that provide the desired instruction decoding. The microprocessor,
 Introduction to Microprocessors and Microcomputer-Based Applications 3

therefore, does not use valuable clock cycles (machine cycles) in instruction decoding. Most
RISC instructions require a maximum of only two clock cycles to complete. These instructions
are restricted to register-to-register operations with load and store for memory access. Since
RJSC-type microprocessors are hardwired, instructions may be executed simultaneously (as
long as the instructions do not share the same register.) This technique is known as pipelining.
Pipelining is the mechanism that actually enables simultaneous processing to occur. In-
structions are fetched in sequential order. The processor continues to fetch instructions even
though it has not executed the present instruction. This provides an input pipeline to the
instruction cache. At this stage, the instructions are intelligently fed into the instruction
execution unit for processing. When an instruction is executed, the registers used by the
instruction clear respective bits in a scoreboard register. As the microprocessor is executing a
given instruction, it checks the scoreboard register to see if the next instructions (residing in
a fast read/write memory internal to the microprocessor called the instruction cache) use
registers that are currently in use. Instructions not using the same registers can therefore be
executed at the same time. The RISC microprocessors can execute as many as five instructions
simultaneously.
The trend in microprocessors is implementation of more on-chip functions and for im-
provement of the speeds of memory and 1/0 devices. Some manufacturers are speeding up the
processors for data crunching type applications. Digital Equipment Corporation's Alpha
21164 with 300 MHz clock, four instruction-per-cycle rate and RISC-based architecture is the
fastest microprocessor available today.

1.2 Microprocessor Data Types

This section discusses the data types used by microprocessor. Typical data types include signed
and unsigned binary integers, binary coded decimal (BCD), American Standard Code for
Information Interchange (ASCII) and floating-point numbers. Note that binary integer num-
bers do not support fractions in microprocessors . Fractions and mixed numbers (numbers
comprised of integers and fractions) use either binary or BCD floating-point formats. Float-
ing-point numbers are often referred to as real numbers.

1.2.1 Unsigned and Signed Binary Integers

An unsigned binary integer has no arithmetic sign. Unsigned binary numbers are therefore
always positive. An example is memory address which is always a positive number. An 8-bit
unsigned binary integer represents all numbers from 00 16 through FF 16 (0 10 through 255 10 ).
A signed binary integer, on the other hand, includes both positive and negative numbers .
It is represented in true form for a positive number and in two's complement form for a
negative number. For example, the decimal number+ 10 can be represented as a true form 8-
bit number in a microprocessor as 0000 1010 (binary) or OA (hexadecimal). The decimal
number -10 can be represented in two's complement form as 1111 0110 (binary) or F6
(hexadecimal). The most significant bit of a signed binary number represents the sign of the
number. For example, bit 7 of an 8-bit signed number, bit 15 of a 16-bit signed number and
bit 31 of a 32-bit signed number represent the signs of the respective numbers. A 32-bit signed
binary integer includes all numbers from -2,147,483,648 to 2,147,483,647 with 0 being a
positive number.
Finally, note that the hexadecimal number FF 16 is 255 10 when represented as an unsigned
number. On the other hand, FF 16 is -1 10 when represented as a signed number.

1.2.2 BCD (Binary Coded Decimal) Numbers

A BCD digit consists of four bits with a value ranging from 0000 2 to 1001 2 (0 through 9
decimal). A BCD digit greater than 9 10 can be represented as two or more BCD digits.
 4 Microprocessors and Microcomputer-Based System Design, 2nd Edition

Microprocessors store BCD numbers in two forms, packed and unpacked. The unpacked
BCD number represents each BCD digit as a byte while the packed BCD number represents
two BCD digits in a byte. For example, 23 10 is represented as 0000 0010 0000 0011 2 as two
unpacked BCD numbers, while it is represented as 0010 0011 2 as a packed BCD number.
Microprocessors normally input data from a keypad in unpacked BCD form. This data can
then be converted by writing a program in the microprocessor to packed BCD form for
arithmetic operations or for storing in memory. After processing, the packed BCD result is
then converted to unpacked BCD form by another microprocessor program written by the
user for displays. Typical displays use either unpacked BCD data or unpacked BCD data
converted to seven segment code by the microprocessor's program.

1.2.3 ASCII
ASCII (American Standard Code for Information Interchange) is a code that represents
alphanumeric (alpha characters and numbers) in a microcomputer's memory. ASCII also
represents special symbols such as# and o/o. It is a 7 -bit code. The most significant bit (bit 7)
is sometimes used as a parity bit. The parity bit represents the number of ones in the byte. If
the number of ones is odd, the parity is odd; otherwise, the parity is even.
Also, note that the hexadecimal numbers 30 16 through 39 16 are ASCII codes representing the
decimal numbers 0 through 9. A listing of the ASCII codes is included in Appendix F.

1.2.4 Floating-Point Numbers

Floating-Point numbers contain three components. These are a sign, exponent and mantissa.
For example, consider the decimal value -2.5 x JQ- 2 • The sign is negative, the exponent is -2 and
the significand or mantissa is 2.5. In floating point numbers, it is possible to store the same
number in several different ways. For example, 1 can be represented as 10.0 x JQ- 1, 1.0 x 10°,
0.1 x 10 1 and 0.01 x 10 2 • To make computations yield the maximum accuracy, the numbers are
normalized. This means that the exponent is adjusted so that the mantissa always follows a
specific format. A binary floating point number is represented as a normalized binary fraction
raised to a power of 2. To convert a binary number to its standard floating-point form, the
binary number is converted to a normalized floating-point number. Note that a normalized
binary floating-point number is represented as I.XXXXXX raised to some power of 2 where
X can be 0 or I. The 1. part is implied and is not stored by the microprocessor. First, the binary
number is converted to a common 32-bit floating-point format. The most significant bit (bit
31) is the sign bit (S). If S is zero, the number is positive, while if S is one, the number is
negative. The next 8 bits contain the biased exponent. This means that an 8-bit number 7F 16
or 127 10 is added to the exponent. Biased exponent makes numeric comparison (such as less
than or greater than) easy. The bias is usually chosen such that the most negative number
aU owed in the exponent becomes zero and the most positive number becomes the largest value
of the representation. For example, with an 8-bit exponent, and + 127 10 bias, the smallest and
the largest values of the bias exponent are 0 10 and 255 10 respectively. Note that the zero biased
exponent is represented as 127 10 , while the unbiased minimum and maximum values of the 8-
bit exponent are -127 10 and + 128 10 respectively. The remaining 23 bits represent the fractional
part of the number. Note that zero is stored as 32 zeros while infinity is stored as 32 ones. As
an example, consider converting the decimal number 10 to the standard floating-point format
as follows:

I. I 010 = I 0 I 20
2. Normalize the binary number as I.XXXXXX x 2n = 1.010 x 23
3. Sign, S = 0 for positive
4. Biased exponent = 7F 16 + 3 = 82 16
Introduction to Microprocessors and Microcomputer-Based Applications 5

5. 23-bit Fraction = 0100 0000 0000 00000000 000

6. The floating-point equivalent of 10 10 is
S Exponent Fraction
0 1000 00 10 0100 0000 0000 0000 0000 0000

A special case of the floating-point format is called NaN (Not a Number). NaNs are results
generated by floating-point operations that have no mathematical interpretations. These
results may be generated by operations such as multiplication of infinity by infinity.
The BCD floating-point form represents a number in BCD scientific notation . The number
is represented as normalized significand raised to some power of 10. Each BCD floating-point
number is represented in typical microprocessors as 80 bits. The BCD fraction is 16 digits wide
(64-bit) and is stored as packed BCD digits. The whole number portion of the significand is
stored as one digit BCD from 0 to 9. The BCD exponent along with the sign is expressed as
12 bits.
Typical floating-point coprocessors such as 80387 (for the Intel80386 microprocessor) and
6888l/68882 (for the Motorola 68020/68030 microprocessor) support several data types. For
example, the 80387 coprocessor supports seven data types. These are word integer (16-bits),
short integer (32-bit), long integer (64-bit), packed BCD (80-bit), short real (32-bit), long real
(64-bit), and temporary real (80-bit).
The 80387 integer data types are represented by the two's complement same as those used
by the 80386. The only difference is that the 80386 supports an 8-bit integer while the 80387
supports a 64-bit integer.
The 80387 supports 80-bit packed BCD with 18 decimal digits (bits 0-71 ), bit 79 as the sign-
bit and seven (bits 72-78) unused bits. With 18-digits representation, the COBOL standard
(the High level language utilizing BCD) is followed.
The 80387 supports three real data formats. These are short real (32-bit with one sign bit,
8-bit exponent and 23-bit significand) , long real (64-bit with one sign-bit, 11-bit for exponent
and 62-bit for the significand), temporary real (80-bit with one sign-bit, 15-bit exponent, and
64-bit significand).
The 80387 uses the temporary real format internally. All data types are converted by the
80387 immediately into temporary real. This is done to maximum precision and range of
computations.
The 80387 supports four special cases. These are zeros, infinities (both positive and nega-
tive), denormals, and NaNs (signalling and quiet) .
Denormals represent very small numbers that are not normalized. Normally, numbers are
required to be normalized by shifting to left until the most significant is one. Denormals do
not have one as the most significant bit of the significand. Denormals permit a gradual
underflow. That is the precision is lost gradually rather than abruptly. When the least normal-
izable number is reached, the next small representation is zero. Denormals provide gradual
underflow of numbers that are not normalized. That is, denormals extend the range of very
small numbers significantly, but with some loss in precision.
A signaling NaN causes an invalid operation exception when used in an operation. A quiet
NaN, on the other hand, does not cause an invalid operation exception.
The floating-point data types supported by the Motorola 68881/68882 floating-point
coprocessors are summarized next. Note that the 68881 and 68882 differ in execution speed.
They are basically identical. The 68882 is an enhanced version of the 68881 in that it executes
several floating-point instructions concurrentJy with the 68020/68030. The 68881/68882 sup-
ports integers, binary floating-point numbers, and packed floating-point BCD. Data are
represented externally by using these formats. The 68881/68882 utilizes an 80-bit binary
floating point form to represent all data internally.
The 68881/68882 supports three signed integer formats. These are 8-bit byte, 16-bit word,
and 32-bit long word .
 6 Microprocessors and Microcomputer-Based System Design, 2nd Edition

Binary floating-point format is also called binary real form. The 68881168882 supports
binary floating-point form which contains three fields. These are a sign , biased exponent and
a significand. The 68881/68882 operates on these sizes, namely 32-bit single-precision, 64-bit
double precision, and 96-bit extended precision.
For single precision (bit 31: sign bit, bits 23-30: 8-bit exponent, bits 0-22: 23-bit significand),
64-bit double precision (bit 63: sign bit, bits 62-52: 11-bit exponent, bits 0-51 : 52-bit significand),
and 96-bit extended-precision (bit 95: sign bit, bits 80-94: IS -bit exponent, bits 64-79: zero;
sixteen unused bits, bits 0-63: 64-bit significand).
The biased exponent is used. The Single Precision adds a bias of 127 10 {7F 16 ), double
Precision uses a bias of 1023 10 (3FF 16 ), and the extended-Precision uses a bias of 16383 10
{3FFFF 16 ). The bias is added to the exponent before it is stored in this format and subtracted
to convert to a true exponent when the number is interpreted.
A few special cases that do not conform to the floating-point form are also handled by the
68881/68882. For example, a zero is represented with all bits of the exponent and significand
as zeros. The sign bit may be a one or a zero representing +0 or -0. The infinity, on the other
hand is represented by all bits in the exponent and significand set to ones. The sign bit may
be zero or one representing positive or negative infinity. The 68881/68882 supports BCD
floating point form which represent each number as normalized significand raised to a power
of 10. This format stores a number as 96 bits. The least significant 64 bits (8 bytes) contain the
16-digit BCD fraction . The next byte contains the whole number portion of the significand {0-
9). The most significant bit (bit 95) contains the sign of significand while bit 94 includes the
sign of the exponent. The exponent is represented by three digit BCD packed exponent {000-
999) in bits 80-91. SimiJar to the 80387, the 68881/68882 also represents NaN's and also
provides exceptions for signaling NaN's.
IEEE has established the standard for floating-point arithmetic specified by ANSI -IEEE754-
1985. Typical 32-bit microprocessors use this standard.

1.3 Microcomputer Hardware

In this section, some unique features associated with various microcomputer components will
be described.
The microcomputer contains a microprocessor, a memory unit, and an input/output unit.
These elements are explained in the following in detail. Figure l.l shows a simplified block
diagram of a microcomputer.

1.3.1 The System Bus

The system bus contains three buses. These are the address bus, the data bus, and the control
bus. These buses connect the microprocessor to each of the memory and 1/0 elements so that
information transfer between the microprocessor and any of the other elements can take place.

System Bus

I I
Memory
I
Microprocessor 1/0
(ROMIRAM)

FIGURE 1.1 Simplified block diagram of a microprocessor.

 Introduction to Microprocessors and Microcomputer-Based Applications 7

On the address bus, information transfer normally takes place only in one direction, from
the microprocessor to the memory or 1/0 elements. Therefore, this is called a unidirectional
bus. This bus is usually 16 to 32 bits wide. The number of unique addresses that the micro-
processor can generate on this bus depends on the width of this bus. For example, for a 16-
bit address bus, the microprocessor can generate 2 16 = 65,536 different possible addresses. A
different memory location or an 1/0 element can be represented by each one of these ad-
dresses.
The data bus is a bidirectional bus, that is, information can flow in both directions, to or
from the microprocessor. This bus is normally 8, 16, or 32 bits wide.
The control bus is used to transmit signals that are used to synchronize the operation of the
individual microcomputer elements. Typical control signals include READ, WRITE, and
RESET. Some signals on the control bus such as interrupt signals are unidirectional, while
some others such as RESET may be bidirectional.

1.3.2 The Microprocessor

The commercial microprocessor, fabricated using the MOS technology, is normally contained
in a single chip. The microprocessor is comprised of a register section, one or more ALUs
(Arithmetic Logic Units), and a control unit. Depending on the register section, the micropro-
cessor can be classified either as an accumulator-based or a general-purpose register-based
machine.
In an accumulator-based microprocessor such as the Intel 8085 and Motorola 6809, one of
the operands is assumed to be held in a special register called the "accumulator". All arithmetic
and logic operations are performed using this register as one of the data sources. The result
after the operation is stored in the accumulator. One-address instructions are very predomi-
nant in this organization. Eight-bit microprocessors are usually accumulator-based.
The general-purpose register-based microprocessor is usually popular with 16- and 32-bit
microprocessors, such as Intel 8086/80386/80486 and Motorola 68000/68020/68030/68040,
and is called general-purpose, since its registers can be used to hold data, memory addresses,
or the results of arithmetic or logic operations. The number, size, and types of registers vary
from one microprocessor to another. Most registers are general -purpose registers, while some
are provided with dedicated functions .
Typical dedicated registers include the Program Counter (PC) , the Instruction Register
(IR), Status Register (SR), the Stack Pointer (SP) and the Index Register. The 32-bit micropro-
cessors include special on-chip combinational network called the Barrel Shifter.
The PC normally contains the address of the next instruction to be executed. Upon activat-
ing the microprocessor chip's RESET input, the PC is normally initialized with the address of
the first instruction. For example, the 80486, upon hardware reset, reads the first instruction
from the 32-bit address FFFFFFF0 16 • In order to execute the instruction, the microprocessor
normally places the PC contents on the address bus and reads (fetches) the first instruction
from external memory. The program counter contents are then automatically incremented by
the ALU . The microcomputer thus executes a program sequentially unless it encounters a
jump or branch instruction. The size of the PC varies from one microprocessor to another
depending on the address size. For example, the 68000 has a 24-bit PC, while the 68040
contains a 32-bit PC.
The instruction register (IR) contains the instruction to be executed. After fetching an
instruction from memory, the microprocessor places it in the IR for translation .
The status register contains individual bits with each bit having a special meaning. The bits
in the status register are called flags. Each flag is usually set or reset by an ALU operation. The
flags are used by the Conditional Branch instructions. Typical flags include carry, sign, zero,
and overflow.
8 Microprocessors and Microcomputer-Based System Design, 2nd Edition

The carry (C) flag is used to reflect whether or not an arithmetic operation such as ADD
generates a carry. The carry is generated out of the 8th bit (bit 7) for byte operations, 16th bit
(bit IS) for 16-bit, or 32nd bit (bit 31) for 32-bit operations. The carry is used as the borrow
flag for subtraction. In multiple word arithmetic operations, any carry from a low-order wo rd
must be reflected in the high-order word for correct results.
The zero (Z) flag is used to indicate whether the result of an arithmetic or logic operation
is zero. Z = l for a zero result and Z = 0 for a non-zero result. The sign flag (sometimes also
called the negative flag) indicates whether a number is positive or negative. S = l indicates a
negative number if the most significant bit of the number is one; S = 0 indicates a positive
number if the most significant bit of the number is ze ro.
The overflow (V) flag is set to one if the result of an arithmetic operation on signed (two's
complement) numbers is too large for the microprocessor's m aximum word size; the C flag
is overflow for unsigned numbers. The overflow flag for signed 8-bit numbers can be shown
as V = C7 EB C6, where C7 is the final carry and C6 is the previous bit's carry. The EB symbol
indicates exclusive-OR operation. This can be illustrated by the numerical examples shown
below:

0000 0100
+ 0000 0010
C7~ o+---0000 OliO

C6=~0--:
From the above, the result is correct when C6 and C7 have the sam e values (0 in this case) .
When C6 and C7 are different, an overtlow occurs. For example, consider the followin g:

I 011 1110 6610

lOll !Ill 65 10
Olll 11 01
+ 12510(' )

C7•1~ resu l! is
incorrect

C6 = 0

The result is incorrect. Since V = C6 E!1 C7 = 0 E!1 I = I, the overflow fl ag is set. Note that this
applies to signed two's complemented numbers only.
The stack pointer (SP) register addresses the stack. A stack is Last- In First-Out (LIFO) read/
write memory in the sense that items that go in last will come o ut first. T his is because stacks
perform all read (POP) and write (PUSH ) o perations from one end.
The stack is addressed by a register called the stack pointer (SP). The size of the SP is
dependent o n the microprocessor's address size. The stack is normally used by subroutines or
interrupts for saving certain registers such as the program counter.
Two instructions, PUSH (stack write) and POP (stack read), ca n usually be perfo rmed by
the programmer to manipulate the stack. If the stack is accessed from the top, the stack pointer
is decremented before a PUSH and incremented after a POP. On the other hand, if the stack
is accessed from the bottom, the SP is incremented before a PUSH and decremented afte r a
POP. Typical microprocessors access the stack from the top. Depending on the microproces-
Introduction to Microprocessors and Microcomputer-Based Applications 9

Before PUSH Before PUSH

16 -register
16-register Stack Stack
to be PUSHed
to be PUSHed
08A1
5007
I 08A1
~ A1 5007
~
5008 08 5008

.---------:.,1rr
:
SP after
SP before
01 5009 01 S009
PUSH
PUSH

5009 .
OS SOOA
I S007 I OS SOOA

F2 SOOB F2 500B

Top oft he
'--------- Stack

(a) Stack PUSH via top II

16-register in Before POP I 16-register in After POP
which stack data to 1 which stack data to
be POPped into Stack be POPped into Stack

I 0721
I I 02 Fl
I
r: F1 50 08 Fl S008

02 50 09 02 S009

v;
SP before POP SP after POP
soOA
I 5008
~
61
I SOOA 61 SOOA

26 soOB 26 SOOB

Top of th e
Stack

(b) Stack POP via top

FIGURE 1.2 PUSH and POP operations via top.

sor, an 8-, 16-, or 32-bit register can be pushed onto or popped from the stack. The value by
which the SP is incremented or decremented after POP or PUSH operations depends on the
register size. For example, values of one for an 8-bit register, two for 16-bit registers, and fo ur
for 32-bit registers are used. Figure 1.2 shows the stack data when accessed from the top befo re
and after PUSHing a 16-bit register onto the stack or POPping 16 bits from the stack into the
16-bit register. Note that stack items PUSHed must be POPped in reverse order. The item
pushed last must be popped first.
Consider the PUSH operation in Figure l.2a when the stack is accessed from the top. Th e
SP is decremented by 2 after the PUSH. The SP is decremented since it is accessed from the
top. A decrement value of 2 is used since the register to be pushed is 16 bits wide.
The POP operation shown in Figure 1.2b is the reverse of the PUSH. The SP is incremented
after POP. The contents of locations 5008 16 and 5009 16 are assumed to be empty.
An index register is typically used as a counter for an instruction or for general storage
functions. The index register is useful with instructions where tables or arrays of data are
accessed. The general-purpose register-based microprocessor can use any general-purpose reg-
ister as the index register.
 10 Microprocessors and Microcomputer-Based System Design, 2nd Edition

Typical 32-bit microprocessors such as the Intel 80386/80486 and Motorola 68020/68030/
68040 include a special type of shifter called barrel shifter for performing fast shift operations.
The barrel shifter is an on-chip combinational network for 32-bit microprocessors and
provides fast shift operations. For example, the 80386 barrel shifter can shift a number from
0 through 64 positions in one clock period (clock rate is 16.67 MHz).
The ALU in the microprocessor performs all arithmetic and logic operations on data_ The
size of the ALU defines the size of the microprocessor. For example, Intel 8086 (or Motorola
68000) is a 16-bit microprocessor since its ALU is 16 bits wide. The Intel 8088 (or Motorola
68008) is also a 16-bit microprocessor since its ALU is 16 bits wide, even though its data bus
is 8 bits wide. Motorola 68040 (or Intel 80486) is a 32-bit microprocessor since its ALU is 32
bits wide. The ALU usually performs operations such as binary addition and subtraction. The
32-bit microprocessors include multiple ALUs for parallel operations and thus achieve fast
speed.
The control unit of the microprocessor performs instruction interpreting and sequencing.
In the fetch phase, the control unit reads instructions from memory using the PC as a pointer.
It then recognizes the instruction type, gets the necessary operands, and routes them to the
appropriate functional units of the execution unit. Necessary signals are issued to the execu-
tion unit to perform the desired operations, and the results are routed to the specified
destination.
In the sequencing phase, the control unit determines the address of the next instruction to
be executed and loads it into the PC. The control unit is typical.ly designed using one of three
techniques:
Hardwired control
Microprogramming
• Nanoprogramming
The hardwired control unit is designed by physically connecting typical components such
as gates and flip-flops. Typical 32-bit RISC microprocessors such as the Intel 80960 and
Motorola 88100 are designed using hardwired control. The microprogrammed control unit
includes a control ROM for translating the instructions. Intel 8086 is a microprogrammed
microprocessor. Nanoprogramming includes two ROMs inside the control unit. The first
ROM (microROM) stores all the addresses of the second ROM (nanoROM). If the microin-
structions (which is the case with the 68000/68020/68030/68040) repeat many times in a
microprogram, use of two-level ROMs provides tremendous memory savings. This is the
reason that the control units of the 68000, 68020, 68030, and 68040 are nanoprogrammed.

1.3.3 Memory Organization

:.3.3.a Introduction
A memory unit is an integral part of any microcomputer system and its primary purpose is to
hold programs and data.
In a broad sense, a microcomputer memory system can be logically divided into three
groups:
Processor memory
Primary or main memory
Secondary memory
Processor memory refers to the microprocessor registers. These registers are used to hold
temporary results when a computation is in progress. Also, there is no speed disparity between
these registers and the microprocessor because they are fabricated using the same technology.
Introduction to Microprocessors and Microcomputer-Based Applications 11

However, the cost involved in this approach forces a microcomputer architect to include only
a few registers (usually 8 or 16) in the microprocessor.
Primary or main memory is the storage area in which all programs are executed. The
microprocessor can directly access only those items that are stored in primary memory.
Therefore, all programs and data must be within the primary memory prior to execution.
Secondary memory refers to the storage medium comprising slow devices such as magnetic
tapes and disks. These devices are used to hold large data files and huge programs such as
compilers and data base management systems which are not needed by the processor fre-
quently. Sometimes secondary memories are also referred to as auxiliary or backup store or
virtual memory.
Secondary memory stores programs and data in excess of the main memory. The micro-
computer cannot directly execute programs stored in the secondary memory. In order to
execute these programs, the microcomputer must transfer them to its main memory by a
system program called the operating system. This topic is covered later in the chapter.
Data in disk memories are stored in tracks. A track is a concentric ring of data stored on a
surface of a disk. Each track is further subdivided into several sectors. Each sector typically
stores 512 or 1024 bytes of data. AJI disk memories use magnetic media except the optical disk
memory which stores data on a plastic disk. Data is read or sometimes written on the optical
disk with a laser beam. There are two types of optical disks. These are the CD-ROM (Compact
Disk Read Only Memory) and the WORM (Write Once Read Many) . The CD-ROM is
inexpensive compared to the WORM drive. However it suffers from lack of speed and has
limited software applications at the present time. The WORM drive is typically used in huge
data storing applications such as insurance and banking since data can be written only once.
The optical disk memory is currently becoming popular with microcomputer systems. One of
the commonly used disk memories with microcomputer systems is the floppy or flexible disk.
The floppy disk is a flat, round piece of plastic coated with magnetically sensitive oxide
material . The disk is provided with a protective jacket to prevent fingerprints or foreign matter
from contaminating the disk's surface. The floppy disk is available in three sizes. These are the
8 inch, 5.25 inch, and 3.5 inch. The 8 inch floppy disk is not used in present systems. These
days, the 5.25 inch and 3.5 inch are very popular. Also, the 3.5 inch floppy is replacing the 5.25
inch floppy in newer systems since it is smaller in size and does not bend easily. AU floppy disks
are provided with an off-center index hole that allows the electronic system reading the disk
to find the start of a track and the first sector.
Hard disk memory is also frequently used with microcomputer systems. The hard disk, also
known as the fixed disk, is not removable like the floppy disk.
A comparison of the some of the features associated with the hard disk and floppy disk is
provided below:

Characteristic Hard Disk Floppy Disk

Size 5 Mbytes to several Gbytes 1.2 Mbytes typical to r 5.25 inch tloppy.
1.44 Mbyte typical for 3.5 inch tloppy.
Rotational Speed 3600 rpm 300 rpm
Number of heads May have up to 8 disk surfaces with up to Two heads; One head for the upper surface
two heads per surface and the other head fo r the lower surface

Primary memory normaJiy includes ROM (Read-only Memory) and RAM (Random Access
Memory). As the name implies, a ROM permits only a read access. Some ROMs are custom
made, that is, their contents are programmed by the manufacturer. Such ROMs are called
mask programmable ROMs. Sometimes a user may have to program a ROM in the field. For
instance, in a fusible-link ROM, programmable read-only memory (PROM) is available. The
main disadvantage of a PROM is that it cannot be reprogrammed.
12 Microprocessors and Microcomputer-Based System Design, 2nd Edition

Some ROMs can be reprogrammed, these are called Erasable Programmable Read-Only
Memories (EPROMs).
In an EPROM, programs are entered using electrical impulses and the stored information
is erased by using ultraviolet rays. Usually an EPROM is programmed by inserting the EPROM
chip into the socket of a PROM programmer and providing program addresses and voltage
pulses at the appropriate pins of the chip. Typical erase times vary between I 0 and 30 minutes.
With advances in IC technology, it is possible to achieve an electrical means of erasure.
These new ROMs are called Electrically Alterable ROMs (EAROMs) or Electrically Erasable
PROMs (EEPROMs or £2PROMs) and these ROM chips can be programmed even when they
are in the circuit board. These memories are aJso caJled Read Mostly Memories (RMMs), since
they have much slower write times than read times. Random Access Memories (RAMs) are
read/write memories.
Information stored in random access memories will be lost if the power is turned off. This
property is known as volatility and, hence, RAMs are usually called volatile memories. RAMs
can be backed up by batteries for a certain period of time and are sometimes called nonvolatile
RAMs. Stored information in a magnetic tape or magnetic disk is not lost when the power is
turned off. Therefore, these storage devices are called nonvolatile memories. Note that a ROM
is a nonvolatile memory.
Some RAMs are constructed using bipolar transistors, and the information is stored in the
form of voltage levels in flip-flops. These voltage levels do not usually drift away, or decay. Such
memories are called static RAMs because the stored information remains constant for some
period of time.
On the other hand, in RAMs that are designed using MOS transistors, the information is
held in the form of electrical charges in capacitors. Here, the stored charge has the tendency
to decay. Therefore, a stored 1 would become a 0 if no precautions were taken. These memories
are referred to as dynamic RAMs. In order to prevent any information loss, dynamic RAMs
have to be refreshed at regular intervals. Refreshing means boosting the signal level and writing
it back. This activity is performed by a hardware unit called "refresh logic" which can either
be a separate chip or is contained in the microprocessor chip.
Since the static RAM maintains information in active circuits, power is required even when
the chip is inactive or in standby mode. Therefore, static RAMs require large power supplies.
Also, each static RAM cell is about four times larger in area than an equivalent dynamic cell;
a dynamic RAM chip contains about four times as many bits as a static RAM chip using the
same or comparable semiconductor technology. Figure 1.3 shows the subcategories of ROMs,
RAMs, and their associated technologies.

PRIMARY MEMORY

RAM ROM

Magneti c Semiconductor I
Bipolar MOS

II
Core

Static Dynamic Mask PROM Mask PROM EPROM

ROM ROM AND
EAR OM

FIGURE I .3 Subcategories of RAMs and ROMs .

 Introduction to Microprocessors and Microcomputer-Based Applications 13

Today, one megabit of data can be stored in an ordinary dynamic RAM chip. The data can
be accessed in 80 nanoseconds or less. The RAM chip costs $5. In contrast, it takes 150
nanoseconds to access a one-megabit EEPROM which costs $150. Sixteen megabit DRAMs are
very popular Lhese days at a price of approximately 0.3 millicent per bit. Recently, IBM,
Hitachi, Toshiba and others have introduced 64 mega-bit DRAMs. It is expected that giga-bit
DRAMs will not be introduced until the next century.
In the mid 1980s, Toshiba Semiconductor invented flash memory. About the same time,
Intel and Seeq Semiconductor were also working on flash memories. While each manufacturer
implemented its flash memory differently, they operate in a similar way.
Like EPROMs and EEPROMs or EAR OMs, flash memory is nonvolatile and reprogrammable.
Flash memory is fabricated by using ETOX II (EPROM Tunnel Oxide) technology which is a
combination of EPROM and EEPROM technologies. Flash memory is relatively inexpensive
compared to EEPROM. A one megabit flash memory costs about $15. Flash memory can be
reprogrammed electrically while embedded in the board. However, one can only change a
sector or a block (consisting of multiple bytes) at a time.
Flash memory cells contain a single transistor like the EPROM cell. In contrast, a DRAM cell
typically contains a transistor and a capacitor, an EEPROM cell contains two transistors while
a static RAM cell requires four or six transistors.
The non-volatility and DRAM-like speed of flash memory are ideal for solid-state "disk"
drives. Flash based disks do not have any disks or moving parts. Flash disks are very fast
compared to most available disk drives.
Data can be accessed in 120 nanoseconds in flash memories while it takes 15 to 30 millisec-
onds to access data stored in today's typical hard disk. However, flash disks are limited to up
to 40 megabytes in capacity whereas hard disk drives can store from 5 megabytes to several
gigabytes.
A flash disk can be built from one or more flash-memory IC chips and some controlling
logic devices. For example, to build a 512Kbyte flash disk, four one-megabit flash memory
chips can be connected on a smaU card. An example of such a flash memory system is the Intel
iMC004FLKA 4 Megabyte flash memory card. In addition to flash-disk hardware, software to
manage fLies on a flash disk is required. The file system software handles creating and deleting
files, changing the file sizes and formatting the flash disk. Microsoft offers flash file system
software for the MS-DOS operating system.
The most severe limitation of flash disks has been its cost. However, the cost of flash ROM
is significantly decreasing. In the future, high density flash memory is expected to be available
at an inexpensive cost.
Flash memory can be programmed using either 5V or 12V. The 5V feature becomes more
desirable for portable equipment where no 12V power is available. The speed, rugged con-
struction, and lower power consumption of flash disks is ideal for laptop and notebook
computers.
In summary, due to the high cost of flash disks, desktop computers will continue to use hard
disk drives. Since flash memory combines the advantages of an EPROM's low cost with an
EEPROM's ease of reprogramming, flash memories are being extensively used these days as a
microcomputer's main non-volatile memory. An example of flash memory is the Intel28F020
256K x 8 flash memory. By 1997, the cost of a megabyte of flash memory is expected to move
from its current level of $120 to about $5. At that time, flash disks will be able to replace hard
disks in many applications .

.3.3.b Main Memory Array Design

In many applications, a memory of large capacity is often realized by interconnecting several
small-size memory blocks. In this section, design of a large main memory using small-size
memories as building blocks is presented. The memory map defining all memory addresses is
determined. Note that the microprocessor's reset vector must be included in the memory map.
 14 Microprocessors and Microcomputer-Based System Design, 2nd Edition

There are three types of techniques used for designing the main memory. These are linear
decoding, full decoding/partial decoding and memory decoding using PALs. We will illustrate
the concepts associated with these techniques in the following.
First, consider the block diagram of a typicaJ static RAM chip shown in Figure 1.4.

A9- AO flO
I
- 1Kx8
WE
RAM chip 8/ .,.,. .... 07- DO
I .......
,....
cs

FIGURE 1.4 Typical Static RAM Chip.

The capacity of this chip is 8192 bits and these bits are organized as I 024 words with 8 bits/
word. Each word has a unique address and this is specified on !O-bit address lines A9-AO
(note that 2 10 = 1024). The inputs and outputs are routed through the 8-bit bidirectional data
lines D7 through DO. The operation of this chip is governed by the two control inputs: WE
(write Enable) and CS (chip select). The truth table that describes the operation of this chip
is shown in Table 1.1.

TABLE 1.1 Truth Table for I K x 8 Static RAM

cs WE MODE Status of 07-DO Power

L X Not selected High impedance Standby

H L Write Acts as an input bus Active
H H Read Acts as an output bus Active

Note: H- high, L - low, X - don't ca re.

From this table, it is easy to see that when CS input is low, the chip is not selected and thus
the lines D7 through DO are driven to the high impedance state. When CS = I and WE is LOW,
data on lines D7-DO are written into the word addressed by AO through A9. Similarly, when
CS = 1 and WE is high, the contents of the memory word (whose address is specified on
address lines A9 through AO) will appear on lines D7 through DO. Note that when the chip
select input CS goes to low, the device is disabled and the chip automatically reduces its power
requirements and remains in this low-power standby mode as long as CS remains low. This
feature results in system power savings as high as 85% in larger systems, where the majority
of devices are disabled.

l.J.J.b.i Linear Decoding. This technique uses the unused address Jines of the microprocessor as chip
selects for the memory chips. This method is used for small systems.
A simple way to connect an 8-bit microprocessor to a 6K RAM system using linear
decoding is shown in Figure 1.5. In this approac h, the address lines A9 through AO of the
microprocessor are used as a common input to each I K x 8 RAM ch ip. The remaining 6
high - order lin es are u sed to selec t one of the 6 RAM chips. For examp le, if
Al5Al4Al3AI2A11AIO = 000010, then the RAM chip l is selected. The address map
realized by this arrangement is summarized in Figure J .6. This method is known as the linear
select decoding technique. The principal adva ntage of this method is that it does not require
any decoding hardware. However, this approac h has some disadvantages:
 Introduction to Microprocessors and Microcomputer-Based Applications 15

• Although with a 16-bit address bus we have 64K bytes of RAM space, we are able to
interface only 6K bytes of RAM. This means that this idea wastes address space.
The address map is not contiguous; rather, it is sparsely distributed.
Ifboth All and AlO are high at the same time, both RAM chips 0 and 1 are selected and
thus a bus conflict occurs. This can be avoided by proper programming to select the
desired memory chip and deselect the others.
Also, if all unused address lines are not utilized as chip selects for memory, then these
unused pins become don't cares (can be 0 or 1). This results in foldback, meaning that
a memory location will have its image in the memory map. For example, if A15 is don't
care in design and if A14 to AO address lines are used, then address 0000 16 and address
8000 16 are the same locations. This is called foldback and it wastes memory space .

. 3.3.b.ii Full/Partial Decoding. Difficulties such as the bus conflict and sparse address distribution
are eliminated by the use of the full/partial decoded addressing technique. To see this, consider
the organization shown in Figure 1.7. In this setup, we use a 2-to-4 decoder and interface the
8-bit microprocessor with 4K bytes of RAM. In particular, the four combinations of the lines
All and AlO select the RAM chips as follows:
All AIO Device Selected
0 0 RAM chip 0
0 I RAM chip I
0 RAM chip 2
RAM chip 3

Also observe that this hardware makes sure that the memory system is enabled only when
the lines AlS through Al2 are zero. The complete address map corresponding to this organi-
zation is summarized in Figure 1.8 .

.3.3.b.iii Memory Decoding by using Programmable Array Logic (PAL). A Programmable

Array Logic (PAL) is similar to a ROM in concept except that it does not provide full decoding
of the input lines. Instead, a PAL provides a partial sum of products which can be obtained via
programming and saves a lot of space on the board. The PAL chip contains a fused program-
mable AND array and a fixed OR array. Note that in PLA (Programmable Logic Array) both
AND and OR arrays are programmable. The AND and OR gates are fabricated inside the PAL
without interconnections. The specific functions desired are implemented during program-
ming via software. Programming of the PAL provides connections of the inputs of the AND
gates and the outputs of the AND gates to the inputs of the OR gates. Therefore, the PAL
implements sum of products of the inputs. PALs are used extensively these days with 32-bit
microprocessors such as the Intel80386/80486 and Motorola 68030/68040 for performing the
memory decode function. PALs connect these microprocessors to memory, 1/0 and other
chips without the use of any additional logic gates or circuits.
Each input has both true and complemented forms. A look at the NOR gate output 0 1
indicates that there are two X connections at the inputs of this NOR gate. The three X inputs
are wire-ANDed together with programming the PAL so that 0 1 = ( 10 ·11) + 12 .
The PAL chips are usually identified by a two-digit number followed by a letter and then a
digit. The two-digit number specifies the number of input lines while the last digit defines the
number of output lines. The fixed number of AND gates are connected to either an OR or a
NOR gate. The letter 'H' indicates that the output gates are OR gates. The letter 'L' is used when
the outputs are NOR gates.
As an example, the 10H8 provides eight OR gate outputs driven by ten AND gate inputs. The
10L8, on the other hand, is the same as the 10H8 except that the eight output gates are NOR
gates.
 16 Microprocessors and Microcomputer-Based System Design. 2nd Edition

8- BIT MICROPROCESSO R B US

I A15A14A13A12A11 A10 A9 -AO R/W 07-00 I

RAM CHIP 0
10 (1 K x 8)

+----+-----1 A9-AO
07 - 00~~8~--4
+---I WE

~--~-+--~CS
'-----------'
RAM CHIP 1
(1 K X 8 )

+----+-----1 A9-AO
D7 -Do~~8;;<---4
+----I WE

~----+--,~-_, cs
'------------'
RAM C H IP 2
( 1 K X 8)

+----+----1 A9-AO
0 7 - 00~~8;<---4
+----I WE

'---------~-+--~CS
'------------'
RAM C HIP 3
(1 K x 8)

+----+-------1 A9-AO
D7-D0~~8,_--4
+----I WE

cs
RAM C HIP 4
(1 K x 8)

+----+-------1 A 9 -AO
D7-D0~~8~--~
+----!WE

' - - - - - - - - - - - - + - - + - - - - - - - 1 CLS
__ _ _ __ J

RAM C HIP 5
(1 K X 8)

'-----+----1 A9-AO 0 7 - DOI----;8,___ _

~wE

'------------------~cs
L _ __ _ _ _ _ J

FIGURE 1.5 An 8-bit microprocessor interfaced to a 6K RA.Ivl system using the linear select decoding technique.

Some PALs provide additional features. The l6L8 includes tristate outputs. Each of the eight
NOR gate outputs is driven internally by six AND gates. A seventh AND gate provides the
enable signal for the tristate buffers.
The 1618 is a popular PAL used with 32-bit microprocessors. The 16L8 is a 20-pin PAL
manufactured using bipolar transistors. It has ten input pins (labeled 1), hvo outputs (labeled
0) and six programmable Input/Output (labeled 110) Jines. Using the programmable I/0
lines, the number of input lines can be increased to a maximum of 16 and the number of
output lines can be increased to 8.
 Introduction to Microprocessors and Microcomputer-Based Applications 17

Device Address Assignment in Hex

Binary Address Pattern
Selected
A 15 A 14 A 13 A 12 A II A I 0 A9 A7 A6 AS A4 AJ A2 A I AO

0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 RAM 0400
CHIP to
0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 07FF
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 RAM 0800
CHIP to
0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 OBFF
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 RAM 1000
CHIP to
0 0 0 1 0 0 1 1 1 1 1 1 1 1 1 2 13FF
0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 RAM 2000
CHIP to
0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 3 23FF
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 RAM 4000
CHIP to
0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 4 43FF
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAM 8000
CHIP to
1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 5 83FF

FIGURE 1.6 Address map realized by the system shown in Figure 1.5.

Programming PALs can be accomplished by first creating a file by using a text editor o n a
personal computer. The file should include information such as the pin assignments of the
PAL and the boolean equation for the outputs. By inserting the PAL into the programming
module included with the personal computer, the PAL can then be programmed with the PAL
programming software provided with the personal computer.Note that PAL programmi ng
hardware and software are sold separately and not usually included with a personal compute r.

1.3.3.c Memory Management Concepts

Due to the massive amount of information that must be saved in most svs tems, the mass
storage is often a disk. If each access is to a disk (even a hard disk), then system throughput
will be reduced to unacceptable levels.
An obvious solution is to use a large and fast locally accessed semiconductor memory.
Unfortunately the storage cost per bit for this solution is very high. A combination of both off-
board disk (secondary memory) and on-board semiconductor main memory must be de-
signed into a system. This requires a mechanism to manage the two-way flow of information
between the primary (semiconductor) and secondary (disk) media. This mechanism must be
able to transfer blocks of data efficiently, keep track of block usage, and replace them in a
nonarbitrary way. The primary memory system must therefore be able to dynamically allocate
memory space.
An operating system must have resource protection from corruption or abuse by users.
Users must be able to protect areas of code from each other, while maintaining the ability to
communicate and share other areas of code. All these requirements indicate the need fo: 1
device, located bet\veen the microprocessor and memory, to control accesses, perform address
mappings, and act as an interface between the logical (programmer's memory) and micropro-
cessor physical (memory) address spaces. Since this device must manage memory use, it is
appropriately called the memory management unit (MM U) . Typical 32-bit microprocessors
such as Motorola 68030 and Intel 80386 include on-chip MMU.
The MMU reduces the burden of the memory management function on the operating
system.
The basic functions provided by the MMU are address translation and protection. The
MMU translates logical program addresses to physical memory addresses. The addresses in a
 18 Microprocessors and Microcomputer-Based System Design, 2nd Edition

8 - BIT MICROPROCESSOR BUS

110/M A15 A14A13A12A11 A10 A9-AO RfN D7-DO I

RAM CHIP 3
10 (1Kx8)

+--+---iA9-AO
D7 -DOt--...;&;o,.__-;

2to4 MUX INV -WE

74LS139 74LS04
~ G YJ p:-7----'-11 Z cs
Y2P%- RAM CHIP Z
3 B Y1~ (1Kx8)
r-2<:>: YO~
t--t---iA9-AO
07 -DOt--...;&;o,.__-;

INV -WE

•---+<; Inverters ~~04~4-+--+-~L~----~

8 RAM CHIP 1
(1Kx8)
+5 --,Wr-;-H7N:7"ANO
L...Lt: 74LS30 +---+-~ A9-AO 8
D7-DOt----71- ---+
INV

~~04~6--r_,__-Lc_s___~
RAM CHIP 0
(1Kx8)

~-~-~A9-AO
D7-DOJ---i'-'----~
8

INV '------WE
74LS04
~~,-~8_ _ _ _~LCS_____~

FIGURE 1.7 An 8-bit microprocessor interfaced to a 4K RAM system using a fuiUpartial decoded addressing
technique

Device
Binary Address Pallern Selected Address Assignm e nt in Hex
A 1S A 14 A 13 A 12 A 11 A 10 A9 A7 A6 AS A4 AJ A2 A 1 AO

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAM 0000
CH IP 10
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 03FF
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 RAM 0400
CHIP to
0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 07FF
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 RAM 0800
CHIP to
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 2 OBFF
0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 RAM ocoo
CHIP to
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 3 OFFF

FIGURE 1.8 Address map corresponding to the organization shown in Figure 1.7.
Introduction to Microprocessors and Microcomputer-Based Applications 19

lo-----1
~---r---+--~--~r---+----r-

12-----1
~---r---+--~--~r---+----r-

FIGURE 1.9 A typical PAL.

program are called logical addresses since they indicate the logical positions of instructions and
data. The MMU translates these logical addresses to physical addresses provided by the
memory chips. The MMU can perform address translation in one of two ways:
l. By using the substitution technique as shown in Figure l.lOa
2. By adding an offset to each logical address to obtain the corresponding physical address
as shown in Figure l.lOb
Address translation using substitution is faster than the offset method . However, the offset
method has the advantage of mapping a logical address to any physical address as determined
by the offset value.
Memory is usually divided into small manageable units. The terms "page" and "segment"
are frequently used to describe these units. Paging divides the memory into equal-sized pages,
while segmentation divides the memory into variable-sized segments.
It is relatively easier to implement the address translation table if the logical and main
memory spaces are divided into pages. The term "page" is associated with logical address
space, while the term "block" usually refers to a page in main memory space.
There are three ways to map logical addresses to physical addresses. These are paging,
segmentation, and combined paging/segmentation.
In a paged system, a user has access to a larger address space than physical memory provides.
The virtual memory system is managed by both hardware and software. Note that memory in
excess of the main memory such as floppy disk storage is called virtual memory. The hardware
included in the memory management unit handles address translation. The memory manage-
ment software in the operating system performs all functions including page replacement
policies in order to provide efficient memory utilization. The memory management software
performs functions such as removal of the desired page from main memory to accommodate
a new page, transferring a new page from secondary to main memory at the right instant of
time, and placing the page at the right location in memory.
20 Microprocessors and Microcomputer-Based System Design, 2nd Editior

Logical Logical

Address Address

Physical Physical

Address Adcir(·S~

FIGURE !.lOa Address translation using subst itution techn ique.

Logical Address - -- )o-1

Physical
" Address

OFFSET

FIGURE !.lOb Address translation by offset technique.

If the main memory is full during transfer from secondary to main memory, it is necessaf)
to remove a page from main memory to accommodate the new page. Two popular pagt
replacement policies are first -in first-out (FIFO) and least recently used (LRU) . T he FIFC
policy removes the page from main memory that has been resident in memory for the longesl
amount of time. The FIFO replacement policy is easy to implement. One of the main disad-
vantages of the FIFO policy is that it is likely to replace heavily used pages. Note that heavily
used pages are resident in main memory for the longest amount of time. Sometimes this
replacement policy might be a poor choice. For example, in a time-shared system, several users
normally share a copy of the text editor in order to type and correct programs. The FIFO policy
on such a system might replace a heavily used editor program page to make room for a new
page. This program page might be recalled to main memory immed iately. T he FIFO, in this
case, would be a poor choice.
The LRU policy, on the o ther hand, replaces that page which has not been used for the
longest amou nt of time.
In the segmentation method, the MMU utilizes the segment selector to obta in a descriptor
from a table in memory containing several descriptors. A descriptor contains the physical base
address for a segment, the segment's privilege level, and some control bits. When the MMU
obtains a logica l add ress from the microprocessor, it first determ ines whether the segment is
already in the physical memory. If it is, the MMU adds an offset component to the segment
base component of the address obtained from the segment descriptor table to provide the
physical address. The MMU then generates the physical address on the add ress bus for
accessing the memory. On the other hand, if the MMU does not find the logica l add ress in
physical memory, it interrupts the microprocessor. The microprocessor executes a service
routine to bring the desired program from a secondary memory such as disk to the physical
memory. T he MMU determines the physical address using the segment offset and descriptor
as above and then generates the physical address on the address bus fo r memory. A segment
will usually consist of an integral number of pages, say, each 256 bytes long. With diffe rent-
sized segments being swapped in and out, areas of valuable primary memory can become
unusable. Memory is unusable for segmentation when it is sandwiched between already
a llocated segments and if it is not large enough to hold the latest segment that needs to be
Introduction to Microprocessors and Microcomputer-Based Applications 21

loaded. This is called external fragmentation and is handled by MMUs using special tech-
niques. An example of external fragmentation is given in Figure 1.11. The advantages of
segmented memory management are that few descriptors are required for large programs or
data spaces, and internal fragmentation (to be discussed later) is minimized. The disadvan -
tages include external fragmentation, involved algorithms for placing data are required, pos-
sible restrictions on starting address, and longer data swap times are required to support
virtual memory.

ALLOCATED ~

FREE [==:J MEMORY

BLO K
REQU IRED

FIGURE 1.11 Memory fragmentation (ex tern al).

Address translation using descriptor tables offers a protection feature. A segment or a page
can be protected from access by a program section of a lower privilege level. For example, the
selector component of each logical address includes one or two bits indicating the privilege
level of the program requesting access to a segment. Each segment descriptor also includes one
or two bits providing the privilege level of that segment. When an executing program tries to
access a segment, the MMU can compare the selector privilege level with the descripto r
privilege level. If the segment selector has the same or higher privilege level, then the MM U
permits the access. If the privilege level of the selector is lower than the descriptor, the MM U
can interrupt the microprocessor informing of a privilege level violation. T herefore, the
indirect technique of generating physical address provides a mechanism of protecting critical
program sections in the operating system .
Paging divides the memory into equal-sized pages, it avoids the major problem of segmen-
tation-external fragmentation . Since the pages are of the same size, when a new page is
requested and an old one swapped out, the new one wiiJ always fit into the vaca ted space.
However, a problem common to both techniques remains- internal fragmentation . Interna l
fragmentation is a condition where memory is unused but allocated due to memory block size
implementation restrictions. This occurs when a module needs, say, 300 bytes and page is I K
bytes, as shown in Figure 1.12.
In the paged-segmentation method , each segment contains a num ber of pages. The logical
address is divided i.nto three components: segment, page, and word. The segment com ponent
defines a segment number, the page component defines the page within the segment, and the word
component provides the particular word \vi thin the page. A page co mponent of n bits can provide
up to 2" pages. A segment can be assigned with one or more pages up to a maximum of 2" pages;
therefore, a segment size depends on the number of pages assigned to it.
Protection mechanisms can operate either on physical address or logical address. Physical
memory protection can be accomplished by using one or more protection bits with each block
to define the access type permitted on the block. This means that each time a page is transferred
from one block to another, the block protection bits must be updated. A more efficient
approach is to provide a protection feature in logical address space by including protection bits
in the descriptors of the segment table in the MMU.
 22 Microprocessors and Microcomputer-Based System Design, 2nd Edition

PAGES=1 K
IF 300 BYTES NEEDED 1 K BYTES ARE ALLOCATED

-~
USED

MEMORY UNUSED BUT ALLOCATED BECAUSE OF 1 K

IMPLEMENTATION RESTRICTIONS ON BLOCK SIZES PAGE
UNUSED

1
BUT
ALLOCATED
-'----
FIGURE Ll2 Memory fragmentation (internal).

1.3.3.d Cache Memory Organization

The performance of a microcomputer system can be significantly improved by introducing a
small, expensive, but fast memory between the microprocessor and main memory. This
memory is called cache memory and this idea was first introduced in the IBM 360/85 com-
puter. Later on, this concept was also implemented in minicomputers such as PDP-11/70.
With the advent ofVLSI technology, the cache memory technique is gaining acceptance in the
microprocessor world. For example, an on-chip cache memory is implemented in Intel's 32-
bit microprocessor, the 80486, and Motorola's 32-bit microprocessors, the MC 68020/68030/
68040. The 80386 does not have on-chip cache but external cache memory can be interfaced
to it. Studies have shown that typical programs spend most of their execution times in loops.
This means that the addresses generated by a microprocessor have a tendency to cluster
around a small region in the main memory. This phenomenon is known as locality of
reference. The 32-bit microprocessor can execute the same instructions in a loop from the on-
chip cache rather than reading them repeatedly from the external main memory. Thus the
performance offered by 32-bit microprocessors is greatly improved.
The block diagram representation of a microprocessor system that employs an on-chip
cache memory is shown in Figure 1.13. Usually, a cache memory is very small in size and its
access time is less than that of the main memory by a factor of 5.
Cache hit means that the reference is found in the cache and the data pertaining to the
microprocessor reference is transferred to the microprocessor from the cache. However, if the
reference is not found in the cache, we call it a cache miss. When there is a cache miss, the main
memory is accessed by the microprocessor and the data are then transferred to the mrcropro-
cessor from the main memory. At the same time, a block of data containing the desired data
needed by the microprocessor is transferred from the main memory to the cache. The block
normally contains 4 to 16 bytes, and this block is placed in the cache using the standard
replacement policies such as FIFO (First-In First-Out) or LRU (Least Recently Used). This
block transfer is done with a hope that all future references made by the microprocessor will
be confined to the fast cache.
The relationship between the cache and main memory blocks is established using mapping
techniques. Three widely used mapping techniques are
Direct mapping
Fully-associative mapping
Set-associative mapping
In direct mapping, the main memory address is divided into two fields: an index field and
a tag field. The number of bits in the index field is equal to the number of address bits required
to access the cache memory.
Assume that the main memory address is m bits wide and the cache memory address is n
bits wide. Then the index field requires n bits and the tag field is (m - n) bits wide. The n-
Introduction to Microproce'isors and Microcumputer-Bascd Applications 23

-----1
Microprocessor
I
I_------

-
On-chip
Internal to the cache
mi< roprocessor memory
chip
I
--F-------J
,----L---'--;

Main Memory

FIGURE 1.13 Memory Or[\anization of a computer sy,tern that employ' a cache memory.

bit address accesses the code. Ea€h word in the cache includes the data word and its associated
tag. When the microprocessor generates an address for main memory, the index field is used
as the address to access the cache. The tag field of the main memory is compared with the tag
field in the word read from cache. A hit occurs if the tags match. This means that the desired
data word is in cache. A miss occurs if there is no match, and then the required word is read
from main memory. It is written in the cache along with the new tag. A random access memory
is used as the cache memory.
One of the main drawbacks of direct mapping is that numerous misses may occur if two or
more words with addresses having the same index but ditferent tags are accessed several times.
This can be minimized by incorporating a larger cache.
The fastest cache memory utilizes an associative memory. The method is known as fully
associative mapping. Each associative memory content contains main memory address and its
content (data). \Vhen the microprocessor generates a main memory addre~'>, it is compared
associatively (simultaneously) with all addresses in the associative memory. If there is a match,
the corresponding data word is read from the associative cache memory and sent to the
microprocessor. If a miss occurs, the main memory is accessed, and the address and its
corresponding data are written to the associative cache memory. If the cache is fuiJ, certain
policies such as FIFO (first-in first-out) are used as replacement algorithm for the cache. The
associative cache is expensive but provides fast operation.
The set-associative mapping is a combination of direct and associative mapping. Each cache
word stores two or more main memory words using the same index address. Each main
memory word consists of a tag and its data word. An index with two or more tags and data
words forms a set. When the microprocessor generates a memory request, the index of the
main memory address is used as the cache address. The tag field of the main memory address
is then compared associatively (si multaneously) with all tags stored under the index. If a match
occurs, the desired data word is read. If a miss occurs, the data word, along with its tag, is read
from main memory and also written into the cache. The hit ratio improves as the set size
increases. This is because more words with the same index but different tags can be stored in
cache.
There are two ways of writing into cache: the write-back and write-through methods. In the
write-back method, whenever the microprocessor writes something into a cache word, a dirty
bit is assigned to the cache word. When a dirty word is to be replaced with a new word, the
 24 Microprocessors and Microcomputer-Based System Design , 2nd Edition

dirty word is first copied into the main memory before it is overwritten by the incoming new
word . The advantage of this method is that it avoids unnecessary writing into main memory.
In the write-through method, whenever the microprocessor alters cache data, the same
alteration is made in the main memory copy of the altered cache data. This policy can be easily
implemented and also it insures that the contents of the main memory are always valid. This
feature is desirable in a multiprocessor system where the main memory is shared by several
processors. However, this approach may lead to several unnecessary writes to main memory.
One of the important aspects of cache memory organization is to devise a method that
insures proper utilization of the cache. UsuaUy, the tag directory contains an extra bit for each
entry. This additional bit is called a valid bit. When the power is turned on, the valid bit
corresponding to each cache block entry of the tag directory is reset to zero. This is done in
order to indicate that the cache block holds invalid data. When a block of data is first
transferred from the main memory to a cache block, the valid bit corresponding to this cache
block is set to l. In this arrangement, whenever the valid is a zero, it implies that a new
incoming block can overwrite the existing cache block. Thus, there is no need to copy the
contents of the cache block being replaced into the main memory.

1.3.4 Input/Output {1/0)

This section describes the basic input and output techniques used by microcomputers to
transfer data between the microcomputer and external devices. The general characteristics of
1/0 are described. One communicates with a m icrocomputer system via the 1/0 devices
interfaced to it. The user can enter programs and data using the keyboard on a terminal and
execute the programs to obtain results. Therefore, the 1/0 devices connected to a microcom-
puter system provide an efficient means of communication between the computer and the
outside world . These 1/0 devices are commonl y called peripherals a nd include keyboards, CRT
displays, printers, and disks.
The characteristics of the 1/0 devices are normally different from those of the microcom-
puter. For example, the speed of operation of the peripherals is usually slower compared to the
microcomputer, and the word length of the microcomputer may be different from the data
format of the peripheral device. To make the characteristics of the 1/0 devices compatible with
those of the microcomputer, interface hardwa re circuitry between the microcomputer and II
0 devices is necessary.
In a typical microcomputer system, the user gets involved with two types of 1/0 devices:
physical I/0 and logical 1/0. When the microcomputer has no operating system, the user must
work directly with physical 1/0 devices and perform detailed 1/0 design.
T here are three ways of transferring data between the microcomputer and a physical 1/0
device:

Programmed 1/0
Interrupt d riven I/0
Direct memory access (DMA)

The microcomputer executes a program to communicate with an external device via a

register ca lled the 1/0 port for programmed J/0.
An external device requests the microcomputer to tra nsfer data by act ivating a signal on the
microcomputer's interrupt line during interrupt 1/0. In response, the microcomputer ex-
ecutes a program called the interrupt-service routine to carry out the functio n desired by the
external device, again by way of one or more 1!0 ports.
Data transfer between the microcomputer's memory and an external device occurs without
microprocesso r involvement with direct mem ory access.
 Introduction to Microprocessors and Microcomputer,Based Applications 25

For a microcomputer with an operating system, the user works with virtual 1/0 devices. The
user does not have to be familiar with the characteristics of the physical 1/0 devices. Instead,
the user performs data transfers between the microcomputer and the physical 1/0 devices
indirectly by calling the J/0 routines provided by the operating system using virtual 1/0
instructions. This is called logical I/0 .

.3.4.a Programmed I/0

As described earlier, the microcomputer communicates with an external device via one or
more registers called 1/0 ports using programmed 1/0. These 1/0 ports are occasionally
fabricated by the manufacturer in the same chip as the memory chip to achieve minimum chip
count for small system applications. For example, the Intel 8355/8755 contains 2K bytes of
ROM/EPROM with two 1/0 ports. The Motorola 6846 has 2K bytes of ROM and an 8-bit I/
0 port.
1/0 ports are usually of two types . For one type, each bit in the port can be individually
configured as either input or output. For the other type, all bits in the port can be set up as
either all parallel input or output bits. Each port can be configured as an input or output port
by another register called the command, or data-direction register. The port data register
contains the actual input or output data. The data-direction register is an output register and
can be used to configure the bits in the port as inputs or outputs.
Each bit in the port can usually be set up as an input or output by respectively writing a 0
or a I in the corresponding bit of the data-direction register (ODR). A bidirectional buffer
(one input buffer and one output buffer) is connected at each bit of the port. A' l' written to
a particular bit in ODR enables the output buffer while a '0' enables the input buffer cor:nected
at the corresponding bit of the port. As an example, if an 8-bit data-direction register contains
3416> then the corresponding port is defined as foUows:

7 6 5 4 3 2 0 Bir posirion

0 0 0 0 0 Data -di recrion

rcg1src r

1/ 0 porr

i i 1 1 i 1 i T

In the preceding example, since 34 16 (00 11 0 1002 ) is sent as an output into the data-direction
register, bits 0, I, 3, 6, and 7 of the port are set up as inputs, and bits 2, 4, and 5 of the port
are defined as outputs. The microcomputer can then send outputs to external devices, such as
LEOs, connected to bits 2, 4, and 5 through a proper interface. Similarly, the microcomputer
can input the status of external devices, such as switches, through bits 0, I, 3, 6, and 7. To input
data from the input switches, the 8-bit microcomputer assumed here inputs the complete byte,
including the bits to which LEOs are co nnected. While receiving input data from .m 1/0 port,
however, the microcomputer places a value, probably 0, at the bits configured as outputs and
the program must interpret them as "don't cares" . At the same time, the microcomputer's
outputs to bits configured as inputs are disregarded .
For parallel I/O, there is only one register, known as the command register, for all ports. A
particular bit in the command register configures all bits in a port as either inputs or outputs.
Consider two 1/0 ports in an 1/0 chip along with one command register. Ass ume that a 0
or a 1 in a particular bit position defines all bits of ports A or B as inputs or outputs.
 26 Microprocessors and Microcomputer-Based System Design, 2nd Edition

For example,

OtJ1cr control information

such as timer control signals

7 2 1 0

I ~-- --- I I 0 I 1 I Command register

~------~1 ~~~

E- - - - -I IP~rt
7 0 7 0
I E- - - - - - -1 IP~rt
f --- -----=-t }- -- - --- -~
Input Devices Output Devices

Some I/0 ports are caJJed handshake ports. Data transfer occurs via these ports through
exchanging of control signals between the 1/0 controller and an external device.

1.3.4.b Standard 1/0 Versus Memory-Mapped 1/0

1/0 ports are addressed using either standard 1/0 or memory-mapped 1/0 techniques. The
standard 1/0, also called isolated I/0, uses the 10/M control pin on the microprocessor chip.
The processor outputs a HIGH on this pin to indicate to memory and the 1/0 chips that an
1/0 operation is taking place. A LOW output from the processor to this pin indicates a memory
operation. Execution of IN or OUT instructions makes the 10/M HIGH, whereas memory-
oriented instructions, such as LDA and STA, drive the 10/M to LOW. In standard 1/0, the
processor uses the 10/M pin to distinguish between 1/0 and memory. For 8-bit microproces-
sors, an 8-bit address is typically used for each I/0 port. This is because 8 bits are the basic data
unit for these processors. Eight-bit processors are usually capable of directly addressing 64K
bytes of memory using 16 address Jines. With an 8-bit 1/0 port address, these processors are
capable of addressing 256 ports. However, in a typical application, there are usually four or five
I/0 ports required. Some of the address bits of the microprocessor are normally decoded to
obtain the I/0 port addresses. With memory-mapped 1/0, the processor does not differentiate
between I/0 and memory and, therefore, does not use the microprocessor's !0 / M control
pin. The microprocessor uses the memory add resses (which may not exist in the
microcomputer's physical memo ry) to represent I/0 ports. The 1/0 ports are mapped into the
microprocessor's main memory and, hence, are called memory-mapped 1/ 0.
In memory-mapped I/0, the most significant bit (MSB) of the address may be used to
distinguish between 1/0 and memory. If the MSB of address is I, an I/0 port is selected. If the
MSB of address is 0, a memory location is accessed. This reduces the microprocessor's
addressing memory (main memory) by 50%. Sixteen and thirty-two bit microprocessors
provide special control sign als for performing memory-mapped 1/0. Thus, these processors
do not use MSB of the address lines. Intel microprocessors can use either standard or memory-
mapped I/0 while Motorola microprocessors use only memory-mapped 1/0. For example,
with standard 1/0, Intel 8086 uses IN AL, PortA, and OUT PortA, AL for inputing and
outputing data. On the other hand, the 8086 uses memory-oriented instructions such as MOV
AL, START, and MOV START, AL for inputing and outputing data. Note that START is an
 Introduction to Microprocessors and Microcomputer-Based Applications 27

I/0 port mapped as a memory address. Motorola, on the other hand, does not have any IN or
OUT instructions and uses memory-oriented instructions for I/0 operation .

.. 3.4.c Unconditional and Conditional Programmed 1/0

The microprocessor can send data to an external device at any time during unconditional II
0 . The external device must always be ready for data transfer. A typical example is when the
processor outputs a 7-bit code through an 1/0 port to drive a seven-segment display connected
to this port.
In conditional I/O, the microprocessor outputs data to an external device via handshaking.
Data transfer occurs by the exchanging of control signals between the microprocessor and an
external device. The microprocessor inputs the status of the external device to determine
whether the device is ready for data transfer. Data transfer takes place when the device is ready.
The concept of conditional I/O wiU now be demonstrated by means of data transfer between
a microprocessor and an analog-to-digital (A/D) converter. Consider, for example, the AID
converter shown in the accompanying figure.

Vx

START
conversion t 07
, 06
05
8-bit
BUSY 8-bit 04 tri-state
(end of conversion )
... Tri-state
ND converter 03
digital
output
"' 02
ou TPUT ENABLE Dl
DO

The AID converter just shown transforms an analog voltage Vx into an 8-bit binary output
at pins 07-00. A pulse at the START conversion pin initiates the conversion. This drives the
BUSY signal LOW. The signal stays LOW during the conversion process. The BUSY signal goes
HIGH as soon as the conversion ends. Since the ND converter's output is tristated, a LOW
o n the (OUTPUTENABLE) transfers the converter's output. A HIGH on the
(OUTPUT ENABLE) drives the converter's output to a high impedance state.
The concept of conditional I/O can be demonstrated by interfacing the ND converter to an
8-bit processor. Figure 1.14 shows such an interfacing example.
The user writes a program to carry out the conversion process. When this program is
executed, the processor sends a pulse to the START pin of the converter via bit 2 of port A. The
microprocessor then checks the BUSY signal by bit 1 of port A to determine if the conversion
is completed . If the BUSY signal is HIGH (i ndicating the end of conversion), the micropro-
cessor sends a LOW to the (OUTPUT ENABLE) pin of the AID converter. The microproces-
sor then inputs the converter's 00-07 outputs via port B. If the conversion is not completed ,
the microprocessor waits in a loop checking for the BUSY signal to go HIGH .

..3.4.d Typical Microcomputer Output Circuit

The microcomputer designer is often concerned with the output circuit because of the
microcomputer's small output current drive capability. The tristate output circuit shown in
Figure 1.15 typically is utilized by a microcomputer as the output circuit. This circuit uses
totem pole-type output called a PUSH-PULL circuit providing low-output currents. There-
fore, a current amplifier (buffer) is required to drive devices such as LEOs.
28 Microprocessors and Microcomputer-Ba sed System Design, 2nd Edition

Vx

~
Bit 0 OUTPUT ENABLE
Port A Bit 1 BU SY

..
Bit 2 START

.. ...
Bit 7 07
Port B

Bit 0 DO
Processor ND Con verter

FIGURE 1.14 Interfacing a n A/ D converter to an 8-bit processor.

+5 v

Q, I~ ~

r
Microprocesso r output

Q, 1

~
FIGURE 1.15 Digital microprocessor output circuit.

In the preceding figure, when Q1 is ON , Q 2 is OFF and I,;nk will flow from the external device
into Q 1• Also, when Q 2 is ON, Q 1 is OFF and ! so urce will flow from Q 2 into the output device.
Figure 1.16 shows a hardware interface circuit using the push-pull circuit for driving an
external device such as LED.
Assume ! so urce to be 400 ~A (usually represented by a negative sign such as ! 0 H = -400 ~;
the negative sign indicates that the chip is losing current) with a minimum voltage VAof 2.4
at point A, and that the LED requires lOrnA at 1. 7 V. Therefore, a buffer such as a transistor
is required at the output circuit to increase the current drive capabiJity to drive the LED. In
order to design the interface, the values of R1,R 2 and minimum ~ of the tra nsistor will be
determined in the following:

R =vA - v BE(Q J) 2.4- 0 ' 7 = 4.25 ill

I 4001J.A 4001J.A

Since lu 11 = 10 IJ.A at 1.7 V and assuming that VeE (saturation) = 0 V,

5-l.7-V CE(Q 3 ) 3.3

R2 = = - - =3 30 Q
lOrnA lOrnA
 Introduction to Microprocessors and Microcomputer-Based Applications 29

-5 v
r--------------,
+5 v ~R 2
--.-----02--,1 ~ \ ' ~"'co ~LED
VA~

I
:~Buffer
_ _ _ _ _ _ _ _ __.l I
- _J

~Microprocessor output circuit

FIGURE L16 Microprocessor 1/0 interfaces for driving an LED.

Since I,ourcc = 400 ~A = 18 (Q 3), ~ for transistor Q 3 is

Therefore, the interface design is complete, and a transistor with a mimimum of saturation ~
of25 and R1 = 4.25 kQ and R2 = 330 Q is required. Note that aMOS outputs more sink current
than source current. If sink current is used, the LED in Figure 1.16 can directly be connected
to the microcomputer's output through an appropriate resistance. However, if the resistor
value is not large enough, it may damage the transistor Ql.

1.3.4.e Interrupt Driven 1/0

A disadvantage of conditional programmed I/0 is that the microcomputer needs to check
the status bit (BUSY signal for the AID converter) by waiting in a loop. This type ofl /0 transfer
is dependent on the speed of the external device. For a slow device, this waiting m ay slo w do wn
the capability of the microprocessor to process other data. The polled I/0 and interru pt 1/0
techniques are efficient in this type of situation.
Interrupt 1/0 is a device-initiated 1/0 transfer. The external device is connected to a pin
called the interrupt (INT) pin on the microprocessor chip. When the device needs an 1/0
transfer with the microcomputer, it activates the interrupt pin of the microprocesso r chip. The
microcomputer usually completes the current instruction and saves at least the contents of the
current program counter on the stack.
The microcomputer then automatically loads an address into the program coun ter to
branch to a subroutine-like program called the interrupt-service rou tine. T his program is
written by the user. The external device wants the microcomputer to execute th is p rogram to
transfer data. The last instruction of the service routine is a RET URN, which is typ ically the
same instruction used at the end of a subroutine. This instruction normally loads the return
address (saved in the stack before going to the service routine) in the program counter. Then,
the microcomputer continues executing the main program . Note that subroutines and inter-
rupts are handled in a similar way: subroutines are initiated via execution of an instruction
such as subroutine CALL while interrupts are initiated via activation of the microprocessor's
interrupt pin by the interrupting device.
 30 Microprocessors and Microcomputer-Based System Design, 2nd Edition

1.3.4.e.i Interrupt Types. There are typically three types of interrupts: external interrupts, traps or
internal interrupts, and software interrupts.
External interrupts are initiated through the microcomputer's interrupt pins by external
devices such as AID converters. External interrupts can further be divided into two types:
maskable and nonmaskable. A maskable interrupt is enabled or disabled by executing instruc-
tions such as EI or DI. If the microcomputer's interrupt is disabled, the microcomputer
ignores the maskable interrupt. Some microprocessors, such as the Intel 8086, have an inter-
rupt-flag bit in the processor status register. When the interrupt is disabled, the interrupt-flag
bit is I, so no maskable interrupts are recognized by the processor. The interrupt-flag bit resets
to zero when the interrupt is enabled.
The nonmaskable interrupt has higher priority than the maskable interrupt. Ifboth maskable
and nonmaskable interrupts are activated at the same time, the processor will service the
nonmaskable interrupt first. The nonmaskable interrupt is typically used as a power failure
interrupt. Microprocessors normally use +5 V DC, which is transformed from llO V AC. If
the power falls below 90 V AC, the DC voltage of +5 V cannot be maintained. However, it will
take a few milliseconds before the AC power can drop this low (below 90 V AC). In these few
milliseconds, the power failure-sensing circuitry can interrupt the microprocessor. An inter-
rupt service routine can be vrritten to store critical data in nonvolatile memory such as battery-
backed CMOS RAM. The interrupted program can continue without any loss of data when the
power returns.
Some microprocessors are provided with a maskable handshake interrupt. This interrupt is
usually implemented by using two pins- INTR and INTA. When the INTR pin is activated
by an external device, the processor completes the current instruction, saves at least the current
program counter onto stack, and generates an interrupt acknowledge ( INTA) . In response to
the !NTA, the external device provides an instruction, such as CALL, using external hardware
on the data bus of the microcomputer. This instruction is then read and executed by the
microcomputer to branch to the desired service routine.
Internal interrupts, or traps, are activated internally by exceptional conditions such as
overflow, division by zero, or execution of an illegal op-code. Traps are handled the same way
as external interrupts. The user writes a service routine to take corrective measures and provide
an indication to inform the user that an exceptional condition has occurred.
Many microprocessors include software interrupts, or system calls. When one of these instruc-
tions is executed, the microprocessor is interrupted and serviced similarly to external or internal
interrupts. Software interrupt instructions are normally used to call the operating system. These
instructions are shorter than subroutine calJs, and no calling program is needed to know the
operating system's address in memory. Software interrupt instructions allow the user to switch
from user to supervisor mode. For some microprocessors, a sofu...,are interrupt is the only way
to call the operating system, since a subroutine call to an address in the operating system is not
allowed.

1.3.4.e.ii Interrupt Address Vector. The technique used to find the starting address of the service
routine (commonly known as the interrupt address vector) varies from one microprocessor to
another. With some microprocessors, the manufacturers define the fLXed starting address for
each interrupt. Other manufacturers use an indirect approach by defining fLXed locations
where the interrupt address vector is stored.

1.3.4.e.iii Saving tlte Microprocessor Registers. When a microprocessor is interrupted, it saves at

least the program counter on the stack so the microprocessor can return to the main program
after executing the service routine . Some microprocessors save only one or two registers, such
as the program counter and status register. Some other microprocessors save all microproces-
sor registers before going to the service routine. The user should know the specific registers the
 Introduction to Microprocessors and Microcomputer-Bast:d Applications 31

microprocessor saves prior to executing the service routine. This wilJ enable the user to use the
appropriate return instruction at the end of the service routine to restore the original condi-
tions upon return to the main program.

1.3.4.e.ivlnterrupt Priorities. A microprocessor is typically provided with one or more interrupt pins
on the chip. Therefore, a special mechanism is necessary to handle interrupts from several
devices that share one of these interrupt lines. There are two ways of servicing multiple
interrupts: polled and daisy chain techniques.
Polled interrupts are handled by software and therefore are slower when compared with
daisy chaining. The processor responds to an interrupt by executing one general service
routine for aU devices. The priorities of devices are determined by the order in which the
routine polls each device. The processor checks the status of each device in the general service
routine, starting with the highest-priority device to service an interrupt. Once the processor
determines the source of the interrupt, it branches to the service routine for the device.
In a daisy chain priority system, devices are connected in a daisy chain fashion to set up a
priority system. Suppose one or more devices interrupt the processor. In response, the proces-
sor pushes at least the PC and generates an interrupt acknowledge ( INTA) signal to the
highest-priority device. If this device has generated the interrupt, it will accept the INT A.
Otherwise it \'.ill pass the INTA onto the next device until INTA is accepted. Once accepted,
the device provides a means for the processor to find an interrupt address vector by using
external hardware. The daisy chain priority scheme is based on mostly hardware and is
therefore faster than the polled interrupt.

1.3.4.f Direct Memory Access (DMA)

Direct Memory Access (DMA) is a technique that transfers data between a microcomputer's
memory and an 1/0 device without involving the microprocessor. DMA is widely used in
transferring large blocks of data between a peripheral device and the microcomputer's memory.
The DMA technique uses a DMA controller chip for the data-transfer operation. The main
functions of a typical DMA controller are summarized as follows:
The 1!0 devices request DMA operation via the DMA request lines of the controller
chip.
The controller chip activates the microprocesso r HOLD pin, requesting the CPU to
release the bus.
The processor sends HLDA (hold acknowledge) back to the DMA controller, indicating
that the bus is disabled. The DMA controller places the current value of its internal
registers, such as the address register and counter, on the system bus and sends a DMA
acknowledge to the peripheral device. The DMA controller completes the DMA transfer
and releases the buses.
There are three basic types of DMA: block transfer, cycle stealing, and interleaved DMA.
For block-transfer DMA, the DMA controller chip takes the bus from the microcomputer
to transfer data between the memory and 1/0 device. The microprocessor has no access to the
bus until the transfer is completed. During this time, the microprocessor can perform internal
operations that do not need the bus. This method is popular with microprocessors. Using this
technique, blocks of data can be tra nsfe rred.
Data transfer between the microco m puter memory and an l/0 device occurs on a word-
by-word basis with cycle stea ling. Typ ica lly, the microprocessor clock is enabled by ANDing
an INHIBIT signal with the system clock. T he system clock has the same frequency as the
microprocessor clock.
The DMA controller controls the JNH IBIT line. During normal operation, the INHIBIT line
is HIGH, providing the microprocessor clock. When DMA operation is desired, the controller
 32 Microprocessors and Microcomputer-Based System Design, 2nd Edition

makes the INHIBIT line LOW for one clock cycle. The microprocessor is then stopped
completely for one cycle. Data transfer between the memory and l/0 takes place during this
cycle. This method is called cycle stealing because the DMA controller takes away or steals a
cycle without microprocessor recognition. Data transfer takes place over a period of time.
With interleaved DMA, the DMA controller chip takes over the system bus when the
microprocessor is not using it. For example, the microprocessor does not use the bus while
incrementing the program counter or performing an ALU operation. The DMA controller
chip identifies these cycles and allows transfer of data between the memory and l/0 device.
Data transfer takes place over a period of time for this method.
The DMA controller chip usually has at least three registers normally selected by the
controller's register select (RS) line: an address register, a terminal count register, and a status
register. Both the address and terminal count registers are initialized by the micro processor.
The address register contains the starting of the data to be transferred, and the term inal count
register contains the desired block to be transferred. The status register contains information
such as completion of DMA transfer.
It should be mentioned that while using either block transfer or cycle stealing DMA in
systems with dynamic RAMs, circuitry must be included for refreshing the dynamic RAM's
during DMA transfer.

1.3.4.g Summary of Microcomputer 1/0 Methods

Figure 1.17 summarizes the 1/0 structure (explained so far) of typical microcomputers.

1/0

Physical I/O Logical I/O

Programmed 1/0 Interrupt 1/0 Direct Memory Access

(DMA)
I
I
Standard 1/0 Memory- Cycle Stealing
or Mapped 1/0 Block Transfer Interleaved
Isolated 1/0
or
Port 1/0 External Internal
I I
Maskable Non-maskable Due to Software
(can be (cannot be exceptional such as
enabled enabled or conditions TRAP
or disabled disabled by instructions
by instructions) instructions)

FIGURE 1.17 1/0 structure of a typical microcomputer.

1.3.4.h Coprocessors
In typical 8-bit microprocessors such as the Intel 8085, technology places a limit on the chip
area. As a consequence, these microprocessors include no hardware or firmware for perform-
ing scientific computations such as floating-point arithmetic, matrix manipulation, and graphic-
data processing. Therefore, users of these systems must write these programs. Unfortunately,
Introduction to Microprocessors and Microcomputer-Based Applications 33

this approach is unacceptable in high-speed applications, since program execution takes a

significant amount of time. To eliminate this problem, coprocessors are used .
In this approach, a single chip is built for performing scientific computations at high speed.
However, the chip is regarded as a companion to the original or host microprocessor. Typi-
cally, each special operation is encoded as an instruction that can be interpreted only by the
companion processor. When the companion processor encounters one of these special in-
structions, it assumes the processing functions independent of the host microprocessor. The
companion processor that operates in this manner is called the coprocessor. Therefore, this
concept not only extends the capabilities of the host microprocessor, but also increases the
processing rate of the system. The coprocessor concept is widely used with typical 32-bit
microprocessors such as the Motorola 68020 and Intel 80386.
It is important to make the distinction between standard peripheral hardware and a
coprocessor. A coprocessor is a device that has the capability of communicating with the main
processor through the protocol defined as the coprocessor interface. As mentioned before, the
coprocessor also adds additional instructions, registers, and data types that are not directly
supported by the main microprocessor. The coprocessor provides capabilities to the user
without appearing to be hardware external to the main microprocessor.
Standard peripheral hardware, on the other hand, is generally accessed through the use of
interface registers mapped into the memory space of the main processor. The programmer
uses standard processor instructions to access the peripheral interface registers and thus utilize
the services provided by the peripheral. It should be pointed out that even though a peripheral
can provide capabilities equivalent to a coprocessor for many applications, the programmer
must implement the communication protocol between the main microprocessor and the
peripheral necessary to use the peripheral hardware. Two main techniques may be used to pass
commands to a coprocessor. These are intelligent monitor interface and coprocessors using
special signals.
In the intelligent monitor inteiface, the coprocessor monitors the instruction stream by obtaining
commands directly from the bus at the same time as the main microprocessor. The Intel 80387
floating-point coprocessor is of this type, as it monitors the instruction stream simultaneously with
a main microprocessor such as the Intel 80386. This has the obvious advantage of requiring no
additional bus cycles to pass the content of the instruction word to the coprocessor. One of the main
disadvantages of this approach is that each coprocessor in the system must duplicate the bus
monitoring circuitry and instruction queue, tracking all branches, wait states, operand fetches, and
instruction fetches.
In the second type, the coprocessor may be explicitly addressed by certain instructions,
which initiate a special sequence of microinstructions in the main microprocesso r to effect
command and operand transfer.
In this approach, when the main microprocessor executes a coprocessor instruction, it
decodes the instruction and writes a command in the command register (one of the interface
registers) specifying the operation required by the coprocessor. In response, the coprocessor
writes data back in a register called the response register (one of the interface registers) . The
main microprocessor can read these data, and it tells the main microprocessor certain infor-
mation such as whether additional information is required by the coprocessor to carry out the
operation. If such data are required, the main microprocessor provides this; otherwise, the
coprocessor carries out the operation concurrently with the main microprocessor and pro-
vides the result .
An advantage of this approach is that no special signals are required for the coprocessor
interface.
One of the main disadvantages of this method is that once the main processor detects a
coprocessor instruction, the main has to use bus bandwidth and timing to transmit the
command to the appropriate coprocessor. The Motorola 68881 (floating-point coprocessor)
is of this type.
 34 Microprocessors and Microcomputer-Based System Design, 2nd Edition

Note that state-of-the-art 32-bit microprocessors such as the Intel 80486 and the Motorola
68040 implement coprocessor hardware such as floating point hardware and MMU on the
microprocessor chip.

1.4 Microcomputer System Software and Programming Concepts

In this section, the basic concepts associated with system software and programming will be
discussed.

1.4.1 System Software

Typical microcomputer system software provided in microcomputer development systems
such as the HP64000 includes editors, assemblers, compilers, interpreters, debuggers, and an
operating system.
The editor is used to create and change source programs. Source programs can be written
in assembly language or a high-level language such as Pascal. The editor has commands to
change, delete, or insert lines or characters. The text editor is a special type of editor that is used
to enter and edit text in a general-purpose computer, whether the text is a report, a Jetter, or
a program.
An assembler translates a source text that was created using the editor into a target machine
language in object code (binary).
High-levellanguages contain English-like commands that are readily understandable by the
programmer. High-level languages normaUy combine a number of assembly-level statements
into a single high-level statement. A compiler is used to translate the high-level languages such
as Pascal into machine language. The advantage of high-level languages over assembly lan -
guage are ease of readability and maintainability.
Like a complier, an interpreter usually processes a high-level language program. Unlike a
compiler, an interpreter actuaUy executes the high-levellanguage program one statement at a
time, rather than translating the whole program into a sequence of machine instructions to be
run later.
The debugger provides an interactive method of executing and debugging the user's soft-
ware, one or a few instructions at a time, allowing the user to see the effects of small pieces of
the program and thereby isolate programming errors.
An operating system performs resource management and human-to-machine translation
functions. A resource may be the microprocessor, memory, or an I/0 device. Basically, an
operating system is another program that tells the machine what to do under a variety of
conditions. Major operating system functions include efficient sharing of memory, 1/0 pe-
ripherals, and the microprocessor among several users. An operating system is
I. The interface between hardware and users
2. The manager of system resources in accordance with system policy to achieve system
objectives
Operating systems for microcomputers became available when microcomputers moved
from process control applications to the general -pu rpose computer applications. It was
appropriate to write a process control program in asse mbly language because the microcom -
puter was required to perform dedicated real-time control fun ctions. But when the micro-
computers evolved to the point of controlling several 1/0 devices (disks, printers), an
organized operating system was needed.
Note that many laboratory trai ners such as the Intel SDK-86 include primitive operating
systems called monitors to provide functions such as keyboard/display interfaces and program
debugging features.
 Introduction to Microprocessors and Microcomputer-Based Applications 35

1.4.2 Programming Concepts

In general, programs are developed using assembly and high-level languages.

1.4.2.a Assembly Language Programming

Program designers realized the importance of symbols in programming to improve readability
and expedite the program development process. As a first step, they came up with the idea of
giving a symbolic name for each instruction. These names are called mnemonics, and a
program written using such mnemonics is called an assembly language program. Given below
is a typical 8086 assembly language program:
MOV AL, 5 Load AL reg with 5
ADD AL, 3 ; (AL) f- (AL) + 3
HLT ; Halt processing

From this example, it is clear that the usage of mnemonics (in our example MOV, ADD,
HLT are the mnemonics) improves the readability of our program significantly.
An assembly language program cannot be executed by a machine directly, as it is not in
binary form . Usually, we refer to a symbolic program as a source program. An assembler is
needed in order to translate an assembly language (source) program into the machine lan-
guage (object) executable by the machine. This is illustrated in Figure 1.18.

A ssembly
language Object
Program Result
Program
(text) (bin ary)

FIGURE 1.18 Assembly Process.

1.4.2.b High-Level Language Programming

Typical examples of high-level languages include FORTRAN, BASIC, Pascal, C and C++. The
program shown below is written in FORTRA..'\1, in order to obtain the sum of the first N natural
numbers:
READ (5, 10) N
10 FORMAT (I4)
NSUM = N* (N+1) /2
WRITE (2,10) NSUM
STOP
END
A translator called a compiler is needed to translate a program written in a high-level
language into binary form .

. . ______.~ I
'
Compiler I------.
data
....______,
IUniZl
______. ~ __.Result

FIGURE 1.19 Compilation process.

 36 Microprocessors and Microcomputer-Based System Design. 2nd Edition

.4.2.c Which Programming Language to Choose?

Compilers normally provide inefficient machine codes because of the general guidelines which
must be followed for designing them. It was found that a compiled high level language
generates many more lines of machine code than an equivalent assembly language program.
Therefore, the machine code program generated by the assembler will take up less memory
space and also wiU execute much faster.
Therefore, although the C language includes 1/0 instructions, applications involving 1/0 are
normally written in assembly language. One of the main uses of assembly language is in writing
programs for real-time applications. Real time applications means that the task required by the
application must be completed before any other input to the program can occur which will
change its operation.
High level languages are normally used for applications which require extensive mathemati-
cal computations. These applications include optimizations and other non-real time control
system applications.

1.5 Typical Microcomputer Addressing Modes and Instructions

In this chapter, some important characteristics and properties of microcomputer instruction
sets are discussed. Topics include addressing modes and instruction types .

1.5.1 Introduction
An instruction manipulates the stored data, and a sequence of instructions constitutes a
program. In general, an instruction has two components:
Op-code field
Operand field(s)
The op-code field specifies how data are to be manipulated.The op-code field may contain
data or a microprocessor register or a memory address. Consider the following instruction:

ADD Rl, RO
op-code field operand field
Assume that this microcomputer uses Rl as the source register and RO as the destination
register. The preceding instruction then adds the contents of registers RO and Rl and saves the
sum in register RO.
Depending on the number of addresses specified, one can have the following instruction
formats:
Three-operand
Two-operand
One-operand
Zero-operand
The 8-bit microprocessors include mostly one-operand instructions along with some zero-
and two-operand instructions. In 16-bit microprocessors, two-operand instructions are pre-
dominant although some zero- and one-operand instructions are present. The 32-bit micro-
processors include all four instruction formats.

1.5.2 Addressing Modes

The sequence of operations that a microprocessor has to carry out while executing an instruc-
tion is called its instruction cycle. One of the activities in an instruction cycle is the determina-
tion of the addresses of the operands involved in that instruction.
 Introduction to Microprocessors and Microcomputer-Based Applications 37

The way in which a microprocessor accomplishes this task is by recognizing the addressing
mode used in the instruction. Typical addressing modes supported by the instruction sets of
popular processors will be examined.
An instruction is said to have an inherent addressing mode if it is a zero-operand instruction.
As an example, consider the zero-operand instruction CLC which clears the carry flag to zero.
Whenever an instruction contains data in the operand field, it is called an immediate mode
instruction. For example, consider the following instruction:

ADD #25, Rl; Rl ~ Rl + 25

In this instruction, the symbol# indicates that it is an immediate-mode instruction. This

convention is adopted in the assemblers for processors such as MC68000.
An instruction is said to have an absolute addressing mode if it contains the address of the
operand. For example, consider the following move instruction:
MOVE 5000, R2; R2 ~ [5000]

This instruction copies the contents of memory location 5000 in the register R2.
An instruction is said to have a register mode if it contains a register in the operand field. For
example, consider the following register mode intruction.

ADD R2, R3; R3 ~ R2 + R3

This instruction uses register mode for both source and destination operands.
Whenever an instruction specifies a register that holds the address of an operand, the
resulting addressing mode is known as the register indirect mode. From this definition, it
follows that the Effective Address (EA) of an operand in the register-indirect mode is the
contents of the register R. More formally, this result is written as follows:
EA = [R]

To iJJustrate this idea clearly, consider the following instruction:

MOVE (R2) I (R3); [R3] ~ [R2]

Assume that the following configuration exists:

[R2] = 500016
[R3] = 4000 16
[5000] = 125616
[4000] = 462916
This instruction copies the contents of the memory location, whose address is specified by
the register R2, into the location whose address is specified by the register R3. Thus, after the
execution of this instruction, the memory location 4000 will contain the value 1256 16 .

1.5.3 Instruction Types

In general, instructions available in a processor may be broadly classified into five groups:
Data transfer instructions
Arithmetic instructions
Logical instructions
• Program control instructions
I/0 instructions
 38 Microprocessors and Microcomputer-Based System Design, 2nd Edition

Data transfer instructions are primarily concerned with data transfers between the micro-
processor registers or between register and memory. An example is MOVE RO, Rl which
transfers the contents of register RO to register Rl.
Typical arithmetic instructions include ADD and SUBTRACT instructions. For example,
ADD RO, Rl adds the contents of RO to Rl and stores the result in Rl.
Logical instructions perform Boolean AND, OR, NOT, and EXCLUSIVE-OR operations on
a bit-by-bit basis. An example is OR RO, Rl which logically ORs the contents of RO with Rl
and places the result in Rl.
Typical program control instructions include unconditional and conditional branch and
subroutine CALL instructions. For example, JMP 2035H unconditionally branches to the 16-
bit address 2035H.
1/0 instructions perform input and output operations. An example is IN PORTA which
inputs the contents of an 1/0 port called Port A into a microprocessor register such as the
accumulator.

1.6 Basic Features of Microcomputer Development Systems

A microcomputer development system is a tool that allows the designer to develop, debug,
and integrate error-free application software in microprocessor systems.
Development systems fall into one of two categories: systems supplied by the device manu-
facturer (non-universal systems)and systems built by after-market manufacturers (universal
systems). The main difference bet\veen the two categories is the range of microprocessors that
a system will accommodate. Non-universal systems are supplied by the microprocessor manu-
facturer (Intel, Motorola, RCA) and are limited to use for the particular microprocessor
manufactured by the supplier. In this manner, an Intel development system may not be used
to develop a Motorola-based system. The universal development systems (Hewlett-Packard,
Tektronix) can develop hardware and software for several microprocessors.
Within both categories of development systems, there are basically three types available: single-
user systems, time-shared systems, and net\vorked systems. A single-user system consists of one
development station that can be used by one user at a time. Single-user systems are low in cost and
may be sufficient for small systems development. Time-shared systems usually consist of a "dumb"-
type terminal connected by data Lines to a centralized microcomputer-based system that controls
all operations. A net\vorked ~ystem usually consists of a number of smart Cathode Ray Tubes
(CRTs) capable of performing most of the development work and can be connected over data lines
to a central microcomputer. The central microcomputer in a net\vork system usually is in charge
of allocating disk storage space and will download some programs into the user's work station
microcomputer. A microcomputer development system is a combination of the hardware neces-
sary for microprocessor design and the software to control the hardware. The basic components of
the hardware are the central processor, the CRT terminal, mass storage device (floppy or hard disk),
and usually an In-Circuit Emulator (ICE).
In a single-user system, the central processor executes the operating system software,
handles the Input/Output (I/0) facilities, executes the development programs (editor, assem-
bler, hnker), and aUocates storage space for the programs in execution. In a large multiuser
networked system the central processor may be responsible for mass storage allocation, while
a local processor may be responsible for the 1/0 facilities and execution of development
programs.
The CRT terminal provides the interface bet\veen the user and the operating system or
program under execution. The user enters commands or data via the CRT keyboard and the
program under execution displays data to the user via the CRT screen.
Each program (whether system software or user program) is stored in an ordered format on
disk. Each separate entry on the disk is called a file. The operating system software contains the
Introduction to Microprocessors and Microcomputer-Based Applications 39

routines necessary to interface between the user and the mass storage unit. When the user
requests a file by a specific file name, the operating system finds the program stored on disk
by the file name and loads it into main memory. More advanced development systems contain
memory management software that protects a user's files from unauthorized modification by
another user. This is accomplished via a unique user identification code called USER ID. A user
can only access files that have the user's unique code.
The equipment listed above comprises a basic development system, but most systems have
other devices such as printers and PROM programmers attached . A printer is needed to
provide the user with a hard copy record of the program under development.
After the application system software has been completely developed and debugged, it needs
to be permanently stored for execution in the target hardware. The EPROM programmer takes
the machine code and programs it into an EPROM. Erasable/Programmable Read Only
Memories (EPROMs) are more generally used in system development as they may be erased
and reprogrammed if the program changes. EPROM programmers usually interface to circuits
particularly designed to program a specific PROM. These interface boards are called person-
ality cards and are available for all the popular PROM configurations.
Most development systems support one or more in-circuit emulators (ICEs). The ICE is one
of the most advanced tools for microprocessor hardware development. To use an ICE, the
microprocessor chip is removed from the system under development (called the target
processor) and the emulator plugged into the microprocessor socket. The ICE will function-
ally and electrically act identically to the target processor with the exception that the ICE is
under the control of development system software. In this manner the development system
may exercise the hardware that is being designed and monitor all status information avail-
able about the operation of the target processor. Using an ICE, processor register contents
may be displayed on the CRT and operation of the hardware observed in a single-stepping
mode. In-circuit emulators can find hardware and software bugs quickly that might take
many hours using conventional hardware testing methods.
Architectures for development systems can be generally divided into two categories: the
master/slave configuration and the single-processor configuration . In a master/~lave configu-
ration, the master (host) processor controls all development functions such as editing, assem-
bling, and so on. The master processor controls the mass storage device and proces~es aU 1/0
(CRT, printer).
The software for the development systems is written for the m ;1ster proces~or which is
usually not the same as the slave (target) processor. The slave microprocessor is typically
connected to the user prototype via a 40-pin connector (the number varies with the processor)
which links the slave processor to the master processor.
Some development systems such as the HP 64000 completely :>eparate the system bus from
the emulation bus and therefore use a separate block of memory for emulation . This separa-
tion allows passive monitoring of the software executing on the target processor without
stopping the emulation process. A benefit of the separate emulation [Kilities allows the master
processor to be used for editing, assembling, and so on, while the slave proce~sor continues the
emulation. A designer may therefore start an emulation running, exit the emulator program,
and at some future time return to the emulation program.
Another advantage of the separate bus architecture is that an operating system needs to be
written only once for the master proce~sor and wi!J be med no matter what type of slave
processor is being emulated. When a new slave proce~sor is to be emulated, only the emulator
probe needs to be changed.
A disadvantage of the master/slave architecture is that it is expensive. In single-processor
architecture, only one processor is used for system operation and target emulation. The single
processor does both jobs of executing system software as weU as acting as the target processor.
Since there is only one processor involved, the system software must be rewritten for each type
40 Microprocessors and Microcomputer-Based System Design, 2nd Edition

of processor that is to be emulated. Since the system software must reside in the same memory
used by the emulator, not all memory will be available to the emulation process, which may
be a disadvantage when large prototypes are being developed. The single processor systems are
inexpensive.
The programs provided for microprocessor development are the operating system, editor,
assembler, linker, compiler, and debugger.
The operating system is responsible for executing the user's commands. The operating
system (such as UNIX) handles 1/0 functions, memory management, and loading of programs
from mass storage into RAM for execution.
The editor allows the user to enter the source code (either assembly language or some high-
level language) into the development system.
Almost all current microprocessor development systems use the character-oriented editor,
more commonly referred to as the screen editor. The editor is called a screen editor because
the text is dynamically displayed on the screen and the display automatically updates any edits
made by the user.
The screen editor uses the pointer concept to point to the character(s) that need editing. The
pointer in a screen editor is called the cursor and special commands allow the user to position
the cursor to any location displayed on the screen. When the cursor is positioned, the user may
insert characters, delete characters, or simply type over the existing characters.
Complete lines may be added or deleted using special editor commands. By placing the
editor in the insert mode, any text typed will be inserted at the cursor position when the cursor
is positioned between two existing lines. If the cursor is positioned on a line to be deleted, a
single command will remove the entire line from the file.
Screen editors implement the editor commands in different fashions. Some editors use
dedicated keys to provide some cursor movements. The cursor keys are usually marked with
arrows to show the direction of cursor movement.
More advanced editors (such as the HP 64000) use soft keys. A soft key is an unmarked key
located on the keyboard directly below the bottom of the CRT screen. The mode of the editor
decides what functions the keys are to perform. The function of each key is displayed on the
screen directly above the appropriate key. The soft key approach is valuable because it frees the
user from the problem of memorizing many different special control keys. The soft key
approach also allows the editor to reassign a key to a new function when necessary.
The source code generated on the editor is stored as ASCII or text characters and cannot be
executed by a microprocessor. Before the code can be executed, it must be converted to a form
acceptable by the microprocessor. An assembler is the program used to translate the assembly
language source code generated with an editor into object code (machine code) which may be
executed by a microprocessor.
Assemblers recognize four fields on each line of source code. The t!elds consist of a variable
number of characters and are identified by their position in the line. T he fields, from left to
right on a line, are the label field, the mnemonic or op-code field, the operand field, and the
comment field. Fields are separated by characters called delimiters which serve as a flag to the
assembler that one field is done and the next one is to start. Typical delimiters and their uses
are
space used to separate fields
TAB used to separate field s
used between addresses or data in the operand field
used before a comment statement
used after a label
A few typical lines of 8085 source code are
 Introduction to Microprocessors and Microcomputer-Based Applications 41

LABEL MNEMONIC OPERAND COMMENT

P':IELD P':IELD P':IELD P':IELD

MOV AL, 5 LOAD 5 :INTO AL

ADD AL,2 ADD 5 AND 2 , STORE RESULT :IN AL

As can be seen in the above example, tab keys are used instead of spaces to separate the fields
to give a more spread out line which is easier to read during debugging.
In order for the assembler to differentiate between numbers and labels, specific rules are set
up which apply to aU assemblers. A label must start with a letter. After the letter, a combination
ofletters and numbers (called alphanumerics) may be used. For example, when grouping Lines
of code by function, a common alphabetic string may be used followed by a unique number
for the label: LOOPO 1, LOOP02, LOOP 10, and so on.
A numeric quantity must start with a number, even though the number may be in hex
(which may start with a letter). Most assemblers assume that a number is expressed in the
decimal system and if another base is desired, a special code letter is used immediately
following the number. The usual letter codes used are

B binary
C octal
H hex (Motorola uses$ before the number)

To avoid confusion when hex quantities are used, a leading zero is inserted to tell the
assembler that the quantity is a number and not a label (for example, the quantity FA in hex
would be represented by OFAH in the source code).

Assembler Directives
Assembler directives are instructions entered into the source code along with the assembly
language. These directives do not get translated into object code but are used as special
instructions to the assembler to perform some special functions. The assembler will recognize
directives that assign memory space, assign addresses to labels, format the pages of the source
code, and so on.
The directive is usually placed in the op-code field . If any labels or data are required by the
directive, they are placed in the label or operand field as necessary.
Some common directives will now be discussed in detail.

a. ORIGIN (ORG). The ORG statement is used by the programmer when it is necessary to
place the program in a particular location in memory. As the assembler is translating the
source code, it keeps an internal counter (similar to the microprocessor program counter) that
keeps track of the address for the machine code. The counter is incremented automatically and
sequentially by the assembler. If the programmer wishes to alter the locations where the
machine code is going to be located, the ORG statement is used.
For example, if it is desired to have a subroutine at a particular location in memory, such
as 2000H, the statement ORG 2000H, would be placed immediately before the subroutine to
direct the assembler to alter the internal program counter.
Most assemblers will assume a starting address of zero if no ORG statement is given in the
source code.

b. EQUATE (EQU). The EQU instruction is used to assign the data value or address in the
operand field to the label in the label field. The EQU instruction is valuable because it allows
the programmer to write the source code in symbolic form and not be concerned with the
 42 Microprocessors and Microcomputer-Based System Design, 2nd Edition

numeric value needed. In some cases, the programmer is developing a program without
knowing what addresses or data may be required by the hardware. The program may be
written and debugged in symbolic form and the actual data added at a later time. Using the
EQU instruction is also helpful when a data value is used several times in a program. If, for
example, a counter value was loaded at ten different locations in the program, a symbolic label
(such as COUNT) could be used and the label count defined at the end of the program. By
using this technique, if it is found during debugging that the value in COUNT must be
changed, it need only be changed at the EQU instruction and not at each of the ten locations
where it is used in the program.

c. DEFTNE BYTE (DEFB or DB). The DB instruction is used to set a memory location to a
specific data value. The DB instruction is usually used to create data tables or to preset a flag
value used in a program. As the name implies, the DB instruction is used for creating an 8-bit
value.
For example, if a table of four values, 44H, 34H, 2SH, and OD3H, had to be created at
address 2000H , the following code could be written:
ORG 2000H ; SET TABLE ADDRESS
TABLE DB 44H,34H,25H,OD3H;PRESET TABLE VALUES
The commas are necessary for the assembler to be able to differentiate between data values.
When the code is assembled, the machine code would appear as follows:

2000 44
2001 34
2002 25
2003 D3

d. DEFINE WORD (DEFW or DW). Similarly to DB, DW defines memory locations to specific
values. As the name implies, the memory allotted is in word lengths which are usually 16 bits
wide. When assigning a 16-bit value to memory locations, two 8-bit memory locations must
be used . By convention, most assemblers store the least significant byte of the 16-bit value in
the first memory location and the most significant byte of the 16-bit value in the next memory
location. This technique is sometimes referred to as Intel style, because the first microproces-
sors were developed by Intel, and this storage method is how the Intel processors store 16-bit
words .
Data tables may be created with the DW instruction, but care must be taken to remember
the order in which the 16-bit words are stored. For example, consider the following table:
ORG 2500H
DATA DW 4000H, 2300H, 4BCAH

The machine code generated for this table would appear as folJows:

2500 00
2501 40
2502 00
2503 23
2504 CA
2505 4B
 Introduction to Microprocessors and Microcomputer-Based Applications 43

e. TITLE. TITLE is a formatting instruction that allows the user to name the program and have
the name appear on the source code listing. Consider the following line:

TITLE 'MULTIPLICATION ROUTINE'

When the assembler generates the program listing, each time it starts a new page the title
MULTIPLICATION ROUTINE appears at the top of each page.
Several types of assemblers are available, the most common types are discussed below.

a. One-Pass Assembler. The one-pass assembler was the first type to be developed and is
therefore the most primitive. Very few systems use a one-pass assembler because of the
inherent problem that only backward references may be used.
In a one-pass assembler the source code is processed only once. As the source code is
processed, any labels encountered are given an address and stored in a table. Therefore, when
the label is encountered again, the assembler may look backward to find the address of the
label. If the label has not been defined yet (for example, a jump instruction that jumps
forward), the assembler issues an error message.

b. Two-Pass Assembler. In the two-pass assembles, the source code is passed twice through the
assembler. The first pass made through the source code is specifically for the purpose of
assigning an address to aU labels. When aU labels have been stored in a table with the
appropriate addresses, a second pass is made to actually translate the source code into machine
code.
The two -pass style assembler is the most popular type of assembler currently in use.

c. Macroassembler. A macroassembler is a type of two-pass assembler that allows the program-

mer to write the source code in macros. A macro is a sequence of instructions that the
programmer gives a name. Whenever the programmer wishes to dupl.icate the sequence of
instructions, the macro name is inserted into the source code.

d. Cross Assemblers. A cross assembler may be of any of the types already mentioned. The
distinguishing feature of a cross assembler is that it is not written in the same language used
by the microprocessor that will execute the machine code generated by the assembler.
Cross assemblers are usually written in a high-levellanguage such as FORTRAN which wiiJ
make them machine independent. For example, an 8086 assembler may be written in FOR-
TRAN and then the assembler may be executed on another machine such as the Motorola
6800.

e. Metaassembler. The most powerful assembler is the metaassembler because it will support
many different microprocessors. The programmer merely specifies at the start of the source
code which microprocessor assembly language will be used and the metaassembler wiU trans-
late the source code to the correct machine code.
The output file from most development system assemblers is an object file. The object file
is usually relocatable code that may be configured to execute at any address . The function of
the linker is to convert the object file to an absolute file which consists of the actual machine
code at the correct address for execution. The absolute files thus created are used for debugging
and finally for programming EPROMs.
Debugging a microprocessor-based system may be divided into two categories: software
debugging and hardware debugging. Both debug processes are usually carried out separately
from each other because software debugging can be carried out on an Out-Of-Circuit-
Emulator (OCE) without having the final system hardware.
 44 Microprocessors and Microcomputer-Based System Design, 2nd Edition

The usual software development tools provided with the development system are
Single-step facility
Breakpoint facility

A single-stepper simply allows the user to execute the program being debugged one instruc-
tion at a time. By examining the register and memory contents during each step, the debugger
can detect such program faults as incorrect jumps, incorrect addressing, erroneous op codes,
and so on.
A breakpoint a.llows the user to execute an entire section of a program being debugged.
There are two types ofbreakpoint systems: hardware and software. The hardware breakpoint
uses hardware to monitor the system address bus and detect when the program is executing
the desired breakpoint location. When the breakpoint is detected, the hardware uses the
processor control Jines to either halt the processor for inspection or cause the processor to
execute an interrupt to a breakpoint routine. Hardware breakpoints can be used to debug both
ROM- and RAM -based programs. Software breakpoint routines may only operate on a system
with the program in RAM because the breakpoint instruction must be inserted into the
program that is to be executed .
Single-stepper and breakpoint methods complement each other. The user m ay insert a
breakpoint at the desired point a nd let the program execute up to that point. When the
program stops at the breakpoint the user may use a single-stepper to examine the program one
instruction at a time. Thus, the user can pinpoint the error in a program.
There are t\vo main hardware debugging tools: the logic analyzer and the in-circuit emula -
tor.
Logic analyzers are usually used to debug hardware faults in a system. T he logic analyzer is
the digital version of an oscilloscope because it allows the user to view logic levels in the
hardware.
In-circuit emulators can be used to debug and integrate software and hardware.
PC- based workstations are extensively used as development systems.

1.7 System Development Flowchart

T he total development of a microprocessor-based system typically involves three phases:
software design , hardware design, and program diagnostic design. A systems programmer will
be assigned the task of writing the application software, a logic designer will be assigned the
task of designing the hardware, and typically both designers will be assigned the task of
developing diagnostics to test the system. For small systems, one engineer may do all three
phases, while on large systems several engineers may be assigned to each phase. Figure 1.20
shows a flowchart for the total development of a system . Notice that software a nd hardware
development may occur in parallel to save time.

1.7.1 Software Development

The first step in developing the software is to take the system specificatio ns and write a
flowchart to accomplish the desired tasks that will implement the specifications.
The assembly language or high-level source code may now be written from the system
flowchart.
T he complete source code is then assembled . The asse mbler will check fo r syntax errors and
print error messages to help in the correction of errors.
T he normal o utput of an assembler is the object code and a program listing. The object code
will be used later by the linker. T he program listing may be sent to a disk file fo r use in
debugging or it may be directed to the printer.
Introduction to Microprocessors and Microcomputer-Based Applications 45

FIGURE 1.20 Microprocessor system developmen t flowchart.

The linker can now take the object code generated by the assembler and create the final
absolute code that will be executed on the target system. The emulation phase will take the
absolute code and load it into the development system RAM. From here, the program may be
debugged using breakpoints or single-stepping.
 46 Microprocessors and Microcomputer-Based System Design, 2nd Edition

1.7.2 Hardware Development

Working from the system specifications, a block diagram of the hardware must be developed.
The logic diagram and schematics may now be drawn using the block diagram as a guide.
A prototype may now be constructed and tested for wiring errors.
When the prototype has been constructed it may be debugged for correct operation using
standard electronic testing equipment such as oscilloscopes, meters, logic probes, and logic
analyzers, all with test programs created for this purpose.
After the prototype has been debugged electrically, the development system in-circuit emulator
may be used to check it functionally. The ICE will verify memory map, correct 1/0 operation, and
so on.
The next step in the system development is to validate the complete system by running
operational checks on the prototype with the finalized application software installed. The
EPROM is then programmed with the error-free programs.

1.8 Typical Microprocessors

Intel and Motorola established the standard for future microprocessors.
Both Intel and Motorola introduced popular 8-bit microprocessors, namely, Intel 8080/
8085, and Motorola 6800/6809 in the mid 1970's. These microprocessors are capable of
directly addressing 64k of memory and were popular for several years. They are still being
utilized in many inexpensive low-speed applications.
In 1978, Intel introduced its first 16-bit microprocessor, the Intel 8086. Several variations
of the Intel 16-bit microprocessor family include the 8088,80186/80188 and 80286. The 8088
is similar to the 8086 except that the 8088 has an 8-bit data bus. Both the 8086 and 8088 can
run at 5 Mhz. They are packaged in 40 pins and can directly address one megabyte of memory.
In 1982, Intel introduced an enhanced version of the 8086/8088 which is the Intel 80186/
80188. The 80186 has a 16-bit data bus while the 80188 has an 8-bit data bus. The 80186/80188
can operate at 8 Mhz (80186), 6 Mhz (80186-6) and other frequencies. The 80186 integrates
the 8086 and several new functional units into a single chip. The new on-chip components
include a clock generator, two DMA channels, interrupt controller, address decoding, and
three 16-bit programmable timers. Like the 8086, the 80186 can directly address one megabyte
of memory. The 80186 is housed in a 68-pin leadless package.
The 80286 is Intel's other 16-bit microprocessor with on-chip memory protection capability
primarily designed for multiuser/multitasking systems and introduced virtual memory.
Intel's 32-bit microprocessor family includes the 80386, 80486, and Pentium. The 80386
includes an on-chip memory management unit while the 80486 (DX and DX2) contains all the
features of the 80386 along with floating-point hardware in the same chip. The Pentium, on
the other hand, is a superscalar processor. This means that it includes dual pipelining and
executes more than one instruction per cycle.
Soon after introduction of the Intel 8086, Motorola released its first 16-bit microprocessor, the
68000.1t is housed in 64-pin or 68-pin package with a direct addressing capability of 16 megabytes.
The 68008 is similar to the 68000 except that the 68000 has a 16-bit data bus while the 68008 has
an 8-bit data bus. Also, the 68008 can directly address one megabyte of memory. The 68010 and
68012 are 16-bit microprr::essors similar to the Intel80286 and provide on-chip memory manage-
ment support. Motorola CPU 32 is an t>nhanced 68000 along with many features of the 16-bit 68010
and the 32-bit 68020. The CPU 32 can ·' 1pport high level languages and is suited for controller
applications. For example, in applic.:tions where power consumption is a consideration, the
CPU32 forces the device into a low-power standby mode when immediate processing is not
required upon execution of the LPSTOP instruction. Also, to maximize throughput for real-
time applications, reference data is often precalculated and stored in memory for quick access
upon execution of the TBL instruction.
 Introduction to Microprocessors and Microcomputer-Based Applications 47

Motorola's 32-bit microprocessor family includes the 68020, 68030, and 68040.
Since 1988, Intel, Morotola, and others have been introducing the RISC microprocessors.
Some of these are the Intel 80960 family, the Motorola MC88100, the Apple/IBM/Motorola
PowerPC, and Digital Equipment Corporation's Alpha 21164. The 80960 and 88100 are 32-
bit microprocessors. They can directly address 4 gigabytes of memory. The Power PC family,
on the other hand, includes both 32-bit and 64-bit microprocessors. The 80960 and 88100
include a 32-bit data bus while the Power PC contains a 64-bit data bus. The PowerPc is based
on IBM PowerPC architecture and Motorola's 88100 bus interface design. These RISC micro-
processors find extensive applications in embedded controls such as laser printers.
The PowerPC 601 outperforms and under-prices the Pentium but to be successful must
build up its selection of software applications. Note that the Pentium had a flaw in its division
algorithm caused by a problem with a Lookup table used in the division. Intel recently
corrected this problem.
Tables 1.2a and 1.2b provide a brief description oflntel and Motorola's typical 16- and 32-
bit microprocessors.

1.9 Typical Practical Applications

Microprocessors are being extensively used in a wide variety of applications. Typical applica-
tions include dedicated controllers, personal workstations, and real-time robotics control.
Some of these applications are described in the following.

1.9.1 Personal Workstations

Personal workstations are designed using the high-performance 16- and 32-bit microproces-
sors. A dedicated single user (rather than multiple users sharing resources of a single micro-
computer) can obtain significant computing power from these workstations.
The state-of-the-art workstations use 32-bit microprocessors to provide certain sophisti-
cated functions such as IC layout, 3D graphics, and stress analysis.

1.9.2 Fault-Tolerant Systems

In many applications such as control of life-critical systems, control of nuclear waste, and
unattended remote system operation, the reliability of the hardware is of utmost importance.
The need for such reliable systems resulted in fault-tolerant systems. These systems use
redundant computing units to provide reliable operation. However, the cost of fault-tolerant

Table 1.2a Intel 16-bit microprocessors

8086 8088 80286

Introduced June 1978 June 1978 Feb. 1982

Maximum clock speed 10 Mhz 10 Mhz 20 Mhz
On-chip cache No No No
MIPS (Millions of Instructions 0.33 0.33 1.2
Per Second)
Addressing Modes' 8 8 8
Transistors 29,000 29,000 134,000
Data Bus 16-bit 8-bit 16-bit
Address Bus 20-bit 20-bit 24-bit
Directly Addressable memory One megabyte One megabyte Sixteen megabytes
Number of pins 40 40 68
Virtual Memory No No Yes; One gigabyte per task
On-Chip memory management No No Yes
and protection
Math Coprocessor Interface 8087 8087 80287XL/XLT

• Addressing modes include register, immediate, and memory modes.

 48 Microprocessors and Microcomputer-Based System Design, 2nd Edition

Table 1.2a Intel 32-bit microprocessors

80386DX 80386SX 486DX 486SX 486DX2 Pentium

Introduced October 1985 June 1988 April 1989 April 1991 March 1992 May 1993
Maximum clock speed 40 Mbz 33 Mbz 50 Mbz 25 Mhz 66 Mhz 100 Mhz
MIPS 6 2.5 20 16.5 40 112
Transistor 275,000 275 ,000 1.2 Millions 1.185 Mill ions 1.2 Millions 3.1 Millions
On-ch.ip cache memory Support Support Yes Yes Yes Yes
chips avaJiable chips avaliable
Data Bus 32-bit 16-bit 32-bit 32-bit 32-bit 64-bit
Address Bus 32-bit 24-bit 32-bit 32-bit 32-bit 32-bit
Directly Addressable 4 gigabytes 16 megabytes 4 gigabytes 4 gigabytes 4 gigabytes 4 gigabytes
Memory
Pins 132 100 168 168 168 273
Virtual Memory Yes Yes Yes Yes Yes Yes
On-chip Memory Yes Yes Yes Yes Yes Yes
Management and

..
Protection
Addressing Modes• 11 II II II 11 11
Floating-point 387DX 387SX 487SX

• Addressing modes include register, immediate, and memory modes.

'* Indicates on-chip floating point.
Note that the 80386SL is also a 32-bit microprocessor with a 16-but data bus like the 80386SX (not listed in the table above) .
The 80386SL can run at a speed of up to 25 MHz and has a direct addressing capabiliry of 32 megabytes. The 80386SL provides
virtual memory support along with on-chip memory management and protection. It can be interfaced to the 80387SX to
provide floating-point support. The 80386SL includes an on-chip disk controller hardware.

Table 1.2b Motorola 16-bit Microprocessors

MC68000 MC68010 CPU32

Maximum Clock Speed 25 Mhz 25 Mhz 16.67 Mhz

Pins 64,68 64,68 64, 68
Data Bus 16-bit 16-bit 16-bit
Virtual Memory No Yes Yes
Directly Addressable 16 Megabytes 16 Megabytes 16 Megabytes
Memory
Control Registers None 3 3
Stack Pointers 2 2 2
Cache No No No
Addressing Modes 14 14 16
Coprocessor Interface No on-chip hardware No on-chip hardware No on-chip hardware

Table 1.2b Motorola 32-bit Microprocessors

MC68020 MC68030 MC68040

Maximum Clock Speed 33 Mhz (8 Mhz min.) 33 Mhz (8 Mhz min.) 33 Mhz (8 Mhz min.)
Pins 114 118 179
Address Bus 32-bit 32-bit 32-bit
Addressing Modes 18 18 18
Maximum Addressable 4 Gigabytes 4 Gigabytes 4 Gigabytes
Memory
Memory Management By interfacing the 68851 On-chip M.\1U On-chip MMU
MMU chip
Cache (on-chip) Instruction cache Instruction and data cache Instruction and data cache
Floating Point By interfacing 68881/68882 By interfacing 68881/68882 On-chip floating-point
floating-point coprocessor floating-point coprocessor hardware
chip chip
 Introduction to Microprocessors and Microcomputer-Based Applications 49

systems can be very high if the performance requirements of the application need high-
performance VAX-type computers. Since the performance levels of32-bit microprocessors are
comparable to the V AX-type computer, multiple 32-bit microprocessors in a redundant
configuration outperform the V A.Xs. Thus, the 32-bit microprocessors provide efficient fault -
tolerant systems.

1. 9.3 Real-Time Controllers

Real-time controllers such as flight-control systems for aircraft, flight simulators, and automo -
bile engine control require high-performance computers. Some of these applications were
handled in the past by using mainframe computers which resulted in high cost and the
controllers occupied large spaces.
The state-of-the-art flight simulators use multiple 32-bit microprocessors to perform graphic
manipulation, data gathering, and high-speed communications. Obviously, an application such
as real-time automobile engine control using mainframe computers is not practical since these
systems are not small enough to fit under a car hood . These controllers are currently being
designed using the small-sized 32-bit microprocessors to perform high-speed data manipulation
and ca.lculation.

1.9.4 Robotics
The processing requirements of complex robots attempting to emulate human activities
exceed the capabilities of 8- and 16-bit microprocessors. With 32-bit microprocessors, it is
now feasible to design these controllers at low cost. In many cases, the microprocesso r is used
as the brain of the robot. In a typical application, the microprocessor will in put the actual arm
angle measurement from a sensor, compare it with the desired arm angle, and will then send
outputs to a motor to position the arm .
Mitsubishi manufactured the first 68020-based system robot control system.

1.9.5 Embedded Control

Embedded Control microprocessor~ , abo called embedded co ntrollers, are designed to be
programmed to manage specific tasks. Once programmed, the embedded controllers ca n
manage the functions of a wide variety of electronic products. Since the microprocesso rs are
embedded in the host sv,;tem, their presence and operation are basically hidden from the host
system . Typical embedded control applications include office automation products such as
copiers, laser printers, fax machines, and consumer electronics like VCRs, micro wave ovens,
and automative systems.
There are two types of embedded control applications, event control ( real-time) and d ata
control. Even control applications require distributed embedded controllers dedicated to
single functions.
These applications include motor engine or instrument control system. In these applica-
tions, the controllers offer re.1l-time respunse to support programs wi th small amo unts of data.
Typically, 8- and 16-bit single chip microcontroUers such as the Intel 875 1/8096 and Moto rol a
HCII / HC16 are used.
The 80186/80188 based microcontrollers are used for data con trol applications.
RISC microprocessor-based embedded controllers perform m any d ifferent fu nctions whi le
handling large programs using large amounts of data . Applications such as laser printers
require a high performance microprocessor with on-chip tloating-point hardware. The RISC
microprocessors are ideal for these types of applications.
52 Microprocessors and Microcomputer-Based System Design. 2nd Editior

Ll6 Discuss the main features of typical coprocessors.

LI7 What is the difference between software breakpoint and hardware breakpoint?

Ll8 Discuss the basic features of microcomputer development systems.

Ll9 Compare the typical features of the 16- and 32-bit microprocessors by Intel anc
Motorola.

L20 What types of applications are the RlSC microprocessors used for?

L21 Discuss floating-point data formats supported by both Intel 80387 and Motorol<
68881/6882.
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